From d6c4f6128c880a4e8054bde795fd15d85801da4e Mon Sep 17 00:00:00 2001
From: asterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Fri, 10 Jun 2011 10:13:01 +0000
Subject: [PATCH] Move the pdc definition in separate file and comply the other
 headers.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4947 38d2e660-2303-0410-9eaa-f027e97ec537
---
 bertos/cpu/cortex-m3/io/sam3.h      | 34 +++++++--------
 bertos/cpu/cortex-m3/io/sam3_dacc.h | 41 ++++++------------
 bertos/cpu/cortex-m3/io/sam3_pdc.h  | 65 +++++++++++++++++++++++++++++
 3 files changed, 93 insertions(+), 47 deletions(-)
 create mode 100644 bertos/cpu/cortex-m3/io/sam3_pdc.h

diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index beba6793..24fefc00 100644
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -137,25 +137,8 @@
 	#error undefined U(S)ART_PORTS for this cpu
 #endif
 
-/* PDC registers */
-#define PERIPH_RPR_OFF  0x100  // Receive Pointer Register.
-#define PERIPH_RCR_OFF  0x104  // Receive Counter Register.
-#define PERIPH_TPR_OFF  0x108  // Transmit Pointer Register.
-#define PERIPH_TCR_OFF  0x10C  // Transmit Counter Register.
-#define PERIPH_RNPR_OFF 0x110  // Receive Next Pointer Register.
-#define PERIPH_RNCR_OFF 0x114  // Receive Next Counter Register.
-#define PERIPH_TNPR_OFF 0x118  // Transmit Next Pointer Register.
-#define PERIPH_TNCR_OFF 0x11C  // Transmit Next Counter Register.
-#define PERIPH_PTCR_OFF 0x120  // PDC Transfer Control Register.
-#define PERIPH_PTSR_OFF 0x124  // PDC Transfer Status Register.
-
-#define PDC_RXTEN  0
-#define PDC_RXTDIS 1
-#define PDC_TXTEN  8
-#define PDC_TXTDIS 9
-
-
 #include "sam3_sysctl.h"
+#include "sam3_pdc.h"
 #include "sam3_pmc.h"
 #include "sam3_smc.h"
 #include "sam3_sdramc.h"
@@ -173,6 +156,7 @@
 #include "sam3_dacc.h"
 #include "sam3_tc.h"
 #include "sam3_twi.h"
+#include "sam3_ssc.h"
 
 /**
  * U(S)ART I/O pins
@@ -304,5 +288,19 @@
 	#define TWI1_TWCK   25
 #endif
 
+#if CPU_CM3_SAM3X
+	#define SSC_PORT            PIOA_BASE
+	#define SSC_RECV_PERIPH     PIO_PERIPH_A
+	#define SSC_TRAN_PERIPH     PIO_PERIPH_B
+	#define SSC_RD              18
+	#define SSC_RF              17
+	#define SSC_RK              19
+	#define SSC_TD              16
+	#define SSC_TF              15
+	#define SSC_TK              14
+#else
+	#error no ssc pins are defined for this cpu
+#endif
+
 /*\}*/
 #endif /* SAM3_H */
diff --git a/bertos/cpu/cortex-m3/io/sam3_dacc.h b/bertos/cpu/cortex-m3/io/sam3_dacc.h
index 562d5f49..e2071dd7 100644
--- a/bertos/cpu/cortex-m3/io/sam3_dacc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_dacc.h
@@ -41,6 +41,8 @@
 #ifndef SAM3_DACC_H
 #define SAM3_DACC_H
 
+#include <io/cm3.h>
+
 /** DACC registers base. */
 #define DACC_BASE               0x400C8000
 
@@ -184,35 +186,16 @@
  * DMA controller for DACC
  * DACC PDC register.
  */
-#define DACC_RPR_OFF                     0x100 ///< Receive Pointer Register.
-#define DACC_RPR        (*((reg32_t*) (DACC_BASE + DACC_RPR_OFF)))    ///< Receive Pointer Register.
-
-#define DACC_RCR_OFF                     0x104 ///< Receive Counter Register.
-#define DACC_RCR       (*((reg32_t*) (DACC_BASE + DACC_RCR_OFF)))   ///<  Receive Counter Register.
-
-#define DACC_TPR_OFF                     0x108 ///< Transmit Pointer Register.
-#define DACC_TPR       (*((reg32_t*) (DACC_BASE + DACC_TPR_OFF)))   ///<  Transmit Pointer Register.
-
-#define DACC_TCR_OFF                     0x10C ///< Transmit Counter Register.
-#define DACC_TCR       (*((reg32_t*) (DACC_BASE + DACC_TCR_OFF)))   ///< Transmit Counter Register.
-
-#define DACC_RNPR_OFF                    0x110 ///< Receive Next Pointer Register.
-#define DACC_RNPR      (*((reg32_t*) (DACC_BASE + DACC_RNPR_OFF)))   ///< Receive Next Pointer Register.
-
-#define DACC_RNCR_OFF                    0x114 ///< Receive Next Counter Register.
-#define DACC_RNCR      (*((reg32_t*) (DACC_BASE + DACC_RNCR_OFF)))   ///< Receive Next Counter Register.
-
-#define DACC_TNPR_OFF                    0x118 ///< Transmit Next Pointer Register.
-#define DACC_TNPR      (*((reg32_t*) (DACC_BASE + DACC_TNPR_OFF)))   ///< Transmit Next Pointer Register.
-
-#define DACC_TNCR_OFF                    0x11C ///< Transmit Next Counter Register.
-#define DACC_TNCR      (*((reg32_t*) (DACC_BASE + DACC_TNCR_OFF)))   ///< Transmit Next Counter Register.
-
-#define DACC_PTCR_OFF                    0x120 ///< Transfer Control Register.
-#define DACC_PTCR      (*((reg32_t*) (DACC_BASE + DACC_PTCR_OFF)))  ///< Transfer Control Register.
-
-#define DACC_PTSR_OFF                    0x124 ///< Transfer Status Register.
-#define DACC_PTSR      (*((reg32_t*) (DACC_BASE + DACC_PTSR_OFF)))    ///< Transfer Status Register.
+#define DACC_RPR       (*((reg32_t*) (DACC_BASE + PERIPH_RPR_OFF)))  ///< Receive Pointer Register.
+#define DACC_RCR       (*((reg32_t*) (DACC_BASE + PERIPH_RCR_OFF)))  ///<  Receive Counter Register.
+#define DACC_TPR       (*((reg32_t*) (DACC_BASE + PERIPH_TPR_OFF)))  ///<  Transmit Pointer Register.
+#define DACC_TCR       (*((reg32_t*) (DACC_BASE + PERIPH_TCR_OFF)))  ///< Transmit Counter Register.
+#define DACC_RNPR      (*((reg32_t*) (DACC_BASE + PERIPH_RNPR_OFF))) ///< Receive Next Pointer Register.
+#define DACC_RNCR      (*((reg32_t*) (DACC_BASE + PERIPH_RNCR_OFF))) ///< Receive Next Counter Register.
+#define DACC_TNPR      (*((reg32_t*) (DACC_BASE + PERIPH_TNPR_OFF))) ///< Transmit Next Pointer Register.
+#define DACC_TNCR      (*((reg32_t*) (DACC_BASE + PERIPH_TNCR_OFF))) ///< Transmit Next Counter Register.
+#define DACC_PTCR      (*((reg32_t*) (DACC_BASE + PERIPH_PTCR_OFF))) ///< Transfer Control Register.
+#define DACC_PTSR      (*((reg32_t*) (DACC_BASE + PERIPH_PTSR_OFF))) ///< Transfer Status Register.
 
 
 #define DACC_PTCR_RXTEN               0  ///< DACC_PTCR  Receiver Transfer Enable.
diff --git a/bertos/cpu/cortex-m3/io/sam3_pdc.h b/bertos/cpu/cortex-m3/io/sam3_pdc.h
new file mode 100644
index 00000000..cb261cf3
--- /dev/null
+++ b/bertos/cpu/cortex-m3/io/sam3_pdc.h
@@ -0,0 +1,65 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \author Daniele Basile <asterix@develer.com>
+ *
+ *  SAM3X PDC register definitions.
+ */
+
+#ifndef SAM3_PDC_H
+#define SAM3_PDC_H
+
+
+/**
+ * PDC controller offset
+ */
+#define PERIPH_RPR_OFF                     0x100 ///< Receive Pointer Register.
+#define PERIPH_RCR_OFF                     0x104 ///< Receive Counter Register.
+#define PERIPH_TPR_OFF                     0x108 ///< Transmit Pointer Register.
+#define PERIPH_TCR_OFF                     0x10C ///< Transmit Counter Register.
+#define PERIPH_RNPR_OFF                    0x110 ///< Receive Next Pointer Register.
+#define PERIPH_RNCR_OFF                    0x114 ///< Receive Next Counter Register.
+#define PERIPH_TNPR_OFF                    0x118 ///< Transmit Next Pointer Register.
+#define PERIPH_TNCR_OFF                    0x11C ///< Transmit Next Counter Register.
+#define PERIPH_PTCR_OFF                    0x120 ///< Transfer Control Register.
+#define PERIPH_PTSR_OFF                    0x124 ///< Transfer Status Register.
+
+
+#define PDC_PTCR_RXTEN               0  ///< Receiver Transfer Enable.
+#define PDC_PTCR_RXTDIS              1  ///< Receiver Transfer Disable.
+#define PDC_PTCR_TXTEN               8  ///< Transmitter Transfer Enable.
+#define PDC_PTCR_TXTDIS              9  ///< Transmitter Transfer Disable.
+#define PDC_PTSR_RXTEN               0  ///< Receiver Transfer Enable.
+#define PDC_PTSR_TXTEN               8  ///< Transmitter Transfer Enable.
+
+
+#endif /* SAM3_PDC_H */
-- 
2.25.1