From da0ee63685fa7ddd25d99225178b396601773c79 Mon Sep 17 00:00:00 2001 From: asterix Date: Thu, 21 Feb 2008 18:09:59 +0000 Subject: [PATCH] Fix paste bug. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@1146 38d2e660-2303-0410-9eaa-f027e97ec537 --- cpu/arm/io/at91_tc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu/arm/io/at91_tc.h b/cpu/arm/io/at91_tc.h index 5a9772eb..080d5881 100644 --- a/cpu/arm/io/at91_tc.h +++ b/cpu/arm/io/at91_tc.h @@ -269,9 +269,9 @@ #define TC2_IDR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IDR_OFF))) ///< Channel 2 interrupt disable register address. #define TC_IMR_OFF 0x0000002C ///< Interrupt Mask Register offset. -#define TC0_IMR (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_SR_OFF))) ///< Channel 0 interrupt mask register address. -#define TC1_IMR (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_SR_OFF))) ///< Channel 1 interrupt mask register address. -#define TC2_IMR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_SR_OFF))) ///< Channel 2 interrupt mask register address. +#define TC0_IMR (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IMR_OFF))) ///< Channel 0 interrupt mask register address. +#define TC1_IMR (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IMR_OFF))) ///< Channel 1 interrupt mask register address. +#define TC2_IMR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IMR_OFF))) ///< Channel 2 interrupt mask register address. #define TC_COVFS 0 ///< Counter overflow flag. #define TC_LOVRS 1 ///< Load overrun flag. -- 2.25.1