From e444d916197e4345dd2bbd85800d8544c2699096 Mon Sep 17 00:00:00 2001 From: aleph Date: Fri, 15 Oct 2010 19:55:25 +0000 Subject: [PATCH 1/1] sam3n: update clock and kdebug modules to use lastest register definion convention git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4434 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/drv/clock_sam3.c | 37 ++++++++++++++------------ bertos/cpu/cortex-m3/drv/kdebug_sam3.c | 36 ++++++++++++------------- 2 files changed, 38 insertions(+), 35 deletions(-) diff --git a/bertos/cpu/cortex-m3/drv/clock_sam3.c b/bertos/cpu/cortex-m3/drv/clock_sam3.c index 25f0f986..dfb2eb24 100644 --- a/bertos/cpu/cortex-m3/drv/clock_sam3.c +++ b/bertos/cpu/cortex-m3/drv/clock_sam3.c @@ -36,9 +36,12 @@ */ #include "clock_sam3.h" -#include #include #include +#include +#include +#include +#include /* Frequency of board main oscillator */ @@ -90,45 +93,45 @@ void clock_init(void) uint32_t timeout; /* Disable watchdog */ - WDT_MR = WDT_MR_WDDIS; + WDT_MR = BV(WDT_WDDIS); /* Set 4 wait states for flash access, needed for higher CPU clock rates */ - EFC_FMR = EEFC_FMR_FWS(3); + EEFC_FMR = EEFC_FMR_FWS(3); // Select external slow clock - if (!(SUPC_SR & SUPC_SR_OSCSEL)) + if (!(SUPC_SR & BV(SUPC_SR_OSCSEL))) { - SUPC_CR = SUPC_CR_XTALSEL | SUPC_CR_KEY(0xA5); - while (!(SUPC_SR & SUPC_SR_OSCSEL)); + SUPC_CR = BV(SUPC_CR_XTALSEL) | SUPC_CR_KEY(0xA5); + while (!(SUPC_SR & BV(SUPC_SR_OSCSEL))); } // Initialize main oscillator - if (!(PMC_MOR & CKGR_MOR_MOSCSEL)) + if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL))) { - PMC_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN); timeout = CLOCK_TIMEOUT; - while (!(PMC_SR & PMC_SR_MOSCXTS) && --timeout); + while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout); } // Switch to external oscillator - PMC_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL); timeout = CLOCK_TIMEOUT; - while (!(PMC_SR & PMC_SR_MOSCSELS) && --timeout); + while (!(PMC_SR & BV(PMC_SR_MOSCSELS)) && --timeout); - PMC_MCKR = (PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + PMC_MCKR = (PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_MASK) | PMC_MCKR_CSS_MAIN_CLK; timeout = CLOCK_TIMEOUT; - while (!(PMC_SR & PMC_SR_MCKRDY) && --timeout); + while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); // Initialize and enable PLL clock - PMC_PLLR = evaluate_pll() | CKGR_PLLR_STUCKTO1 | CKGR_PLLR_PLLCOUNT(0x1); + CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x1); timeout = CLOCK_TIMEOUT; - while (!(PMC_SR & PMC_SR_LOCK) && --timeout); + while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout); PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK; timeout = CLOCK_TIMEOUT; - while (!(PMC_SR & PMC_SR_MCKRDY) && --timeout); + while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); PMC_MCKR = PMC_MCKR_CSS_PLL_CLK; timeout = CLOCK_TIMEOUT; - while (!(PMC_SR & PMC_SR_MCKRDY) && --timeout); + while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); } diff --git a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c index d9880d34..80e5501f 100644 --- a/bertos/cpu/cortex-m3/drv/kdebug_sam3.c +++ b/bertos/cpu/cortex-m3/drv/kdebug_sam3.c @@ -42,24 +42,24 @@ #if CONFIG_KDEBUG_PORT == 0 - #define UART_BASE UART0 - #define UART_INT UART0_IRQn - #define UART_PIO_BASE PIOA - #define UART_PINS (GPIO_UART0_RX_PIN | GPIO_UART0_TX_PIN) + #define UART_BASE UART0_BASE + #define UART_INT INT_UART0 + #define UART_PIO_BASE PIOA_BASE + #define UART_PINS (BV(RXD0) | BV(TXD0)) #elif (CONFIG_KDEBUG_PORT == 1) && !defined(CPU_CM3_AT91SAM3U) - #define UART_BASE UART1 - #define UART_INT UART1_IRQn - #define UART_PIO_BASE PIOB - #define UART_PINS (GPIO_UART1_RX_PIN | GPIO_UART1_TX_PIN) + #define UART_BASE UART1_BASE + #define UART_INT INT_UART1 + #define UART_PIO_BASE PIOB_BASE + #define UART_PINS (BV(RXD1) | BV(TXD1)) #else #error "UART port not supported in this board" #endif // TODO: refactor serial simple functions and use them, see lm3s kdebug -#define KDBG_WAIT_READY() while (!(UART_BASE->UART_SR & UART_SR_TXRDY)) {} -#define KDBG_WAIT_TXDONE() while (!(UART_BASE->UART_SR & UART_SR_TXEMPTY)) {} +#define KDBG_WAIT_READY() while (!(HWREG(UART_BASE + UART_SR_OFF) & BV(UART_SR_TXRDY))) {} +#define KDBG_WAIT_TXDONE() while (!(HWREG(UART_BASE + UART_SR_OFF) & BV(UART_SR_TXEMPTY))) {} -#define KDBG_WRITE_CHAR(c) do { UART_BASE->UART_THR = (c); } while(0) +#define KDBG_WRITE_CHAR(c) do { HWREG(UART_BASE + UART_THR_OFF) = (c); } while(0) /* Debug unit is used only for debug purposes so does not generate interrupts. */ #define KDBG_MASK_IRQ(old) do { (void)old; } while(0) @@ -73,22 +73,22 @@ typedef uint32_t kdbg_irqsave_t; INLINE void kdbg_hw_init(void) { /* Disable PIO mode and set appropriate UART pins peripheral mode */ - UART_PIO_BASE->PIO_PDR = UART_PINS; - UART_PIO_BASE->PIO_ABCDSR[0] &= ~UART_PINS; - UART_PIO_BASE->PIO_ABCDSR[1] &= ~UART_PINS; + HWREG(UART_PIO_BASE + PIO_PDR_OFF) = UART_PINS; + HWREG(UART_PIO_BASE + PIO_ABCDSR1_OFF) &= ~UART_PINS; + HWREG(UART_PIO_BASE + PIO_ABCDSR2_OFF) &= ~UART_PINS; /* Enable the peripheral clock */ PMC_PCER |= BV(UART_INT); /* Reset and disable receiver & transmitter */ - UART_BASE->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS; + HWREG(UART_BASE + UART_CR_OFF) = BV(UART_CR_RSTRX) | BV(UART_CR_RSTTX) | BV(UART_CR_RXDIS) | BV(UART_CR_TXDIS); /* Set mode: normal, no parity */ - UART_BASE->UART_MR = UART_MR_PAR_NO; + HWREG(UART_BASE + UART_MR_OFF) = UART_MR_PAR_NO; /* Set baud rate */ - UART_BASE->UART_BRGR = CPU_FREQ / CONFIG_KDEBUG_BAUDRATE / 16; + HWREG(UART_BASE + UART_BRGR_OFF) = CPU_FREQ / CONFIG_KDEBUG_BAUDRATE / 16; /* Enable receiver & transmitter */ - UART_BASE->UART_CR = UART_CR_RXEN | UART_CR_TXEN; + HWREG(UART_BASE + UART_CR_OFF) = BV(UART_CR_RXEN) | BV(UART_CR_TXEN); } -- 2.25.1