From e4f77ad0d0b668029e0400412ea8628bc005a583 Mon Sep 17 00:00:00 2001
From: arighi <arighi@38d2e660-2303-0410-9eaa-f027e97ec537>
Date: Tue, 4 May 2010 08:55:13 +0000
Subject: [PATCH] STM32: add GPIO driver.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3606 38d2e660-2303-0410-9eaa-f027e97ec537
---
 bertos/cpu/cortex-m3/drv/gpio_stm32.c | 107 ++++++++++++++++++++++++++
 bertos/cpu/cortex-m3/drv/gpio_stm32.h | 102 ++++++++++++++++++++++++
 2 files changed, 209 insertions(+)
 create mode 100644 bertos/cpu/cortex-m3/drv/gpio_stm32.c
 create mode 100644 bertos/cpu/cortex-m3/drv/gpio_stm32.h

diff --git a/bertos/cpu/cortex-m3/drv/gpio_stm32.c b/bertos/cpu/cortex-m3/drv/gpio_stm32.c
new file mode 100644
index 00000000..f15145a4
--- /dev/null
+++ b/bertos/cpu/cortex-m3/drv/gpio_stm32.c
@@ -0,0 +1,107 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief STM32 GPIO control interface.
+ *
+ * \author Andrea Righi <arighi@develer.com>
+ */
+
+#include <cfg/compiler.h>
+#include <cfg/debug.h>
+#include <io/stm32.h>
+#include "gpio_stm32.h"
+
+/**
+ * Configure a GPIO pin
+ *
+ * \param base Base address of the GPIO port
+ * \param pins Bit-packed representation of the pin(s)
+ * \param mode Pin(s) configuration mode
+ * \param speed Output drive speed
+ *
+ * Return 0 on success, otherwise a negative value.
+ */
+int stm32_gpioPinConfig(struct stm32_gpio *base,
+			uint16_t pins, uint8_t mode, uint8_t speed)
+{
+	uint32_t reg_mode = mode & 0x0f;
+	int i;
+
+	if (mode & 0x10)
+		reg_mode |= speed;
+
+	if (pins & 0xff)
+	{
+		uint32_t reg = base->CRL;
+
+		for (i = 0; i < 8; i++)
+		{
+			uint32_t pos = 1 << i;
+
+			if (pins & pos)
+			{
+				pos = i << 2;
+				reg &= ~(0x0f << pos);
+				reg |= reg_mode << pos;
+
+				if (mode == GPIO_MODE_IPD)
+					base->BRR = 0x01 << i;
+				if (mode == GPIO_MODE_IPU)
+					base->BSRR = 0x01 << i;
+			}
+		}
+		base->CRL = reg;
+	}
+	if (pins > 0xff)
+	{
+		uint32_t reg = base->CRH;
+
+		for (i = 0; i < 8; i++)
+		{
+			uint32_t pos = 1 << (i + 8);
+
+			if (pins & pos)
+			{
+				pos = i << 2;
+				reg &= ~(0x0f << pos);
+				reg |= reg_mode << pos;
+
+				if (mode == GPIO_MODE_IPD)
+					base->BRR = 0x01 << (i + 8);
+				if (mode == GPIO_MODE_IPU)
+					base->BSRR = 0x01 << (i + 8);
+			}
+		}
+		base->CRH = reg;
+	}
+	return 0;
+}
diff --git a/bertos/cpu/cortex-m3/drv/gpio_stm32.h b/bertos/cpu/cortex-m3/drv/gpio_stm32.h
new file mode 100644
index 00000000..4d09db47
--- /dev/null
+++ b/bertos/cpu/cortex-m3/drv/gpio_stm32.h
@@ -0,0 +1,102 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief STM32 GPIO control interface.
+ */
+
+#ifndef GPIO_STM32_H
+#define GPIO_STM32_H
+
+#include <io/stm32.h>
+
+/* GPIO configuration registers structure */
+struct stm32_gpio
+{
+	reg32_t CRL;
+	reg32_t CRH;
+	reg32_t IDR;
+	reg32_t ODR;
+	reg32_t BSRR;
+	reg32_t BRR;
+	reg32_t LCKR;
+};
+
+/**
+ * GPIO mode
+ */
+/*\{*/
+enum
+{
+	GPIO_MODE_AIN = 0x0,
+	GPIO_MODE_IN_FLOATING = 0x04,
+	GPIO_MODE_IPD = 0x28,
+	GPIO_MODE_IPU = 0x48,
+	GPIO_MODE_OUT_OD = 0x14,
+	GPIO_MODE_OUT_PP = 0x10,
+	GPIO_MODE_AF_OD = 0x1C,
+	GPIO_MODE_AF_PP = 0x18,
+};
+/*\}*/
+
+/**
+ * GPIO speed
+ */
+/*\{*/
+enum
+{
+	GPIO_SPEED_10MHZ = 1,
+	GPIO_SPEED_2MHZ,
+	GPIO_SPEED_50MHZ,
+};
+/*\}*/
+
+/* Write a value to the specified pin(s) */
+INLINE void
+stm32_gpioPinWrite(struct stm32_gpio *base, uint32_t pins, uint8_t val)
+{
+	if (val)
+		base->BSRR |= pins;
+	else
+		base->BRR  |= pins;
+}
+
+/* Read a value from the specified pin(s) */
+INLINE uint8_t stm32_gpioPinRead(struct stm32_gpio *base, uint32_t pins)
+{
+	return !!(base->IDR & pins);
+}
+
+/* Initialize a GPIO peripheral configuration */
+int stm32_gpioPinConfig(struct stm32_gpio *base,
+			uint16_t pins, uint8_t mode, uint8_t speed);
+
+#endif /* GPIO_STM32_H */
-- 
2.25.1