From e8dd780680a822dfb6c53dc9104b46491c00ad1d Mon Sep 17 00:00:00 2001 From: asterix Date: Tue, 2 Aug 2011 17:18:36 +0000 Subject: [PATCH] Define response offest register. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4985 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/io/sam3_hsmci.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bertos/cpu/cortex-m3/io/sam3_hsmci.h b/bertos/cpu/cortex-m3/io/sam3_hsmci.h index f75fd112..d8036b86 100644 --- a/bertos/cpu/cortex-m3/io/sam3_hsmci.h +++ b/bertos/cpu/cortex-m3/io/sam3_hsmci.h @@ -53,6 +53,9 @@ #define HSMCI_BLKR (*((reg32_t *)(HSMCI_BASE + 0x018))) ///< (Hsmci Offset: 0x18) Block Register #define HSMCI_CSTOR (*((reg32_t *)(HSMCI_BASE + 0x01C))) ///< (Hsmci Offset: 0x1C) Completion Signal Timeout Register #define HSMCI_RSPR (*((reg32_t *)(HSMCI_BASE + 0x020))) ///< (Hsmci Offset: 0x20) Response Register +#define HSMCI_RSPR1 (*((reg32_t *)(HSMCI_BASE + 0x024))) ///< (Hsmci Offset: 0x24) Response Register +#define HSMCI_RSPR2 (*((reg32_t *)(HSMCI_BASE + 0x028))) ///< (Hsmci Offset: 0x28) Response Register +#define HSMCI_RSPR3 (*((reg32_t *)(HSMCI_BASE + 0x02C))) ///< (Hsmci Offset: 0x2C) Response Register #define HSMCI_RDR (*((reg32_t *)(HSMCI_BASE + 0x030))) ///< (Hsmci Offset: 0x30) Receive Data Register #define HSMCI_TDR (*((reg32_t *)(HSMCI_BASE + 0x034))) ///< (Hsmci Offset: 0x34) Transmit Data Register #define HSMCI_SR (*((reg32_t *)(HSMCI_BASE + 0x040))) ///< (Hsmci Offset: 0x40) Status Register -- 2.25.1