From ed52be9771baf970f4dbfb293d902d459e3f9513 Mon Sep 17 00:00:00 2001 From: asterix Date: Mon, 27 Sep 2010 17:19:36 +0000 Subject: [PATCH] Add reg definition for adc driver. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4316 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/io/lm3s.h | 1 + bertos/cpu/cortex-m3/io/lm3s_adc.h | 1361 ++++++++++++++++++++++++++++ bertos/cpu/cortex-m3/io/lm3s_com.h | 410 --------- 3 files changed, 1362 insertions(+), 410 deletions(-) create mode 100644 bertos/cpu/cortex-m3/io/lm3s_adc.h diff --git a/bertos/cpu/cortex-m3/io/lm3s.h b/bertos/cpu/cortex-m3/io/lm3s.h index af815384..018b42ba 100644 --- a/bertos/cpu/cortex-m3/io/lm3s.h +++ b/bertos/cpu/cortex-m3/io/lm3s.h @@ -49,6 +49,7 @@ #include "lm3s_uart.h" #include "lm3s_ssi.h" #include "lm3s_i2c.h" +#include "lm3s_adc.h" #if CPU_CM3_LM3S1968 diff --git a/bertos/cpu/cortex-m3/io/lm3s_adc.h b/bertos/cpu/cortex-m3/io/lm3s_adc.h new file mode 100644 index 00000000..1fa14239 --- /dev/null +++ b/bertos/cpu/cortex-m3/io/lm3s_adc.h @@ -0,0 +1,1361 @@ +/** + * \file + * + * + * \brief LM3S ADC definition. + */ + +#ifndef LM3S_ADC_H +#define LM3S_ADC_H + + +/* + * The following are defines for the ADC register offsets. + */ +#define ADC_O_ACTSS 0x00000000 ///< ADC Active Sample Sequencer +#define ADC_O_RIS 0x00000004 ///< ADC Raw Interrupt Status +#define ADC_O_IM 0x00000008 ///< ADC Interrupt Mask +#define ADC_O_ISC 0x0000000C ///< ADC Interrupt Status and Clear +#define ADC_O_OSTAT 0x00000010 ///< ADC Overflow Status +#define ADC_O_EMUX 0x00000014 ///< ADC Event Multiplexer Select +#define ADC_O_USTAT 0x00000018 ///< ADC Underflow Status +#define ADC_O_SSPRI 0x00000020 ///< ADC Sample Sequencer Priority +#define ADC_O_SPC 0x00000024 ///< ADC Sample Phase Control +#define ADC_O_PSSI 0x00000028 ///< ADC Processor Sample Sequence + ///< Initiate +#define ADC_O_SAC 0x00000030 ///< ADC Sample Averaging Control +#define ADC_O_DCISC 0x00000034 ///< ADC Digital Comparator Interrupt + ///< Status and Clear +#define ADC_O_CTL 0x00000038 ///< ADC Control +#define ADC_O_SSMUX0 0x00000040 ///< ADC Sample Sequence Input + ///< Multiplexer Select 0 +#define ADC_O_SSCTL0 0x00000044 ///< ADC Sample Sequence Control 0 +#define ADC_O_SSFIFO0 0x00000048 ///< ADC Sample Sequence Result FIFO + ///< 0 +#define ADC_O_SSFSTAT0 0x0000004C ///< ADC Sample Sequence FIFO 0 + ///< Status +#define ADC_O_SSOP0 0x00000050 ///< ADC Sample Sequence 0 Operation +#define ADC_O_SSDC0 0x00000054 ///< ADC Sample Sequence 0 Digital + ///< Comparator Select +#define ADC_O_SSMUX1 0x00000060 ///< ADC Sample Sequence Input + ///< Multiplexer Select 1 +#define ADC_O_SSCTL1 0x00000064 ///< ADC Sample Sequence Control 1 +#define ADC_O_SSFIFO1 0x00000068 ///< ADC Sample Sequence Result FIFO + ///< 1 +#define ADC_O_SSFSTAT1 0x0000006C ///< ADC Sample Sequence FIFO 1 + ///< Status +#define ADC_O_SSOP1 0x00000070 ///< ADC Sample Sequence 1 Operation +#define ADC_O_SSDC1 0x00000074 ///< ADC Sample Sequence 1 Digital + ///< Comparator Select +#define ADC_O_SSMUX2 0x00000080 ///< ADC Sample Sequence Input + ///< Multiplexer Select 2 +#define ADC_O_SSCTL2 0x00000084 ///< ADC Sample Sequence Control 2 +#define ADC_O_SSFIFO2 0x00000088 ///< ADC Sample Sequence Result FIFO + ///< 2 +#define ADC_O_SSFSTAT2 0x0000008C ///< ADC Sample Sequence FIFO 2 + ///< Status +#define ADC_O_SSOP2 0x00000090 ///< ADC Sample Sequence 2 Operation +#define ADC_O_SSDC2 0x00000094 ///< ADC Sample Sequence 2 Digital + ///< Comparator Select +#define ADC_O_SSMUX3 0x000000A0 ///< ADC Sample Sequence Input + ///< Multiplexer Select 3 +#define ADC_O_SSCTL3 0x000000A4 ///< ADC Sample Sequence Control 3 +#define ADC_O_SSFIFO3 0x000000A8 ///< ADC Sample Sequence Result FIFO + ///< 3 +#define ADC_O_SSFSTAT3 0x000000AC ///< ADC Sample Sequence FIFO 3 + ///< Status +#define ADC_O_SSOP3 0x000000B0 ///< ADC Sample Sequence 3 Operation +#define ADC_O_SSDC3 0x000000B4 ///< ADC Sample Sequence 3 Digital + ///< Comparator Select +#define ADC_O_TMLB 0x00000100 ///< ADC Test Mode Loopback +#define ADC_O_DCRIC 0x00000D00 ///< ADC Digital Comparator Reset + ///< Initial Conditions +#define ADC_O_DCCTL0 0x00000E00 ///< ADC Digital Comparator Control 0 +#define ADC_O_DCCTL1 0x00000E04 ///< ADC Digital Comparator Control 1 +#define ADC_O_DCCTL2 0x00000E08 ///< ADC Digital Comparator Control 2 +#define ADC_O_DCCTL3 0x00000E0C ///< ADC Digital Comparator Control 3 +#define ADC_O_DCCTL4 0x00000E10 ///< ADC Digital Comparator Control 4 +#define ADC_O_DCCTL5 0x00000E14 ///< ADC Digital Comparator Control 5 +#define ADC_O_DCCTL6 0x00000E18 ///< ADC Digital Comparator Control 6 +#define ADC_O_DCCTL7 0x00000E1C ///< ADC Digital Comparator Control 7 +#define ADC_O_DCCMP0 0x00000E40 ///< ADC Digital Comparator Range 0 +#define ADC_O_DCCMP1 0x00000E44 ///< ADC Digital Comparator Range 1 +#define ADC_O_DCCMP2 0x00000E48 ///< ADC Digital Comparator Range 2 +#define ADC_O_DCCMP3 0x00000E4C ///< ADC Digital Comparator Range 3 +#define ADC_O_DCCMP4 0x00000E50 ///< ADC Digital Comparator Range 4 +#define ADC_O_DCCMP5 0x00000E54 ///< ADC Digital Comparator Range 5 +#define ADC_O_DCCMP6 0x00000E58 ///< ADC Digital Comparator Range 6 +#define ADC_O_DCCMP7 0x00000E5C ///< ADC Digital Comparator Range 7 + + +/* + * The following are defines for the bit fields in the ADC_O_ACTSS register. + */ +#define ADC_ACTSS_ASEN3 0x00000008 ///< ADC SS3 Enable +#define ADC_ACTSS_ASEN2 0x00000004 ///< ADC SS2 Enable +#define ADC_ACTSS_ASEN1 0x00000002 ///< ADC SS1 Enable +#define ADC_ACTSS_ASEN0 0x00000001 ///< ADC SS0 Enable + + +/* + * The following are defines for the bit fields in the ADC_O_RIS register. + */ +#define ADC_RIS_INRDC 0x00010000 ///< Digital Comparator Raw Interrupt + ///< Status +#define ADC_RIS_INR3 0x00000008 ///< SS3 Raw Interrupt Status +#define ADC_RIS_INR2 0x00000004 ///< SS2 Raw Interrupt Status +#define ADC_RIS_INR1 0x00000002 ///< SS1 Raw Interrupt Status +#define ADC_RIS_INR0 0x00000001 ///< SS0 Raw Interrupt Status + + +/* + * The following are defines for the bit fields in the ADC_O_IM register. + */ +#define ADC_IM_DCONSS3 0x00080000 ///< Digital Comparator Interrupt on + ///< SS3 +#define ADC_IM_DCONSS2 0x00040000 ///< Digital Comparator Interrupt on + ///< SS2 +#define ADC_IM_DCONSS1 0x00020000 ///< Digital Comparator Interrupt on + ///< SS1 +#define ADC_IM_DCONSS0 0x00010000 ///< Digital Comparator Interrupt on + ///< SS0 +#define ADC_IM_MASK3 0x00000008 ///< SS3 Interrupt Mask +#define ADC_IM_MASK2 0x00000004 ///< SS2 Interrupt Mask +#define ADC_IM_MASK1 0x00000002 ///< SS1 Interrupt Mask +#define ADC_IM_MASK0 0x00000001 ///< SS0 Interrupt Mask + + +/* + * The following are defines for the bit fields in the ADC_O_ISC register. + */ +#define ADC_ISC_DCINSS3 0x00080000 ///< Digital Comparator Interrupt + ///< Status on SS3 +#define ADC_ISC_DCINSS2 0x00040000 ///< Digital Comparator Interrupt + ///< Status on SS2 +#define ADC_ISC_DCINSS1 0x00020000 ///< Digital Comparator Interrupt + ///< Status on SS1 +#define ADC_ISC_DCINSS0 0x00010000 ///< Digital Comparator Interrupt + ///< Status on SS0 +#define ADC_ISC_IN3 0x00000008 ///< SS3 Interrupt Status and Clear +#define ADC_ISC_IN2 0x00000004 ///< SS2 Interrupt Status and Clear +#define ADC_ISC_IN1 0x00000002 ///< SS1 Interrupt Status and Clear +#define ADC_ISC_IN0 0x00000001 ///< SS0 Interrupt Status and Clear + + +/* + * The following are defines for the bit fields in the ADC_O_OSTAT register. + */ +#define ADC_OSTAT_OV3 0x00000008 ///< SS3 FIFO Overflow +#define ADC_OSTAT_OV2 0x00000004 ///< SS2 FIFO Overflow +#define ADC_OSTAT_OV1 0x00000002 ///< SS1 FIFO Overflow +#define ADC_OSTAT_OV0 0x00000001 ///< SS0 FIFO Overflow + + +/* + * The following are defines for the bit fields in the ADC_O_EMUX register. + */ +#define ADC_EMUX_EM3_M 0x0000F000 ///< SS3 Trigger Select +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 ///< Processor (default) +#define ADC_EMUX_EM3_COMP0 0x00001000 ///< Analog Comparator 0 +#define ADC_EMUX_EM3_COMP1 0x00002000 ///< Analog Comparator 1 +#define ADC_EMUX_EM3_COMP2 0x00003000 ///< Analog Comparator 2 +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 ///< External (GPIO PB4) +#define ADC_EMUX_EM3_TIMER 0x00005000 ///< Timer +#define ADC_EMUX_EM3_PWM0 0x00006000 ///< PWM0 +#define ADC_EMUX_EM3_PWM1 0x00007000 ///< PWM1 +#define ADC_EMUX_EM3_PWM2 0x00008000 ///< PWM2 +#define ADC_EMUX_EM3_PWM3 0x00009000 ///< PWM3 +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 ///< Always (continuously sample) +#define ADC_EMUX_EM2_M 0x00000F00 ///< SS2 Trigger Select +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 ///< Processor (default) +#define ADC_EMUX_EM2_COMP0 0x00000100 ///< Analog Comparator 0 +#define ADC_EMUX_EM2_COMP1 0x00000200 ///< Analog Comparator 1 +#define ADC_EMUX_EM2_COMP2 0x00000300 ///< Analog Comparator 2 +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 ///< External (GPIO PB4) +#define ADC_EMUX_EM2_TIMER 0x00000500 ///< Timer +#define ADC_EMUX_EM2_PWM0 0x00000600 ///< PWM0 +#define ADC_EMUX_EM2_PWM1 0x00000700 ///< PWM1 +#define ADC_EMUX_EM2_PWM2 0x00000800 ///< PWM2 +#define ADC_EMUX_EM2_PWM3 0x00000900 ///< PWM3 +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 ///< Always (continuously sample) +#define ADC_EMUX_EM1_M 0x000000F0 ///< SS1 Trigger Select +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 ///< Processor (default) +#define ADC_EMUX_EM1_COMP0 0x00000010 ///< Analog Comparator 0 +#define ADC_EMUX_EM1_COMP1 0x00000020 ///< Analog Comparator 1 +#define ADC_EMUX_EM1_COMP2 0x00000030 ///< Analog Comparator 2 +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 ///< External (GPIO PB4) +#define ADC_EMUX_EM1_TIMER 0x00000050 ///< Timer +#define ADC_EMUX_EM1_PWM0 0x00000060 ///< PWM0 +#define ADC_EMUX_EM1_PWM1 0x00000070 ///< PWM1 +#define ADC_EMUX_EM1_PWM2 0x00000080 ///< PWM2 +#define ADC_EMUX_EM1_PWM3 0x00000090 ///< PWM3 +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 ///< Always (continuously sample) +#define ADC_EMUX_EM0_M 0x0000000F ///< SS0 Trigger Select +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 ///< Processor (default) +#define ADC_EMUX_EM0_COMP0 0x00000001 ///< Analog Comparator 0 +#define ADC_EMUX_EM0_COMP1 0x00000002 ///< Analog Comparator 1 +#define ADC_EMUX_EM0_COMP2 0x00000003 ///< Analog Comparator 2 +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 ///< External (GPIO PB4) +#define ADC_EMUX_EM0_TIMER 0x00000005 ///< Timer +#define ADC_EMUX_EM0_PWM0 0x00000006 ///< PWM0 +#define ADC_EMUX_EM0_PWM1 0x00000007 ///< PWM1 +#define ADC_EMUX_EM0_PWM2 0x00000008 ///< PWM2 +#define ADC_EMUX_EM0_PWM3 0x00000009 ///< PWM3 +#define ADC_EMUX_EM0_ALWAYS 0x0000000F ///< Always (continuously sample) + + +/* + * The following are defines for the bit fields in the ADC_O_USTAT register. + */ +#define ADC_USTAT_UV3 0x00000008 ///< SS3 FIFO Underflow +#define ADC_USTAT_UV2 0x00000004 ///< SS2 FIFO Underflow +#define ADC_USTAT_UV1 0x00000002 ///< SS1 FIFO Underflow +#define ADC_USTAT_UV0 0x00000001 ///< SS0 FIFO Underflow + + +/* + * The following are defines for the bit fields in the ADC_O_SSPRI register. + */ +#define ADC_SSPRI_SS3_M 0x00003000 ///< SS3 Priority +#define ADC_SSPRI_SS3_1ST 0x00000000 ///< First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 ///< Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 ///< Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 ///< Fourth priority +#define ADC_SSPRI_SS2_M 0x00000300 ///< SS2 Priority +#define ADC_SSPRI_SS2_1ST 0x00000000 ///< First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 ///< Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 ///< Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 ///< Fourth priority +#define ADC_SSPRI_SS1_M 0x00000030 ///< SS1 Priority +#define ADC_SSPRI_SS1_1ST 0x00000000 ///< First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 ///< Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 ///< Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 ///< Fourth priority +#define ADC_SSPRI_SS0_M 0x00000003 ///< SS0 Priority +#define ADC_SSPRI_SS0_1ST 0x00000000 ///< First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 ///< Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 ///< Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 ///< Fourth priority + + +/* + * The following are defines for the bit fields in the ADC_O_SPC register. + */ + +#define ADC_SPC_PHASE_M 0x0000000F ///< Phase Difference +#define ADC_SPC_PHASE_0 0x00000000 ///< ADC sample lags by 0.0 +#define ADC_SPC_PHASE_22_5 0x00000001 ///< ADC sample lags by 22.5 +#define ADC_SPC_PHASE_45 0x00000002 ///< ADC sample lags by 45.0 +#define ADC_SPC_PHASE_67_5 0x00000003 ///< ADC sample lags by 67.5 +#define ADC_SPC_PHASE_90 0x00000004 ///< ADC sample lags by 90.0 +#define ADC_SPC_PHASE_112_5 0x00000005 ///< ADC sample lags by 112.5 +#define ADC_SPC_PHASE_135 0x00000006 ///< ADC sample lags by 135.0 +#define ADC_SPC_PHASE_157_5 0x00000007 ///< ADC sample lags by 157.5 +#define ADC_SPC_PHASE_180 0x00000008 ///< ADC sample lags by 180.0 +#define ADC_SPC_PHASE_202_5 0x00000009 ///< ADC sample lags by 202.5 +#define ADC_SPC_PHASE_225 0x0000000A ///< ADC sample lags by 225.0 +#define ADC_SPC_PHASE_247_5 0x0000000B ///< ADC sample lags by 247.5 +#define ADC_SPC_PHASE_270 0x0000000C ///< ADC sample lags by 270.0 +#define ADC_SPC_PHASE_292_5 0x0000000D ///< ADC sample lags by 292.5 +#define ADC_SPC_PHASE_315 0x0000000E ///< ADC sample lags by 315.0 +#define ADC_SPC_PHASE_337_5 0x0000000F ///< ADC sample lags by 337.5 + + +/* + * The following are defines for the bit fields in the ADC_O_PSSI register. + */ +#define ADC_PSSI_GSYNC 0x80000000 ///< Global Synchronize +#define ADC_PSSI_SYNCWAIT 0x08000000 ///< Synchronize Wait +#define ADC_PSSI_SS3 0x00000008 ///< SS3 Initiate +#define ADC_PSSI_SS2 0x00000004 ///< SS2 Initiate +#define ADC_PSSI_SS1 0x00000002 ///< SS1 Initiate +#define ADC_PSSI_SS0 0x00000001 ///< SS0 Initiate + + +/* + * The following are defines for the bit fields in the ADC_O_SAC register. + */ +#define ADC_SAC_AVG_M 0x00000007 ///< Hardware Averaging Control +#define ADC_SAC_AVG_OFF 0x00000000 ///< No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 ///< 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 ///< 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 ///< 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 ///< 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 ///< 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 ///< 64x hardware oversampling + + +/* + * The following are defines for the bit fields in the ADC_O_DCISC register. + */ +#define ADC_DCISC_DCINT7 0x00000080 ///< Digital Comparator 7 Interrupt + ///< Status and Clear +#define ADC_DCISC_DCINT6 0x00000040 ///< Digital Comparator 6 Interrupt + ///< Status and Clear +#define ADC_DCISC_DCINT5 0x00000020 ///< Digital Comparator 5 Interrupt + ///< Status and Clear +#define ADC_DCISC_DCINT4 0x00000010 ///< Digital Comparator 4 Interrupt + ///< Status and Clear +#define ADC_DCISC_DCINT3 0x00000008 ///< Digital Comparator 3 Interrupt + ///< Status and Clear +#define ADC_DCISC_DCINT2 0x00000004 ///< Digital Comparator 2 Interrupt + ///< Status and Clear +#define ADC_DCISC_DCINT1 0x00000002 ///< Digital Comparator 1 Interrupt + ///< Status and Clear +#define ADC_DCISC_DCINT0 0x00000001 ///< Digital Comparator 0 Interrupt + ///< Status and Clear + + +/* + * The following are defines for the bit fields in the ADC_O_CTL register. + */ +#define ADC_CTL_VREF 0x00000001 ///< Voltage Reference Select + + + +/** + * The following are defines for the bit fields in the ADC_O_ACTSS register. + */ +/*\{*/ +#define ADC_ACTSS_ASEN3 0x00000008 ///< ADC SS3 Enable +#define ADC_ACTSS_ASEN2 0x00000004 ///< ADC SS2 Enable +#define ADC_ACTSS_ASEN1 0x00000002 ///< ADC SS1 Enable +#define ADC_ACTSS_ASEN0 0x00000001 ///< ADC SS0 Enable +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_RIS register. + */ +/*\{*/ +#define ADC_RIS_INR3 0x00000008 ///< SS3 Raw Interrupt Status +#define ADC_RIS_INR2 0x00000004 ///< SS2 Raw Interrupt Status +#define ADC_RIS_INR1 0x00000002 ///< SS1 Raw Interrupt Status +#define ADC_RIS_INR0 0x00000001 ///< SS0 Raw Interrupt Status +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_IM register. + */ +/*\{*/ +#define ADC_IM_MASK3 0x00000008 ///< SS3 Interrupt Mask +#define ADC_IM_MASK2 0x00000004 ///< SS2 Interrupt Mask +#define ADC_IM_MASK1 0x00000002 ///< SS1 Interrupt Mask +#define ADC_IM_MASK0 0x00000001 ///< SS0 Interrupt Mask +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_ISC register. + */ +/*\{*/ +#define ADC_ISC_IN3 0x00000008 ///< SS3 Interrupt Status and Clear +#define ADC_ISC_IN2 0x00000004 ///< SS2 Interrupt Status and Clear +#define ADC_ISC_IN1 0x00000002 ///< SS1 Interrupt Status and Clear +#define ADC_ISC_IN0 0x00000001 ///< SS0 Interrupt Status and Clear +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_OSTAT register. + */ +/*\{*/ +#define ADC_OSTAT_OV3 0x00000008 ///< SS3 FIFO Overflow +#define ADC_OSTAT_OV2 0x00000004 ///< SS2 FIFO Overflow +#define ADC_OSTAT_OV1 0x00000002 ///< SS1 FIFO Overflow +#define ADC_OSTAT_OV0 0x00000001 ///< SS0 FIFO Overflow +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_EMUX register. + */ +/*\{*/ +#define ADC_EMUX_EM3_M 0x0000F000 ///< SS3 Trigger Select +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 ///< Processor (default) +#define ADC_EMUX_EM3_COMP0 0x00001000 ///< Analog Comparator 0 +#define ADC_EMUX_EM3_COMP1 0x00002000 ///< Analog Comparator 1 +#define ADC_EMUX_EM3_COMP2 0x00003000 ///< Analog Comparator 2 +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 ///< External (GPIO PB4) +#define ADC_EMUX_EM3_TIMER 0x00005000 ///< Timer +#define ADC_EMUX_EM3_PWM0 0x00006000 ///< PWM0 +#define ADC_EMUX_EM3_PWM1 0x00007000 ///< PWM1 +#define ADC_EMUX_EM3_PWM2 0x00008000 ///< PWM2 +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 ///< Always (continuously sample) +#define ADC_EMUX_EM2_M 0x00000F00 ///< SS2 Trigger Select +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 ///< Processor (default) +#define ADC_EMUX_EM2_COMP0 0x00000100 ///< Analog Comparator 0 +#define ADC_EMUX_EM2_COMP1 0x00000200 ///< Analog Comparator 1 +#define ADC_EMUX_EM2_COMP2 0x00000300 ///< Analog Comparator 2 +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 ///< External (GPIO PB4) +#define ADC_EMUX_EM2_TIMER 0x00000500 ///< Timer +#define ADC_EMUX_EM2_PWM0 0x00000600 ///< PWM0 +#define ADC_EMUX_EM2_PWM1 0x00000700 ///< PWM1 +#define ADC_EMUX_EM2_PWM2 0x00000800 ///< PWM2 +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 ///< Always (continuously sample) +#define ADC_EMUX_EM1_M 0x000000F0 ///< SS1 Trigger Select +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 ///< Processor (default) +#define ADC_EMUX_EM1_COMP0 0x00000010 ///< Analog Comparator 0 +#define ADC_EMUX_EM1_COMP1 0x00000020 ///< Analog Comparator 1 +#define ADC_EMUX_EM1_COMP2 0x00000030 ///< Analog Comparator 2 +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 ///< External (GPIO PB4) +#define ADC_EMUX_EM1_TIMER 0x00000050 ///< Timer +#define ADC_EMUX_EM1_PWM0 0x00000060 ///< PWM0 +#define ADC_EMUX_EM1_PWM1 0x00000070 ///< PWM1 +#define ADC_EMUX_EM1_PWM2 0x00000080 ///< PWM2 +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 ///< Always (continuously sample) +#define ADC_EMUX_EM0_M 0x0000000F ///< SS0 Trigger Select +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 ///< Processor (default) +#define ADC_EMUX_EM0_COMP0 0x00000001 ///< Analog Comparator 0 +#define ADC_EMUX_EM0_COMP1 0x00000002 ///< Analog Comparator 1 +#define ADC_EMUX_EM0_COMP2 0x00000003 ///< Analog Comparator 2 +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 ///< External (GPIO PB4) +#define ADC_EMUX_EM0_TIMER 0x00000005 ///< Timer +#define ADC_EMUX_EM0_PWM0 0x00000006 ///< PWM0 +#define ADC_EMUX_EM0_PWM1 0x00000007 ///< PWM1 +#define ADC_EMUX_EM0_PWM2 0x00000008 ///< PWM2 +#define ADC_EMUX_EM0_ALWAYS 0x0000000F ///< Always (continuously sample) +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_USTAT register. + */ +/*\{*/ +#define ADC_USTAT_UV3 0x00000008 ///< SS3 FIFO Underflow +#define ADC_USTAT_UV2 0x00000004 ///< SS2 FIFO Underflow +#define ADC_USTAT_UV1 0x00000002 ///< SS1 FIFO Underflow +#define ADC_USTAT_UV0 0x00000001 ///< SS0 FIFO Underflow +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSPRI register. + */ +/*\{*/ +#define ADC_SSPRI_SS3_M 0x00003000 ///< SS3 Priority +#define ADC_SSPRI_SS3_1ST 0x00000000 ///< First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 ///< Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 ///< Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 ///< Fourth priority +#define ADC_SSPRI_SS2_M 0x00000300 ///< SS2 Priority +#define ADC_SSPRI_SS2_1ST 0x00000000 ///< First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 ///< Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 ///< Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 ///< Fourth priority +#define ADC_SSPRI_SS1_M 0x00000030 ///< SS1 Priority +#define ADC_SSPRI_SS1_1ST 0x00000000 ///< First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 ///< Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 ///< Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 ///< Fourth priority +#define ADC_SSPRI_SS0_M 0x00000003 ///< SS0 Priority +#define ADC_SSPRI_SS0_1ST 0x00000000 ///< First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 ///< Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 ///< Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 ///< Fourth priority +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_PSSI register. + */ +/*\{*/ +#define ADC_PSSI_SS3 0x00000008 ///< SS3 Initiate +#define ADC_PSSI_SS2 0x00000004 ///< SS2 Initiate +#define ADC_PSSI_SS1 0x00000002 ///< SS1 Initiate +#define ADC_PSSI_SS0 0x00000001 ///< SS0 Initiate +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SAC register. + */ +/*\{*/ +#define ADC_SAC_AVG_M 0x00000007 ///< Hardware Averaging Control +#define ADC_SAC_AVG_OFF 0x00000000 ///< No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 ///< 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 ///< 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 ///< 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 ///< 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 ///< 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 ///< 64x hardware oversampling +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSMUX0 register. + */ +/*\{*/ +#define ADC_SSMUX0_MUX7_M 0x70000000 ///< 8th Sample Input Select +#define ADC_SSMUX0_MUX6_M 0x07000000 ///< 7th Sample Input Select +#define ADC_SSMUX0_MUX5_M 0x00700000 ///< 6th Sample Input Select +#define ADC_SSMUX0_MUX4_M 0x00070000 ///< 5th Sample Input Select +#define ADC_SSMUX0_MUX3_M 0x00007000 ///< 4th Sample Input Select +#define ADC_SSMUX0_MUX2_M 0x00000700 ///< 3rd Sample Input Select +#define ADC_SSMUX0_MUX1_M 0x00000070 ///< 2nd Sample Input Select +#define ADC_SSMUX0_MUX0_M 0x00000007 ///< 1st Sample Input Select +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSCTL0 register. + */ +/*\{*/ +#define ADC_SSCTL0_TS7 0x80000000 ///< 8th Sample Temp Sensor Select +#define ADC_SSCTL0_IE7 0x40000000 ///< 8th Sample Interrupt Enable +#define ADC_SSCTL0_END7 0x20000000 ///< 8th Sample is End of Sequence +#define ADC_SSCTL0_D7 0x10000000 ///< 8th Sample Diff Input Select +#define ADC_SSCTL0_TS6 0x08000000 ///< 7th Sample Temp Sensor Select +#define ADC_SSCTL0_IE6 0x04000000 ///< 7th Sample Interrupt Enable +#define ADC_SSCTL0_END6 0x02000000 ///< 7th Sample is End of Sequence +#define ADC_SSCTL0_D6 0x01000000 ///< 7th Sample Diff Input Select +#define ADC_SSCTL0_TS5 0x00800000 ///< 6th Sample Temp Sensor Select +#define ADC_SSCTL0_IE5 0x00400000 ///< 6th Sample Interrupt Enable +#define ADC_SSCTL0_END5 0x00200000 ///< 6th Sample is End of Sequence +#define ADC_SSCTL0_D5 0x00100000 ///< 6th Sample Diff Input Select +#define ADC_SSCTL0_TS4 0x00080000 ///< 5th Sample Temp Sensor Select +#define ADC_SSCTL0_IE4 0x00040000 ///< 5th Sample Interrupt Enable +#define ADC_SSCTL0_END4 0x00020000 ///< 5th Sample is End of Sequence +#define ADC_SSCTL0_D4 0x00010000 ///< 5th Sample Diff Input Select +#define ADC_SSCTL0_TS3 0x00008000 ///< 4th Sample Temp Sensor Select +#define ADC_SSCTL0_IE3 0x00004000 ///< 4th Sample Interrupt Enable +#define ADC_SSCTL0_END3 0x00002000 ///< 4th Sample is End of Sequence +#define ADC_SSCTL0_D3 0x00001000 ///< 4th Sample Diff Input Select +#define ADC_SSCTL0_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select +#define ADC_SSCTL0_IE2 0x00000400 ///< 3rd Sample Interrupt Enable +#define ADC_SSCTL0_END2 0x00000200 ///< 3rd Sample is End of Sequence +#define ADC_SSCTL0_D2 0x00000100 ///< 3rd Sample Diff Input Select +#define ADC_SSCTL0_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select +#define ADC_SSCTL0_IE1 0x00000040 ///< 2nd Sample Interrupt Enable +#define ADC_SSCTL0_END1 0x00000020 ///< 2nd Sample is End of Sequence +#define ADC_SSCTL0_D1 0x00000010 ///< 2nd Sample Diff Input Select +#define ADC_SSCTL0_TS0 0x00000008 ///< 1st Sample Temp Sensor Select +#define ADC_SSCTL0_IE0 0x00000004 ///< 1st Sample Interrupt Enable +#define ADC_SSCTL0_END0 0x00000002 ///< 1st Sample is End of Sequence +#define ADC_SSCTL0_D0 0x00000001 ///< 1st Sample Diff Input Select +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSFIFO0 register. + */ +/*\{*/ +#define ADC_SSFIFO0_DATA_M 0x000003FF ///< Conversion Result Data +#define ADC_SSFIFO0_DATA_S 0 +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. + */ +/*\{*/ +#define ADC_SSFSTAT0_FULL 0x00001000 ///< FIFO Full +#define ADC_SSFSTAT0_EMPTY 0x00000100 ///< FIFO Empty +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 ///< FIFO Head Pointer +#define ADC_SSFSTAT0_TPTR_M 0x0000000F ///< FIFO Tail Pointer +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSMUX1 register. + */ +/*\{*/ +#define ADC_SSMUX1_MUX3_M 0x00007000 ///< 4th Sample Input Select +#define ADC_SSMUX1_MUX2_M 0x00000700 ///< 3rd Sample Input Select +#define ADC_SSMUX1_MUX1_M 0x00000070 ///< 2nd Sample Input Select +#define ADC_SSMUX1_MUX0_M 0x00000007 ///< 1st Sample Input Select +#define ADC_SSMUX1_MUX3_S 12 +#define ADC_SSMUX1_MUX2_S 8 +#define ADC_SSMUX1_MUX1_S 4 +#define ADC_SSMUX1_MUX0_S 0 +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSCTL1 register. + */ +/*\{*/ +#define ADC_SSCTL1_TS3 0x00008000 ///< 4th Sample Temp Sensor Select +#define ADC_SSCTL1_IE3 0x00004000 ///< 4th Sample Interrupt Enable +#define ADC_SSCTL1_END3 0x00002000 ///< 4th Sample is End of Sequence +#define ADC_SSCTL1_D3 0x00001000 ///< 4th Sample Diff Input Select +#define ADC_SSCTL1_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select +#define ADC_SSCTL1_IE2 0x00000400 ///< 3rd Sample Interrupt Enable +#define ADC_SSCTL1_END2 0x00000200 ///< 3rd Sample is End of Sequence +#define ADC_SSCTL1_D2 0x00000100 ///< 3rd Sample Diff Input Select +#define ADC_SSCTL1_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select +#define ADC_SSCTL1_IE1 0x00000040 ///< 2nd Sample Interrupt Enable +#define ADC_SSCTL1_END1 0x00000020 ///< 2nd Sample is End of Sequence +#define ADC_SSCTL1_D1 0x00000010 ///< 2nd Sample Diff Input Select +#define ADC_SSCTL1_TS0 0x00000008 ///< 1st Sample Temp Sensor Select +#define ADC_SSCTL1_IE0 0x00000004 ///< 1st Sample Interrupt Enable +#define ADC_SSCTL1_END0 0x00000002 ///< 1st Sample is End of Sequence +#define ADC_SSCTL1_D0 0x00000001 ///< 1st Sample Diff Input Select +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSFIFO1 register. + */ +/*\{*/ +#define ADC_SSFIFO1_DATA_M 0x000003FF ///< Conversion Result Data +#define ADC_SSFIFO1_DATA_S 0 +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. + */ +/*\{*/ +#define ADC_SSFSTAT1_FULL 0x00001000 ///< FIFO Full +#define ADC_SSFSTAT1_EMPTY 0x00000100 ///< FIFO Empty +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 ///< FIFO Head Pointer +#define ADC_SSFSTAT1_TPTR_M 0x0000000F ///< FIFO Tail Pointer +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 +/*\}*/ + + +/** + * The following are defines for the bit fields in the ADC_O_SSCTL2 register. + */ +/*\{*/ +#define ADC_SSCTL2_TS3 0x00008000 ///< 4th Sample Temp Sensor Select +#define ADC_SSCTL2_IE3 0x00004000 ///< 4th Sample Interrupt Enable +#define ADC_SSCTL2_END3 0x00002000 ///< 4th Sample is End of Sequence +#define ADC_SSCTL2_D3 0x00001000 ///< 4th Sample Diff Input Select +#define ADC_SSCTL2_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select +#define ADC_SSCTL2_IE2 0x00000400 ///< 3rd Sample Interrupt Enable +#define ADC_SSCTL2_END2 0x00000200 ///< 3rd Sample is End of Sequence +#define ADC_SSCTL2_D2 0x00000100 ///< 3rd Sample Diff Input Select +#define ADC_SSCTL2_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select +#define ADC_SSCTL2_IE1 0x00000040 ///< 2nd Sample Interrupt Enable +#define ADC_SSCTL2_END1 0x00000020 ///< 2nd Sample is End of Sequence +#define ADC_SSCTL2_D1 0x00000010 ///< 2nd Sample Diff Input Select +#define ADC_SSCTL2_TS0 0x00000008 ///< 1st Sample Temp Sensor Select +#define ADC_SSCTL2_IE0 0x00000004 ///< 1st Sample Interrupt Enable +#define ADC_SSCTL2_END0 0x00000002 ///< 1st Sample is End of Sequence +#define ADC_SSCTL2_D0 0x00000001 ///< 1st Sample Diff Input Select +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSFIFO2 register. + */ +/*\{*/ +#define ADC_SSFIFO2_DATA_M 0x000003FF ///< Conversion Result Data +#define ADC_SSFIFO2_DATA_S 0 +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. + */ +/*\{*/ +#define ADC_SSFSTAT2_FULL 0x00001000 ///< FIFO Full +#define ADC_SSFSTAT2_EMPTY 0x00000100 ///< FIFO Empty +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 ///< FIFO Head Pointer +#define ADC_SSFSTAT2_TPTR_M 0x0000000F ///< FIFO Tail Pointer +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSCTL3 register. + */ +/*\{*/ +#define ADC_SSCTL3_TS0 0x00000008 ///< 1st Sample Temp Sensor Select +#define ADC_SSCTL3_IE0 0x00000004 ///< 1st Sample Interrupt Enable +#define ADC_SSCTL3_END0 0x00000002 ///< 1st Sample is End of Sequence +#define ADC_SSCTL3_D0 0x00000001 ///< 1st Sample Diff Input Select +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSFIFO3 register. + */ +/*\{*/ +#define ADC_SSFIFO3_DATA_M 0x000003FF ///< Conversion Result Data +#define ADC_SSFIFO3_DATA_S 0 +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. + */ +/*\{*/ +#define ADC_SSFSTAT3_FULL 0x00001000 ///< FIFO Full +#define ADC_SSFSTAT3_EMPTY 0x00000100 ///< FIFO Empty +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 ///< FIFO Head Pointer +#define ADC_SSFSTAT3_TPTR_M 0x0000000F ///< FIFO Tail Pointer +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 +/*\}*/ + +/** + * The following are defines for the bit fields in the ADC_O_TMLB register. + */ +/*\{*/ +#define ADC_TMLB_LB 0x00000001 ///< Loopback Mode Enable +/*\}*/ + +/** + * The following are defines for the the interpretation of the data in the +* SSFIFOx when the ADC TMLB is enabled. + */ +/*\{*/ +#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 ///< Continuous Sample Counter +#define ADC_SSFIFO_TMLB_CONT 0x00000020 ///< Continuation Sample Indicator +#define ADC_SSFIFO_TMLB_DIFF 0x00000010 ///< Differential Sample Indicator +#define ADC_SSFIFO_TMLB_TS 0x00000008 ///< Temp Sensor Sample Indicator +#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 ///< Analog Input Indicator +#define ADC_SSFIFO_TMLB_CNT_S 6 ///< Sample counter shift +#define ADC_SSFIFO_TMLB_MUX_S 0 ///< Input channel number shift +/*\}*/ + + +/* + * The following are defines for the bit fields in the ADC_O_SSMUX0 register. + */ +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSCTL0 register. + */ +#define ADC_SSCTL0_TS7 0x80000000 ///< 8th Sample Temp Sensor Select +#define ADC_SSCTL0_IE7 0x40000000 ///< 8th Sample Interrupt Enable +#define ADC_SSCTL0_END7 0x20000000 ///< 8th Sample is End of Sequence +#define ADC_SSCTL0_D7 0x10000000 ///< 8th Sample Diff Input Select +#define ADC_SSCTL0_TS6 0x08000000 ///< 7th Sample Temp Sensor Select +#define ADC_SSCTL0_IE6 0x04000000 ///< 7th Sample Interrupt Enable +#define ADC_SSCTL0_END6 0x02000000 ///< 7th Sample is End of Sequence +#define ADC_SSCTL0_D6 0x01000000 ///< 7th Sample Diff Input Select +#define ADC_SSCTL0_TS5 0x00800000 ///< 6th Sample Temp Sensor Select +#define ADC_SSCTL0_IE5 0x00400000 ///< 6th Sample Interrupt Enable +#define ADC_SSCTL0_END5 0x00200000 ///< 6th Sample is End of Sequence +#define ADC_SSCTL0_D5 0x00100000 ///< 6th Sample Diff Input Select +#define ADC_SSCTL0_TS4 0x00080000 ///< 5th Sample Temp Sensor Select +#define ADC_SSCTL0_IE4 0x00040000 ///< 5th Sample Interrupt Enable +#define ADC_SSCTL0_END4 0x00020000 ///< 5th Sample is End of Sequence +#define ADC_SSCTL0_D4 0x00010000 ///< 5th Sample Diff Input Select +#define ADC_SSCTL0_TS3 0x00008000 ///< 4th Sample Temp Sensor Select +#define ADC_SSCTL0_IE3 0x00004000 ///< 4th Sample Interrupt Enable +#define ADC_SSCTL0_END3 0x00002000 ///< 4th Sample is End of Sequence +#define ADC_SSCTL0_D3 0x00001000 ///< 4th Sample Diff Input Select +#define ADC_SSCTL0_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select +#define ADC_SSCTL0_IE2 0x00000400 ///< 3rd Sample Interrupt Enable +#define ADC_SSCTL0_END2 0x00000200 ///< 3rd Sample is End of Sequence +#define ADC_SSCTL0_D2 0x00000100 ///< 3rd Sample Diff Input Select +#define ADC_SSCTL0_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select +#define ADC_SSCTL0_IE1 0x00000040 ///< 2nd Sample Interrupt Enable +#define ADC_SSCTL0_END1 0x00000020 ///< 2nd Sample is End of Sequence +#define ADC_SSCTL0_D1 0x00000010 ///< 2nd Sample Diff Input Select +#define ADC_SSCTL0_TS0 0x00000008 ///< 1st Sample Temp Sensor Select +#define ADC_SSCTL0_IE0 0x00000004 ///< 1st Sample Interrupt Enable +#define ADC_SSCTL0_END0 0x00000002 ///< 1st Sample is End of Sequence +#define ADC_SSCTL0_D0 0x00000001 ///< 1st Sample Diff Input Select + + +/* + * The following are defines for the bit fields in the ADC_O_SSFIFO0 register. + */ +#define ADC_SSFIFO0_DATA_M 0x000003FF ///< Conversion Result Data +#define ADC_SSFIFO0_DATA_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. + */ +#define ADC_SSFSTAT0_FULL 0x00001000 ///< FIFO Full +#define ADC_SSFSTAT0_EMPTY 0x00000100 ///< FIFO Empty +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 ///< FIFO Head Pointer +#define ADC_SSFSTAT0_TPTR_M 0x0000000F ///< FIFO Tail Pointer +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSOP0 register. + */ +#define ADC_SSOP0_S7DCOP 0x10000000 ///< Sample 7 Digital Comparator + ///< Operation +#define ADC_SSOP0_S6DCOP 0x01000000 ///< Sample 6 Digital Comparator + ///< Operation +#define ADC_SSOP0_S5DCOP 0x00100000 ///< Sample 5 Digital Comparator + ///< Operation +#define ADC_SSOP0_S4DCOP 0x00010000 ///< Sample 4 Digital Comparator + ///< Operation +#define ADC_SSOP0_S3DCOP 0x00001000 ///< Sample 3 Digital Comparator + ///< Operation +#define ADC_SSOP0_S2DCOP 0x00000100 ///< Sample 2 Digital Comparator + ///< Operation +#define ADC_SSOP0_S1DCOP 0x00000010 ///< Sample 1 Digital Comparator + ///< Operation +#define ADC_SSOP0_S0DCOP 0x00000001 ///< Sample 0 Digital Comparator + ///< Operation + + +/* + * The following are defines for the bit fields in the ADC_O_SSDC0 register. + */ +#define ADC_SSDC0_S7DCSEL_M 0xF0000000 ///< Sample 7 Digital Comparator + ///< Select +#define ADC_SSDC0_S6DCSEL_M 0x0F000000 ///< Sample 6 Digital Comparator + ///< Select +#define ADC_SSDC0_S5DCSEL_M 0x00F00000 ///< Sample 5 Digital Comparator + ///< Select +#define ADC_SSDC0_S4DCSEL_M 0x000F0000 ///< Sample 4 Digital Comparator + ///< Select +#define ADC_SSDC0_S3DCSEL_M 0x0000F000 ///< Sample 3 Digital Comparator + ///< Select +#define ADC_SSDC0_S2DCSEL_M 0x00000F00 ///< Sample 2 Digital Comparator + ///< Select +#define ADC_SSDC0_S1DCSEL_M 0x000000F0 ///< Sample 1 Digital Comparator + ///< Select +#define ADC_SSDC0_S0DCSEL_M 0x0000000F ///< Sample 0 Digital Comparator + ///< Select +#define ADC_SSDC0_S6DCSEL_S 24 +#define ADC_SSDC0_S5DCSEL_S 20 +#define ADC_SSDC0_S4DCSEL_S 16 +#define ADC_SSDC0_S3DCSEL_S 12 +#define ADC_SSDC0_S2DCSEL_S 8 +#define ADC_SSDC0_S1DCSEL_S 4 +#define ADC_SSDC0_S0DCSEL_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSCTL1 register. + */ +#define ADC_SSCTL1_TS3 0x00008000 ///< 4th Sample Temp Sensor Select +#define ADC_SSCTL1_IE3 0x00004000 ///< 4th Sample Interrupt Enable +#define ADC_SSCTL1_END3 0x00002000 ///< 4th Sample is End of Sequence +#define ADC_SSCTL1_D3 0x00001000 ///< 4th Sample Diff Input Select +#define ADC_SSCTL1_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select +#define ADC_SSCTL1_IE2 0x00000400 ///< 3rd Sample Interrupt Enable +#define ADC_SSCTL1_END2 0x00000200 ///< 3rd Sample is End of Sequence +#define ADC_SSCTL1_D2 0x00000100 ///< 3rd Sample Diff Input Select +#define ADC_SSCTL1_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select +#define ADC_SSCTL1_IE1 0x00000040 ///< 2nd Sample Interrupt Enable +#define ADC_SSCTL1_END1 0x00000020 ///< 2nd Sample is End of Sequence +#define ADC_SSCTL1_D1 0x00000010 ///< 2nd Sample Diff Input Select +#define ADC_SSCTL1_TS0 0x00000008 ///< 1st Sample Temp Sensor Select +#define ADC_SSCTL1_IE0 0x00000004 ///< 1st Sample Interrupt Enable +#define ADC_SSCTL1_END0 0x00000002 ///< 1st Sample is End of Sequence +#define ADC_SSCTL1_D0 0x00000001 ///< 1st Sample Diff Input Select + + +/* + * The following are defines for the bit fields in the ADC_O_SSFIFO1 register. + */ +#define ADC_SSFIFO1_DATA_M 0x000003FF ///< Conversion Result Data +#define ADC_SSFIFO1_DATA_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. + */ +#define ADC_SSFSTAT1_FULL 0x00001000 ///< FIFO Full +#define ADC_SSFSTAT1_EMPTY 0x00000100 ///< FIFO Empty +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 ///< FIFO Head Pointer +#define ADC_SSFSTAT1_TPTR_M 0x0000000F ///< FIFO Tail Pointer +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSOP1 register. + */ +#define ADC_SSOP1_S3DCOP 0x00001000 ///< Sample 3 Digital Comparator + ///< Operation +#define ADC_SSOP1_S2DCOP 0x00000100 ///< Sample 2 Digital Comparator + ///< Operation +#define ADC_SSOP1_S1DCOP 0x00000010 ///< Sample 1 Digital Comparator + ///< Operation +#define ADC_SSOP1_S0DCOP 0x00000001 ///< Sample 0 Digital Comparator + ///< Operation + + +/* + * The following are defines for the bit fields in the ADC_O_SSDC1 register. + */ +#define ADC_SSDC1_S3DCSEL_M 0x0000F000 ///< Sample 3 Digital Comparator + ///< Select +#define ADC_SSDC1_S2DCSEL_M 0x00000F00 ///< Sample 2 Digital Comparator + ///< Select +#define ADC_SSDC1_S1DCSEL_M 0x000000F0 ///< Sample 1 Digital Comparator + ///< Select +#define ADC_SSDC1_S0DCSEL_M 0x0000000F ///< Sample 0 Digital Comparator + ///< Select +#define ADC_SSDC1_S2DCSEL_S 8 +#define ADC_SSDC1_S1DCSEL_S 4 +#define ADC_SSDC1_S0DCSEL_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSMUX2 register. + */ +#define ADC_SSMUX2_MUX3_M 0x0000F000 ///< 4th Sample Input Select +#define ADC_SSMUX2_MUX2_M 0x00000F00 ///< 3rd Sample Input Select +#define ADC_SSMUX2_MUX1_M 0x000000F0 ///< 2nd Sample Input Select +#define ADC_SSMUX2_MUX0_M 0x0000000F ///< 1st Sample Input Select +#define ADC_SSMUX2_MUX3_S 12 +#define ADC_SSMUX2_MUX2_S 8 +#define ADC_SSMUX2_MUX1_S 4 +#define ADC_SSMUX2_MUX0_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSCTL2 register. + */ +#define ADC_SSCTL2_TS3 0x00008000 ///< 4th Sample Temp Sensor Select +#define ADC_SSCTL2_IE3 0x00004000 ///< 4th Sample Interrupt Enable +#define ADC_SSCTL2_END3 0x00002000 ///< 4th Sample is End of Sequence +#define ADC_SSCTL2_D3 0x00001000 ///< 4th Sample Diff Input Select +#define ADC_SSCTL2_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select +#define ADC_SSCTL2_IE2 0x00000400 ///< 3rd Sample Interrupt Enable +#define ADC_SSCTL2_END2 0x00000200 ///< 3rd Sample is End of Sequence +#define ADC_SSCTL2_D2 0x00000100 ///< 3rd Sample Diff Input Select +#define ADC_SSCTL2_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select +#define ADC_SSCTL2_IE1 0x00000040 ///< 2nd Sample Interrupt Enable +#define ADC_SSCTL2_END1 0x00000020 ///< 2nd Sample is End of Sequence +#define ADC_SSCTL2_D1 0x00000010 ///< 2nd Sample Diff Input Select +#define ADC_SSCTL2_TS0 0x00000008 ///< 1st Sample Temp Sensor Select +#define ADC_SSCTL2_IE0 0x00000004 ///< 1st Sample Interrupt Enable +#define ADC_SSCTL2_END0 0x00000002 ///< 1st Sample is End of Sequence +#define ADC_SSCTL2_D0 0x00000001 ///< 1st Sample Diff Input Select + + +/* + * The following are defines for the bit fields in the ADC_O_SSFIFO2 register. + */ +#define ADC_SSFIFO2_DATA_M 0x000003FF ///< Conversion Result Data +#define ADC_SSFIFO2_DATA_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. + */ +#define ADC_SSFSTAT2_FULL 0x00001000 ///< FIFO Full +#define ADC_SSFSTAT2_EMPTY 0x00000100 ///< FIFO Empty +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 ///< FIFO Head Pointer +#define ADC_SSFSTAT2_TPTR_M 0x0000000F ///< FIFO Tail Pointer +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSOP2 register. + */ +#define ADC_SSOP2_S3DCOP 0x00001000 ///< Sample 3 Digital Comparator + ///< Operation +#define ADC_SSOP2_S2DCOP 0x00000100 ///< Sample 2 Digital Comparator + ///< Operation +#define ADC_SSOP2_S1DCOP 0x00000010 ///< Sample 1 Digital Comparator + ///< Operation +#define ADC_SSOP2_S0DCOP 0x00000001 ///< Sample 0 Digital Comparator + ///< Operation + + +/* + * The following are defines for the bit fields in the ADC_O_SSDC2 register. + */ +#define ADC_SSDC2_S3DCSEL_M 0x0000F000 ///< Sample 3 Digital Comparator + ///< Select +#define ADC_SSDC2_S2DCSEL_M 0x00000F00 ///< Sample 2 Digital Comparator + ///< Select +#define ADC_SSDC2_S1DCSEL_M 0x000000F0 ///< Sample 1 Digital Comparator + ///< Select +#define ADC_SSDC2_S0DCSEL_M 0x0000000F ///< Sample 0 Digital Comparator + ///< Select +#define ADC_SSDC2_S2DCSEL_S 8 +#define ADC_SSDC2_S1DCSEL_S 4 +#define ADC_SSDC2_S0DCSEL_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSMUX3 register. + */ +#define ADC_SSMUX3_MUX0_M 0x0000000F ///< 1st Sample Input Select +#define ADC_SSMUX3_MUX0_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSCTL3 register. + */ +#define ADC_SSCTL3_TS0 0x00000008 ///< 1st Sample Temp Sensor Select +#define ADC_SSCTL3_IE0 0x00000004 ///< 1st Sample Interrupt Enable +#define ADC_SSCTL3_END0 0x00000002 ///< 1st Sample is End of Sequence +#define ADC_SSCTL3_D0 0x00000001 ///< 1st Sample Diff Input Select + + +/* + * The following are defines for the bit fields in the ADC_O_SSFIFO3 register. + */ +#define ADC_SSFIFO3_DATA_M 0x000003FF ///< Conversion Result Data +#define ADC_SSFIFO3_DATA_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. + */ +#define ADC_SSFSTAT3_FULL 0x00001000 ///< FIFO Full +#define ADC_SSFSTAT3_EMPTY 0x00000100 ///< FIFO Empty +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 ///< FIFO Head Pointer +#define ADC_SSFSTAT3_TPTR_M 0x0000000F ///< FIFO Tail Pointer +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_SSOP3 register. + */ +#define ADC_SSOP3_S0DCOP 0x00000001 ///< Sample 0 Digital Comparator + ///< Operation + + +/* + * The following are defines for the bit fields in the ADC_O_SSDC3 register. + */ +#define ADC_SSDC3_S0DCSEL_M 0x0000000F ///< Sample 0 Digital Comparator + ///< Select + + +/* + * The following are defines for the bit fields in the ADC_O_TMLB register. + */ +#define ADC_TMLB_LB 0x00000001 ///< Loopback Mode Enable + + +/* + * The following are defines for the bit fields in the ADC_O_DCRIC register. + */ +#define ADC_DCRIC_DCTRIG7 0x00800000 ///< Digital Comparator Trigger 7 +#define ADC_DCRIC_DCTRIG6 0x00400000 ///< Digital Comparator Trigger 6 +#define ADC_DCRIC_DCTRIG5 0x00200000 ///< Digital Comparator Trigger 5 +#define ADC_DCRIC_DCTRIG4 0x00100000 ///< Digital Comparator Trigger 4 +#define ADC_DCRIC_DCTRIG3 0x00080000 ///< Digital Comparator Trigger 3 +#define ADC_DCRIC_DCTRIG2 0x00040000 ///< Digital Comparator Trigger 2 +#define ADC_DCRIC_DCTRIG1 0x00020000 ///< Digital Comparator Trigger 1 +#define ADC_DCRIC_DCTRIG0 0x00010000 ///< Digital Comparator Trigger 0 +#define ADC_DCRIC_DCINT7 0x00000080 ///< Digital Comparator Interrupt 7 +#define ADC_DCRIC_DCINT6 0x00000040 ///< Digital Comparator Interrupt 6 +#define ADC_DCRIC_DCINT5 0x00000020 ///< Digital Comparator Interrupt 5 +#define ADC_DCRIC_DCINT4 0x00000010 ///< Digital Comparator Interrupt 4 +#define ADC_DCRIC_DCINT3 0x00000008 ///< Digital Comparator Interrupt 3 +#define ADC_DCRIC_DCINT2 0x00000004 ///< Digital Comparator Interrupt 2 +#define ADC_DCRIC_DCINT1 0x00000002 ///< Digital Comparator Interrupt 1 +#define ADC_DCRIC_DCINT0 0x00000001 ///< Digital Comparator Interrupt 0 + + +/* + * The following are defines for the bit fields in the ADC_O_DCCTL0 register. + */ +#define ADC_DCCTL0_CTE 0x00001000 ///< Comparison Trigger Enable +#define ADC_DCCTL0_CTC_M 0x00000C00 ///< Comparison Trigger Condition +#define ADC_DCCTL0_CTC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL0_CTC_MID 0x00000400 ///< Mid Band +#define ADC_DCCTL0_CTC_HIGH 0x00000C00 ///< High Band +#define ADC_DCCTL0_CTM_M 0x00000300 ///< Comparison Trigger Mode +#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL0_CTM_ONCE 0x00000100 ///< Once +#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 ///< Hysteresis Always +#define ADC_DCCTL0_CTM_HONCE 0x00000300 ///< Hysteresis Once +#define ADC_DCCTL0_CIE 0x00000010 ///< Comparison Interrupt Enable +#define ADC_DCCTL0_CIC_M 0x0000000C ///< Comparison Interrupt Condition +#define ADC_DCCTL0_CIC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL0_CIC_MID 0x00000004 ///< Mid Band +#define ADC_DCCTL0_CIC_HIGH 0x0000000C ///< High Band +#define ADC_DCCTL0_CIM_M 0x00000003 ///< Comparison Interrupt Mode +#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL0_CIM_ONCE 0x00000001 ///< Once +#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 ///< Hysteresis Always +#define ADC_DCCTL0_CIM_HONCE 0x00000003 ///< Hysteresis Once + + +/* + * The following are defines for the bit fields in the ADC_O_DCCTL1 register. + */ +#define ADC_DCCTL1_CTE 0x00001000 ///< Comparison Trigger Enable +#define ADC_DCCTL1_CTC_M 0x00000C00 ///< Comparison Trigger Condition +#define ADC_DCCTL1_CTC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL1_CTC_MID 0x00000400 ///< Mid Band +#define ADC_DCCTL1_CTC_HIGH 0x00000C00 ///< High Band +#define ADC_DCCTL1_CTM_M 0x00000300 ///< Comparison Trigger Mode +#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL1_CTM_ONCE 0x00000100 ///< Once +#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 ///< Hysteresis Always +#define ADC_DCCTL1_CTM_HONCE 0x00000300 ///< Hysteresis Once +#define ADC_DCCTL1_CIE 0x00000010 ///< Comparison Interrupt Enable +#define ADC_DCCTL1_CIC_M 0x0000000C ///< Comparison Interrupt Condition +#define ADC_DCCTL1_CIC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL1_CIC_MID 0x00000004 ///< Mid Band +#define ADC_DCCTL1_CIC_HIGH 0x0000000C ///< High Band +#define ADC_DCCTL1_CIM_M 0x00000003 ///< Comparison Interrupt Mode +#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL1_CIM_ONCE 0x00000001 ///< Once +#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 ///< Hysteresis Always +#define ADC_DCCTL1_CIM_HONCE 0x00000003 ///< Hysteresis Once + + +/* + * The following are defines for the bit fields in the ADC_O_DCCTL2 register. + */ +#define ADC_DCCTL2_CTE 0x00001000 ///< Comparison Trigger Enable +#define ADC_DCCTL2_CTC_M 0x00000C00 ///< Comparison Trigger Condition +#define ADC_DCCTL2_CTC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL2_CTC_MID 0x00000400 ///< Mid Band +#define ADC_DCCTL2_CTC_HIGH 0x00000C00 ///< High Band +#define ADC_DCCTL2_CTM_M 0x00000300 ///< Comparison Trigger Mode +#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL2_CTM_ONCE 0x00000100 ///< Once +#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 ///< Hysteresis Always +#define ADC_DCCTL2_CTM_HONCE 0x00000300 ///< Hysteresis Once +#define ADC_DCCTL2_CIE 0x00000010 ///< Comparison Interrupt Enable +#define ADC_DCCTL2_CIC_M 0x0000000C ///< Comparison Interrupt Condition +#define ADC_DCCTL2_CIC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL2_CIC_MID 0x00000004 ///< Mid Band +#define ADC_DCCTL2_CIC_HIGH 0x0000000C ///< High Band +#define ADC_DCCTL2_CIM_M 0x00000003 ///< Comparison Interrupt Mode +#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL2_CIM_ONCE 0x00000001 ///< Once +#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 ///< Hysteresis Always +#define ADC_DCCTL2_CIM_HONCE 0x00000003 ///< Hysteresis Once + + +/* + * The following are defines for the bit fields in the ADC_O_DCCTL3 register. + */ +#define ADC_DCCTL3_CTE 0x00001000 ///< Comparison Trigger Enable +#define ADC_DCCTL3_CTC_M 0x00000C00 ///< Comparison Trigger Condition +#define ADC_DCCTL3_CTC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL3_CTC_MID 0x00000400 ///< Mid Band +#define ADC_DCCTL3_CTC_HIGH 0x00000C00 ///< High Band +#define ADC_DCCTL3_CTM_M 0x00000300 ///< Comparison Trigger Mode +#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL3_CTM_ONCE 0x00000100 ///< Once +#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 ///< Hysteresis Always +#define ADC_DCCTL3_CTM_HONCE 0x00000300 ///< Hysteresis Once +#define ADC_DCCTL3_CIE 0x00000010 ///< Comparison Interrupt Enable +#define ADC_DCCTL3_CIC_M 0x0000000C ///< Comparison Interrupt Condition +#define ADC_DCCTL3_CIC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL3_CIC_MID 0x00000004 ///< Mid Band +#define ADC_DCCTL3_CIC_HIGH 0x0000000C ///< High Band +#define ADC_DCCTL3_CIM_M 0x00000003 ///< Comparison Interrupt Mode +#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL3_CIM_ONCE 0x00000001 ///< Once +#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 ///< Hysteresis Always +#define ADC_DCCTL3_CIM_HONCE 0x00000003 ///< Hysteresis Once + + +/* + * The following are defines for the bit fields in the ADC_O_DCCTL4 register. + */ +#define ADC_DCCTL4_CTE 0x00001000 ///< Comparison Trigger Enable +#define ADC_DCCTL4_CTC_M 0x00000C00 ///< Comparison Trigger Condition +#define ADC_DCCTL4_CTC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL4_CTC_MID 0x00000400 ///< Mid Band +#define ADC_DCCTL4_CTC_HIGH 0x00000C00 ///< High Band +#define ADC_DCCTL4_CTM_M 0x00000300 ///< Comparison Trigger Mode +#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL4_CTM_ONCE 0x00000100 ///< Once +#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 ///< Hysteresis Always +#define ADC_DCCTL4_CTM_HONCE 0x00000300 ///< Hysteresis Once +#define ADC_DCCTL4_CIE 0x00000010 ///< Comparison Interrupt Enable +#define ADC_DCCTL4_CIC_M 0x0000000C ///< Comparison Interrupt Condition +#define ADC_DCCTL4_CIC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL4_CIC_MID 0x00000004 ///< Mid Band +#define ADC_DCCTL4_CIC_HIGH 0x0000000C ///< High Band +#define ADC_DCCTL4_CIM_M 0x00000003 ///< Comparison Interrupt Mode +#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL4_CIM_ONCE 0x00000001 ///< Once +#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 ///< Hysteresis Always +#define ADC_DCCTL4_CIM_HONCE 0x00000003 ///< Hysteresis Once + + +/* + * The following are defines for the bit fields in the ADC_O_DCCTL5 register. + */ +#define ADC_DCCTL5_CTE 0x00001000 ///< Comparison Trigger Enable +#define ADC_DCCTL5_CTC_M 0x00000C00 ///< Comparison Trigger Condition +#define ADC_DCCTL5_CTC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL5_CTC_MID 0x00000400 ///< Mid Band +#define ADC_DCCTL5_CTC_HIGH 0x00000C00 ///< High Band +#define ADC_DCCTL5_CTM_M 0x00000300 ///< Comparison Trigger Mode +#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL5_CTM_ONCE 0x00000100 ///< Once +#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 ///< Hysteresis Always +#define ADC_DCCTL5_CTM_HONCE 0x00000300 ///< Hysteresis Once +#define ADC_DCCTL5_CIE 0x00000010 ///< Comparison Interrupt Enable +#define ADC_DCCTL5_CIC_M 0x0000000C ///< Comparison Interrupt Condition +#define ADC_DCCTL5_CIC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL5_CIC_MID 0x00000004 ///< Mid Band +#define ADC_DCCTL5_CIC_HIGH 0x0000000C ///< High Band +#define ADC_DCCTL5_CIM_M 0x00000003 ///< Comparison Interrupt Mode +#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL5_CIM_ONCE 0x00000001 ///< Once +#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 ///< Hysteresis Always +#define ADC_DCCTL5_CIM_HONCE 0x00000003 ///< Hysteresis Once + + +/* + * The following are defines for the bit fields in the ADC_O_DCCTL6 register. + */ +#define ADC_DCCTL6_CTE 0x00001000 ///< Comparison Trigger Enable +#define ADC_DCCTL6_CTC_M 0x00000C00 ///< Comparison Trigger Condition +#define ADC_DCCTL6_CTC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL6_CTC_MID 0x00000400 ///< Mid Band +#define ADC_DCCTL6_CTC_HIGH 0x00000C00 ///< High Band +#define ADC_DCCTL6_CTM_M 0x00000300 ///< Comparison Trigger Mode +#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL6_CTM_ONCE 0x00000100 ///< Once +#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 ///< Hysteresis Always +#define ADC_DCCTL6_CTM_HONCE 0x00000300 ///< Hysteresis Once +#define ADC_DCCTL6_CIE 0x00000010 ///< Comparison Interrupt Enable +#define ADC_DCCTL6_CIC_M 0x0000000C ///< Comparison Interrupt Condition +#define ADC_DCCTL6_CIC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL6_CIC_MID 0x00000004 ///< Mid Band +#define ADC_DCCTL6_CIC_HIGH 0x0000000C ///< High Band +#define ADC_DCCTL6_CIM_M 0x00000003 ///< Comparison Interrupt Mode +#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL6_CIM_ONCE 0x00000001 ///< Once +#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 ///< Hysteresis Always +#define ADC_DCCTL6_CIM_HONCE 0x00000003 ///< Hysteresis Once + + +/* + * The following are defines for the bit fields in the ADC_O_DCCTL7 register. + */ +#define ADC_DCCTL7_CTE 0x00001000 ///< Comparison Trigger Enable +#define ADC_DCCTL7_CTC_M 0x00000C00 ///< Comparison Trigger Condition +#define ADC_DCCTL7_CTC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL7_CTC_MID 0x00000400 ///< Mid Band +#define ADC_DCCTL7_CTC_HIGH 0x00000C00 ///< High Band +#define ADC_DCCTL7_CTM_M 0x00000300 ///< Comparison Trigger Mode +#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL7_CTM_ONCE 0x00000100 ///< Once +#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 ///< Hysteresis Always +#define ADC_DCCTL7_CTM_HONCE 0x00000300 ///< Hysteresis Once +#define ADC_DCCTL7_CIE 0x00000010 ///< Comparison Interrupt Enable +#define ADC_DCCTL7_CIC_M 0x0000000C ///< Comparison Interrupt Condition +#define ADC_DCCTL7_CIC_LOW 0x00000000 ///< Low Band +#define ADC_DCCTL7_CIC_MID 0x00000004 ///< Mid Band +#define ADC_DCCTL7_CIC_HIGH 0x0000000C ///< High Band +#define ADC_DCCTL7_CIM_M 0x00000003 ///< Comparison Interrupt Mode +#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 ///< Always +#define ADC_DCCTL7_CIM_ONCE 0x00000001 ///< Once +#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 ///< Hysteresis Always +#define ADC_DCCTL7_CIM_HONCE 0x00000003 ///< Hysteresis Once + + +/* + * The following are defines for the bit fields in the ADC_O_DCCMP0 register. + */ +#define ADC_DCCMP0_COMP1_M 0x03FF0000 ///< Compare 1 +#define ADC_DCCMP0_COMP0_M 0x000003FF ///< Compare 0 +#define ADC_DCCMP0_COMP1_S 16 +#define ADC_DCCMP0_COMP0_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_DCCMP1 register. + */ +#define ADC_DCCMP1_COMP1_M 0x03FF0000 ///< Compare 1 +#define ADC_DCCMP1_COMP0_M 0x000003FF ///< Compare 0 +#define ADC_DCCMP1_COMP1_S 16 +#define ADC_DCCMP1_COMP0_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_DCCMP2 register. + */ +#define ADC_DCCMP2_COMP1_M 0x03FF0000 ///< Compare 1 +#define ADC_DCCMP2_COMP0_M 0x000003FF ///< Compare 0 +#define ADC_DCCMP2_COMP1_S 16 +#define ADC_DCCMP2_COMP0_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_DCCMP3 register. + */ +#define ADC_DCCMP3_COMP1_M 0x03FF0000 ///< Compare 1 +#define ADC_DCCMP3_COMP0_M 0x000003FF ///< Compare 0 +#define ADC_DCCMP3_COMP1_S 16 +#define ADC_DCCMP3_COMP0_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_DCCMP4 register. + */ +#define ADC_DCCMP4_COMP1_M 0x03FF0000 ///< Compare 1 +#define ADC_DCCMP4_COMP0_M 0x000003FF ///< Compare 0 +#define ADC_DCCMP4_COMP1_S 16 +#define ADC_DCCMP4_COMP0_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_DCCMP5 register. + */ +#define ADC_DCCMP5_COMP1_M 0x03FF0000 ///< Compare 1 +#define ADC_DCCMP5_COMP0_M 0x000003FF ///< Compare 0 +#define ADC_DCCMP5_COMP1_S 16 +#define ADC_DCCMP5_COMP0_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_DCCMP6 register. + */ +#define ADC_DCCMP6_COMP1_M 0x03FF0000 ///< Compare 1 +#define ADC_DCCMP6_COMP0_M 0x000003FF ///< Compare 0 +#define ADC_DCCMP6_COMP1_S 16 +#define ADC_DCCMP6_COMP0_S 0 + + +/* + * The following are defines for the bit fields in the ADC_O_DCCMP7 register. + */ +#define ADC_DCCMP7_COMP1_M 0x03FF0000 ///< Compare 1 +#define ADC_DCCMP7_COMP0_M 0x000003FF ///< Compare 0 +#define ADC_DCCMP7_COMP1_S 16 +#define ADC_DCCMP7_COMP0_S 0 + + +/* + * The following are defines for the the interpretation of the data in the + * SSFIFOx when the ADC TMLB is enabled. + */ + +#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 ///< Continuous Sample Counter +#define ADC_SSFIFO_TMLB_CONT 0x00000020 ///< Continuation Sample Indicator +#define ADC_SSFIFO_TMLB_DIFF 0x00000010 ///< Differential Sample Indicator +#define ADC_SSFIFO_TMLB_TS 0x00000008 ///< Temp Sensor Sample Indicator +#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 ///< Analog Input Indicator +#define ADC_SSFIFO_TMLB_CNT_S 6 ///< Sample counter shift +#define ADC_SSFIFO_TMLB_MUX_S 0 ///< Input channel number shift + +#endif /* LM3S_ADC_H */ diff --git a/bertos/cpu/cortex-m3/io/lm3s_com.h b/bertos/cpu/cortex-m3/io/lm3s_com.h index 4ffdc0d1..ee871584 100644 --- a/bertos/cpu/cortex-m3/io/lm3s_com.h +++ b/bertos/cpu/cortex-m3/io/lm3s_com.h @@ -1944,416 +1944,6 @@ #define TIMER_TBR_TBRL_S 0 /*\}*/ -/** - * The following are defines for the bit fields in the ADC_O_ACTSS register. - */ -/*\{*/ -#define ADC_ACTSS_ASEN3 0x00000008 ///< ADC SS3 Enable -#define ADC_ACTSS_ASEN2 0x00000004 ///< ADC SS2 Enable -#define ADC_ACTSS_ASEN1 0x00000002 ///< ADC SS1 Enable -#define ADC_ACTSS_ASEN0 0x00000001 ///< ADC SS0 Enable -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_RIS register. - */ -/*\{*/ -#define ADC_RIS_INR3 0x00000008 ///< SS3 Raw Interrupt Status -#define ADC_RIS_INR2 0x00000004 ///< SS2 Raw Interrupt Status -#define ADC_RIS_INR1 0x00000002 ///< SS1 Raw Interrupt Status -#define ADC_RIS_INR0 0x00000001 ///< SS0 Raw Interrupt Status -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_IM register. - */ -/*\{*/ -#define ADC_IM_MASK3 0x00000008 ///< SS3 Interrupt Mask -#define ADC_IM_MASK2 0x00000004 ///< SS2 Interrupt Mask -#define ADC_IM_MASK1 0x00000002 ///< SS1 Interrupt Mask -#define ADC_IM_MASK0 0x00000001 ///< SS0 Interrupt Mask -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_ISC register. - */ -/*\{*/ -#define ADC_ISC_IN3 0x00000008 ///< SS3 Interrupt Status and Clear -#define ADC_ISC_IN2 0x00000004 ///< SS2 Interrupt Status and Clear -#define ADC_ISC_IN1 0x00000002 ///< SS1 Interrupt Status and Clear -#define ADC_ISC_IN0 0x00000001 ///< SS0 Interrupt Status and Clear -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_OSTAT register. - */ -/*\{*/ -#define ADC_OSTAT_OV3 0x00000008 ///< SS3 FIFO Overflow -#define ADC_OSTAT_OV2 0x00000004 ///< SS2 FIFO Overflow -#define ADC_OSTAT_OV1 0x00000002 ///< SS1 FIFO Overflow -#define ADC_OSTAT_OV0 0x00000001 ///< SS0 FIFO Overflow -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_EMUX register. - */ -/*\{*/ -#define ADC_EMUX_EM3_M 0x0000F000 ///< SS3 Trigger Select -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 ///< Processor (default) -#define ADC_EMUX_EM3_COMP0 0x00001000 ///< Analog Comparator 0 -#define ADC_EMUX_EM3_COMP1 0x00002000 ///< Analog Comparator 1 -#define ADC_EMUX_EM3_COMP2 0x00003000 ///< Analog Comparator 2 -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 ///< External (GPIO PB4) -#define ADC_EMUX_EM3_TIMER 0x00005000 ///< Timer -#define ADC_EMUX_EM3_PWM0 0x00006000 ///< PWM0 -#define ADC_EMUX_EM3_PWM1 0x00007000 ///< PWM1 -#define ADC_EMUX_EM3_PWM2 0x00008000 ///< PWM2 -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 ///< Always (continuously sample) -#define ADC_EMUX_EM2_M 0x00000F00 ///< SS2 Trigger Select -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 ///< Processor (default) -#define ADC_EMUX_EM2_COMP0 0x00000100 ///< Analog Comparator 0 -#define ADC_EMUX_EM2_COMP1 0x00000200 ///< Analog Comparator 1 -#define ADC_EMUX_EM2_COMP2 0x00000300 ///< Analog Comparator 2 -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 ///< External (GPIO PB4) -#define ADC_EMUX_EM2_TIMER 0x00000500 ///< Timer -#define ADC_EMUX_EM2_PWM0 0x00000600 ///< PWM0 -#define ADC_EMUX_EM2_PWM1 0x00000700 ///< PWM1 -#define ADC_EMUX_EM2_PWM2 0x00000800 ///< PWM2 -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 ///< Always (continuously sample) -#define ADC_EMUX_EM1_M 0x000000F0 ///< SS1 Trigger Select -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 ///< Processor (default) -#define ADC_EMUX_EM1_COMP0 0x00000010 ///< Analog Comparator 0 -#define ADC_EMUX_EM1_COMP1 0x00000020 ///< Analog Comparator 1 -#define ADC_EMUX_EM1_COMP2 0x00000030 ///< Analog Comparator 2 -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 ///< External (GPIO PB4) -#define ADC_EMUX_EM1_TIMER 0x00000050 ///< Timer -#define ADC_EMUX_EM1_PWM0 0x00000060 ///< PWM0 -#define ADC_EMUX_EM1_PWM1 0x00000070 ///< PWM1 -#define ADC_EMUX_EM1_PWM2 0x00000080 ///< PWM2 -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 ///< Always (continuously sample) -#define ADC_EMUX_EM0_M 0x0000000F ///< SS0 Trigger Select -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 ///< Processor (default) -#define ADC_EMUX_EM0_COMP0 0x00000001 ///< Analog Comparator 0 -#define ADC_EMUX_EM0_COMP1 0x00000002 ///< Analog Comparator 1 -#define ADC_EMUX_EM0_COMP2 0x00000003 ///< Analog Comparator 2 -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 ///< External (GPIO PB4) -#define ADC_EMUX_EM0_TIMER 0x00000005 ///< Timer -#define ADC_EMUX_EM0_PWM0 0x00000006 ///< PWM0 -#define ADC_EMUX_EM0_PWM1 0x00000007 ///< PWM1 -#define ADC_EMUX_EM0_PWM2 0x00000008 ///< PWM2 -#define ADC_EMUX_EM0_ALWAYS 0x0000000F ///< Always (continuously sample) -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_USTAT register. - */ -/*\{*/ -#define ADC_USTAT_UV3 0x00000008 ///< SS3 FIFO Underflow -#define ADC_USTAT_UV2 0x00000004 ///< SS2 FIFO Underflow -#define ADC_USTAT_UV1 0x00000002 ///< SS1 FIFO Underflow -#define ADC_USTAT_UV0 0x00000001 ///< SS0 FIFO Underflow -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSPRI register. - */ -/*\{*/ -#define ADC_SSPRI_SS3_M 0x00003000 ///< SS3 Priority -#define ADC_SSPRI_SS3_1ST 0x00000000 ///< First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 ///< Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 ///< Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 ///< Fourth priority -#define ADC_SSPRI_SS2_M 0x00000300 ///< SS2 Priority -#define ADC_SSPRI_SS2_1ST 0x00000000 ///< First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 ///< Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 ///< Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 ///< Fourth priority -#define ADC_SSPRI_SS1_M 0x00000030 ///< SS1 Priority -#define ADC_SSPRI_SS1_1ST 0x00000000 ///< First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 ///< Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 ///< Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 ///< Fourth priority -#define ADC_SSPRI_SS0_M 0x00000003 ///< SS0 Priority -#define ADC_SSPRI_SS0_1ST 0x00000000 ///< First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 ///< Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 ///< Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 ///< Fourth priority -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_PSSI register. - */ -/*\{*/ -#define ADC_PSSI_SS3 0x00000008 ///< SS3 Initiate -#define ADC_PSSI_SS2 0x00000004 ///< SS2 Initiate -#define ADC_PSSI_SS1 0x00000002 ///< SS1 Initiate -#define ADC_PSSI_SS0 0x00000001 ///< SS0 Initiate -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SAC register. - */ -/*\{*/ -#define ADC_SAC_AVG_M 0x00000007 ///< Hardware Averaging Control -#define ADC_SAC_AVG_OFF 0x00000000 ///< No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 ///< 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 ///< 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 ///< 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 ///< 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 ///< 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 ///< 64x hardware oversampling -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSMUX0 register. - */ -/*\{*/ -#define ADC_SSMUX0_MUX7_M 0x70000000 ///< 8th Sample Input Select -#define ADC_SSMUX0_MUX6_M 0x07000000 ///< 7th Sample Input Select -#define ADC_SSMUX0_MUX5_M 0x00700000 ///< 6th Sample Input Select -#define ADC_SSMUX0_MUX4_M 0x00070000 ///< 5th Sample Input Select -#define ADC_SSMUX0_MUX3_M 0x00007000 ///< 4th Sample Input Select -#define ADC_SSMUX0_MUX2_M 0x00000700 ///< 3rd Sample Input Select -#define ADC_SSMUX0_MUX1_M 0x00000070 ///< 2nd Sample Input Select -#define ADC_SSMUX0_MUX0_M 0x00000007 ///< 1st Sample Input Select -#define ADC_SSMUX0_MUX7_S 28 -#define ADC_SSMUX0_MUX6_S 24 -#define ADC_SSMUX0_MUX5_S 20 -#define ADC_SSMUX0_MUX4_S 16 -#define ADC_SSMUX0_MUX3_S 12 -#define ADC_SSMUX0_MUX2_S 8 -#define ADC_SSMUX0_MUX1_S 4 -#define ADC_SSMUX0_MUX0_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSCTL0 register. - */ -/*\{*/ -#define ADC_SSCTL0_TS7 0x80000000 ///< 8th Sample Temp Sensor Select -#define ADC_SSCTL0_IE7 0x40000000 ///< 8th Sample Interrupt Enable -#define ADC_SSCTL0_END7 0x20000000 ///< 8th Sample is End of Sequence -#define ADC_SSCTL0_D7 0x10000000 ///< 8th Sample Diff Input Select -#define ADC_SSCTL0_TS6 0x08000000 ///< 7th Sample Temp Sensor Select -#define ADC_SSCTL0_IE6 0x04000000 ///< 7th Sample Interrupt Enable -#define ADC_SSCTL0_END6 0x02000000 ///< 7th Sample is End of Sequence -#define ADC_SSCTL0_D6 0x01000000 ///< 7th Sample Diff Input Select -#define ADC_SSCTL0_TS5 0x00800000 ///< 6th Sample Temp Sensor Select -#define ADC_SSCTL0_IE5 0x00400000 ///< 6th Sample Interrupt Enable -#define ADC_SSCTL0_END5 0x00200000 ///< 6th Sample is End of Sequence -#define ADC_SSCTL0_D5 0x00100000 ///< 6th Sample Diff Input Select -#define ADC_SSCTL0_TS4 0x00080000 ///< 5th Sample Temp Sensor Select -#define ADC_SSCTL0_IE4 0x00040000 ///< 5th Sample Interrupt Enable -#define ADC_SSCTL0_END4 0x00020000 ///< 5th Sample is End of Sequence -#define ADC_SSCTL0_D4 0x00010000 ///< 5th Sample Diff Input Select -#define ADC_SSCTL0_TS3 0x00008000 ///< 4th Sample Temp Sensor Select -#define ADC_SSCTL0_IE3 0x00004000 ///< 4th Sample Interrupt Enable -#define ADC_SSCTL0_END3 0x00002000 ///< 4th Sample is End of Sequence -#define ADC_SSCTL0_D3 0x00001000 ///< 4th Sample Diff Input Select -#define ADC_SSCTL0_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select -#define ADC_SSCTL0_IE2 0x00000400 ///< 3rd Sample Interrupt Enable -#define ADC_SSCTL0_END2 0x00000200 ///< 3rd Sample is End of Sequence -#define ADC_SSCTL0_D2 0x00000100 ///< 3rd Sample Diff Input Select -#define ADC_SSCTL0_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select -#define ADC_SSCTL0_IE1 0x00000040 ///< 2nd Sample Interrupt Enable -#define ADC_SSCTL0_END1 0x00000020 ///< 2nd Sample is End of Sequence -#define ADC_SSCTL0_D1 0x00000010 ///< 2nd Sample Diff Input Select -#define ADC_SSCTL0_TS0 0x00000008 ///< 1st Sample Temp Sensor Select -#define ADC_SSCTL0_IE0 0x00000004 ///< 1st Sample Interrupt Enable -#define ADC_SSCTL0_END0 0x00000002 ///< 1st Sample is End of Sequence -#define ADC_SSCTL0_D0 0x00000001 ///< 1st Sample Diff Input Select -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSFIFO0 register. - */ -/*\{*/ -#define ADC_SSFIFO0_DATA_M 0x000003FF ///< Conversion Result Data -#define ADC_SSFIFO0_DATA_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. - */ -/*\{*/ -#define ADC_SSFSTAT0_FULL 0x00001000 ///< FIFO Full -#define ADC_SSFSTAT0_EMPTY 0x00000100 ///< FIFO Empty -#define ADC_SSFSTAT0_HPTR_M 0x000000F0 ///< FIFO Head Pointer -#define ADC_SSFSTAT0_TPTR_M 0x0000000F ///< FIFO Tail Pointer -#define ADC_SSFSTAT0_HPTR_S 4 -#define ADC_SSFSTAT0_TPTR_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSMUX1 register. - */ -/*\{*/ -#define ADC_SSMUX1_MUX3_M 0x00007000 ///< 4th Sample Input Select -#define ADC_SSMUX1_MUX2_M 0x00000700 ///< 3rd Sample Input Select -#define ADC_SSMUX1_MUX1_M 0x00000070 ///< 2nd Sample Input Select -#define ADC_SSMUX1_MUX0_M 0x00000007 ///< 1st Sample Input Select -#define ADC_SSMUX1_MUX3_S 12 -#define ADC_SSMUX1_MUX2_S 8 -#define ADC_SSMUX1_MUX1_S 4 -#define ADC_SSMUX1_MUX0_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSCTL1 register. - */ -/*\{*/ -#define ADC_SSCTL1_TS3 0x00008000 ///< 4th Sample Temp Sensor Select -#define ADC_SSCTL1_IE3 0x00004000 ///< 4th Sample Interrupt Enable -#define ADC_SSCTL1_END3 0x00002000 ///< 4th Sample is End of Sequence -#define ADC_SSCTL1_D3 0x00001000 ///< 4th Sample Diff Input Select -#define ADC_SSCTL1_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select -#define ADC_SSCTL1_IE2 0x00000400 ///< 3rd Sample Interrupt Enable -#define ADC_SSCTL1_END2 0x00000200 ///< 3rd Sample is End of Sequence -#define ADC_SSCTL1_D2 0x00000100 ///< 3rd Sample Diff Input Select -#define ADC_SSCTL1_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select -#define ADC_SSCTL1_IE1 0x00000040 ///< 2nd Sample Interrupt Enable -#define ADC_SSCTL1_END1 0x00000020 ///< 2nd Sample is End of Sequence -#define ADC_SSCTL1_D1 0x00000010 ///< 2nd Sample Diff Input Select -#define ADC_SSCTL1_TS0 0x00000008 ///< 1st Sample Temp Sensor Select -#define ADC_SSCTL1_IE0 0x00000004 ///< 1st Sample Interrupt Enable -#define ADC_SSCTL1_END0 0x00000002 ///< 1st Sample is End of Sequence -#define ADC_SSCTL1_D0 0x00000001 ///< 1st Sample Diff Input Select -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSFIFO1 register. - */ -/*\{*/ -#define ADC_SSFIFO1_DATA_M 0x000003FF ///< Conversion Result Data -#define ADC_SSFIFO1_DATA_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. - */ -/*\{*/ -#define ADC_SSFSTAT1_FULL 0x00001000 ///< FIFO Full -#define ADC_SSFSTAT1_EMPTY 0x00000100 ///< FIFO Empty -#define ADC_SSFSTAT1_HPTR_M 0x000000F0 ///< FIFO Head Pointer -#define ADC_SSFSTAT1_TPTR_M 0x0000000F ///< FIFO Tail Pointer -#define ADC_SSFSTAT1_HPTR_S 4 -#define ADC_SSFSTAT1_TPTR_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSMUX2 register. - */ -/*\{*/ -#define ADC_SSMUX2_MUX3_M 0x00007000 ///< 4th Sample Input Select -#define ADC_SSMUX2_MUX2_M 0x00000700 ///< 3rd Sample Input Select -#define ADC_SSMUX2_MUX1_M 0x00000070 ///< 2nd Sample Input Select -#define ADC_SSMUX2_MUX0_M 0x00000007 ///< 1st Sample Input Select -#define ADC_SSMUX2_MUX3_S 12 -#define ADC_SSMUX2_MUX2_S 8 -#define ADC_SSMUX2_MUX1_S 4 -#define ADC_SSMUX2_MUX0_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSCTL2 register. - */ -/*\{*/ -#define ADC_SSCTL2_TS3 0x00008000 ///< 4th Sample Temp Sensor Select -#define ADC_SSCTL2_IE3 0x00004000 ///< 4th Sample Interrupt Enable -#define ADC_SSCTL2_END3 0x00002000 ///< 4th Sample is End of Sequence -#define ADC_SSCTL2_D3 0x00001000 ///< 4th Sample Diff Input Select -#define ADC_SSCTL2_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select -#define ADC_SSCTL2_IE2 0x00000400 ///< 3rd Sample Interrupt Enable -#define ADC_SSCTL2_END2 0x00000200 ///< 3rd Sample is End of Sequence -#define ADC_SSCTL2_D2 0x00000100 ///< 3rd Sample Diff Input Select -#define ADC_SSCTL2_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select -#define ADC_SSCTL2_IE1 0x00000040 ///< 2nd Sample Interrupt Enable -#define ADC_SSCTL2_END1 0x00000020 ///< 2nd Sample is End of Sequence -#define ADC_SSCTL2_D1 0x00000010 ///< 2nd Sample Diff Input Select -#define ADC_SSCTL2_TS0 0x00000008 ///< 1st Sample Temp Sensor Select -#define ADC_SSCTL2_IE0 0x00000004 ///< 1st Sample Interrupt Enable -#define ADC_SSCTL2_END0 0x00000002 ///< 1st Sample is End of Sequence -#define ADC_SSCTL2_D0 0x00000001 ///< 1st Sample Diff Input Select -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSFIFO2 register. - */ -/*\{*/ -#define ADC_SSFIFO2_DATA_M 0x000003FF ///< Conversion Result Data -#define ADC_SSFIFO2_DATA_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. - */ -/*\{*/ -#define ADC_SSFSTAT2_FULL 0x00001000 ///< FIFO Full -#define ADC_SSFSTAT2_EMPTY 0x00000100 ///< FIFO Empty -#define ADC_SSFSTAT2_HPTR_M 0x000000F0 ///< FIFO Head Pointer -#define ADC_SSFSTAT2_TPTR_M 0x0000000F ///< FIFO Tail Pointer -#define ADC_SSFSTAT2_HPTR_S 4 -#define ADC_SSFSTAT2_TPTR_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSMUX3 register. - */ -/*\{*/ -#define ADC_SSMUX3_MUX0_M 0x00000007 ///< 1st Sample Input Select -#define ADC_SSMUX3_MUX0_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSCTL3 register. - */ -/*\{*/ -#define ADC_SSCTL3_TS0 0x00000008 ///< 1st Sample Temp Sensor Select -#define ADC_SSCTL3_IE0 0x00000004 ///< 1st Sample Interrupt Enable -#define ADC_SSCTL3_END0 0x00000002 ///< 1st Sample is End of Sequence -#define ADC_SSCTL3_D0 0x00000001 ///< 1st Sample Diff Input Select -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSFIFO3 register. - */ -/*\{*/ -#define ADC_SSFIFO3_DATA_M 0x000003FF ///< Conversion Result Data -#define ADC_SSFIFO3_DATA_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. - */ -/*\{*/ -#define ADC_SSFSTAT3_FULL 0x00001000 ///< FIFO Full -#define ADC_SSFSTAT3_EMPTY 0x00000100 ///< FIFO Empty -#define ADC_SSFSTAT3_HPTR_M 0x000000F0 ///< FIFO Head Pointer -#define ADC_SSFSTAT3_TPTR_M 0x0000000F ///< FIFO Tail Pointer -#define ADC_SSFSTAT3_HPTR_S 4 -#define ADC_SSFSTAT3_TPTR_S 0 -/*\}*/ - -/** - * The following are defines for the bit fields in the ADC_O_TMLB register. - */ -/*\{*/ -#define ADC_TMLB_LB 0x00000001 ///< Loopback Mode Enable -/*\}*/ - -/** - * The following are defines for the the interpretation of the data in the -* SSFIFOx when the ADC TMLB is enabled. - */ -/*\{*/ -#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 ///< Continuous Sample Counter -#define ADC_SSFIFO_TMLB_CONT 0x00000020 ///< Continuation Sample Indicator -#define ADC_SSFIFO_TMLB_DIFF 0x00000010 ///< Differential Sample Indicator -#define ADC_SSFIFO_TMLB_TS 0x00000008 ///< Temp Sensor Sample Indicator -#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 ///< Analog Input Indicator -#define ADC_SSFIFO_TMLB_CNT_S 6 ///< Sample counter shift -#define ADC_SSFIFO_TMLB_MUX_S 0 ///< Input channel number shift -/*\}*/ /** * The following are defines for the bit fields in the COMP_O_ACMIS register. -- 2.25.1