From ffc9d84f819c7480515ece4417329f4972510462 Mon Sep 17 00:00:00 2001 From: arighi Date: Tue, 6 Apr 2010 09:28:20 +0000 Subject: [PATCH] CM3: use a distinct stack for handler-mode and thread-mode. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3395 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cpu/cortex-m3/hw/crt_cm3.S | 16 ++++++++++++++++ bertos/cpu/cortex-m3/hw/switch_ctx_cm3.S | 16 ++++++++++------ bertos/cpu/cortex-m3/scripts/lm3s1968_rom.ld | 13 +++++++++---- 3 files changed, 35 insertions(+), 10 deletions(-) diff --git a/bertos/cpu/cortex-m3/hw/crt_cm3.S b/bertos/cpu/cortex-m3/hw/crt_cm3.S index a442bc59..c23d8374 100644 --- a/bertos/cpu/cortex-m3/hw/crt_cm3.S +++ b/bertos/cpu/cortex-m3/hw/crt_cm3.S @@ -35,6 +35,9 @@ * \author Andrea Righi */ +#define CONTROL_UNPRIVILEGED 1 +#define CONTROL_PSP 2 + .syntax unified .thumb .section .init, "ax", %progbits @@ -61,6 +64,11 @@ __dummy_init: __init0: /* Disable IRQs */ cpsid i + /* + * Initialize process stack pointer. + */ + ldr r0, =__psp_end + msr psp, r0 /* Call the early hardware initialization routine */ bl __init1 @@ -86,10 +94,18 @@ bss_loop: strlo r0, [r1], #4 blo bss_loop + /* Switch to the process stack */ + movs r0, CONTROL_PSP + msr control, r0 + isb + /* Call the hardware initialization routine */ bl __init2 /* Call the application's entry point */ + cpsie i + mov r0, #0 + mov r1, #0 bl main end: wfi diff --git a/bertos/cpu/cortex-m3/hw/switch_ctx_cm3.S b/bertos/cpu/cortex-m3/hw/switch_ctx_cm3.S index bda6793c..e464d613 100644 --- a/bertos/cpu/cortex-m3/hw/switch_ctx_cm3.S +++ b/bertos/cpu/cortex-m3/hw/switch_ctx_cm3.S @@ -35,20 +35,24 @@ * \author Andrea Righi */ +#include + .syntax unified +#if !CONFIG_KERN_PREEMPT /* void asm_switch_context(void **new_sp [r0], void **save_sp [r1]) */ .global asm_switch_context .thumb_func asm_switch_context: - mrs r12, msp + mrs ip, psp /* Save registers */ - stmdb r12!, {r4-r11, lr} + stmdb ip!, {r4-r11, lr} /* Save old stack pointer */ - str r12, [r1] + str ip, [r1] /* Load new stack pointer */ - ldr r12, [r0] + ldr ip, [r0] /* Load new registers */ - ldmia r12!, {r4-r11, lr} - msr msp, r12 + ldmia ip!, {r4-r11, lr} + msr psp, ip bx lr +#endif /* CONFIG_KERN_PREEMPT */ diff --git a/bertos/cpu/cortex-m3/scripts/lm3s1968_rom.ld b/bertos/cpu/cortex-m3/scripts/lm3s1968_rom.ld index b93a49f1..e6c0e018 100644 --- a/bertos/cpu/cortex-m3/scripts/lm3s1968_rom.ld +++ b/bertos/cpu/cortex-m3/scripts/lm3s1968_rom.ld @@ -52,7 +52,7 @@ MEMORY /* * Define stack size here */ -MAIN_STACK_SIZE = 0x0400; +STACK_SIZE = 0x1000; /* * Allocate section memory @@ -103,10 +103,15 @@ SECTIONS * Allocated stack at the end of bss section. * Data heap is allocate at end of stack. */ - PROVIDE (__stack_start = .); + PROVIDE (__msp_start = .); . = ALIGN(4); - . += MAIN_STACK_SIZE; - PROVIDE (__stack_end = .); + . += STACK_SIZE; + PROVIDE (__msp_end = .); + + PROVIDE (__psp_start = .); + . = ALIGN(4); + . += STACK_SIZE; + PROVIDE (__psp_end = .); PROVIDE (__heap_start = .); . = ALIGN(4); -- 2.25.1