From: asterix Date: Tue, 27 Sep 2011 13:08:15 +0000 (+0000) Subject: Add some utility to get chip id for sam3. X-Git-Url: https://codewiz.org/gitweb?p=bertos.git;a=commitdiff_plain;h=8a38c90967d213502db928d94aeb484426621c05 Add some utility to get chip id for sam3. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@5100 38d2e660-2303-0410-9eaa-f027e97ec537 --- diff --git a/bertos/cpu/cortex-m3/io/sam3_chipid.c b/bertos/cpu/cortex-m3/io/sam3_chipid.c new file mode 100644 index 00000000..0175cb6e --- /dev/null +++ b/bertos/cpu/cortex-m3/io/sam3_chipid.c @@ -0,0 +1,182 @@ +/** + * \file + * + * + * \brief CHIP ID SAM3 definitions. + */ + +#include "sam3_chipid.h" + +#include + +static const char _unknown[] = "unknown"; +static const char * const chip_id_eproc_names[] = +{ + _unknown, // 0 + "arm946es", // 1 + "arm7tdmi", // 2 + "cortex-m3", // 3 + "arm920t", // 4 + "arm926ejs", // 5 + "cortex-a5", // 6 +}; + +const char *chipid_eproc_name(int idx) +{ + if (idx <= 6) + return chip_id_eproc_names[idx]; + + return _unknown; +} + +#define chip_id_nvpsize2 chip_id_nvpsize // these two tables are identical +static const char * const chip_id_nvpsize[] = +{ + "none", // 0 + "8K bytes", // 1 + "16K bytes", // 2 + "32K bytes", // 3 + _unknown, // 4 + "64K bytes", // 5 + _unknown, // 6 + "128K bytes", // 7 + _unknown, // 8 + "256K bytes", // 9 + "512K bytes", // 10 + _unknown, // 11 + "1024K bytes", // 12 + _unknown, // 13 + "2048K bytes", // 14 + _unknown, // 15 +}; + +const char *chipid_nvpsize(int idx) +{ + if (idx <= 15) + return chip_id_nvpsize[idx]; + + return _unknown; +} + + +static const char * const chip_id_sramsize[] = +{ + "48K Bytes", // 0 + "1K Bytes", // 1 + "2K Bytes", // 2 + "6K Bytes", // 3 + "112K Bytes", // 4 + "4K Bytes", // 5 + "80K Bytes", // 6 + "160K Bytes", // 7 + "8K Bytes", // 8 + "16K Bytes", // 9 + "32K Bytes", // 10 + "64K Bytes", // 11 + "128K Bytes", // 12 + "256K Bytes", // 13 + "96K Bytes", // 14 + "512K Bytes", // 15 + +}; + +const char *chipid_sramsize(int idx) +{ + if (idx <= 15) + return chip_id_sramsize[idx]; + + return _unknown; +} + + +static const struct archnames { unsigned value; const char *name; } chip_id_archnames[] = +{ + { 0x19, "AT91SAM9xx Series" }, + { 0x29, "AT91SAM9XExx Series" }, + { 0x34, "AT91x34 Series" }, + { 0x37, "CAP7 Series" }, + { 0x39, "CAP9 Series" }, + { 0x3B, "CAP11 Series" }, + { 0x40, "AT91x40 Series" }, + { 0x42, "AT91x42 Series" }, + { 0x55, "AT91x55 Series" }, + { 0x60, "AT91SAM7Axx Series" }, + { 0x61, "AT91SAM7AQxx Series" }, + { 0x63, "AT91x63 Series" }, + { 0x70, "AT91SAM7Sxx Series" }, + { 0x71, "AT91SAM7XCxx Series" }, + { 0x72, "AT91SAM7SExx Series" }, + { 0x73, "AT91SAM7Lxx Series" }, + { 0x75, "AT91SAM7Xxx Series" }, + { 0x76, "AT91SAM7SLxx Series" }, + { 0x80, "ATSAM3UxC Series (100-pin version)" }, + { 0x81, "ATSAM3UxE Series (144-pin version)" }, + { 0x83, "ATSAM3AxC Series (100-pin version)" }, + { 0x84, "ATSAM3XxC Series (100-pin version)" }, + { 0x85, "ATSAM3XxE Series (144-pin version)" }, + { 0x86, "ATSAM3XxG Series (208/217-pin version)" }, + { 0x88, "ATSAM3SxA Series (48-pin version)" }, + { 0x89, "ATSAM3SxB Series (64-pin version)" }, + { 0x8A, "ATSAM3SxC Series (100-pin version)" }, + { 0x92, "AT91x92 Series" }, + { 0x95, "ATSAM3NxC Series (100-pin version)" }, + { 0xF0, "AT75Cxx Series" }, + { -1, NULL }, + +}; + +const char *chipid_archnames(unsigned value) +{ + for (int i = 0; chip_id_archnames[i].name; i++) + { + if (chip_id_archnames[i].value == value) + return chip_id_archnames[i].name; + } + + return _unknown; +} + +static const char * const chip_id_nvptype[] = { + "rom", // 0 + "romless or onchip flash", // 1 + "embedded flash memory", // 2 + "rom(nvpsiz) + embedded flash (nvpsiz2)", //3 + "sram emulating flash", // 4 +}; + +const char *chipid_nvptype(int idx) +{ + if (idx <= 4) + return chip_id_nvptype[idx]; + + return _unknown; +} + diff --git a/bertos/cpu/cortex-m3/io/sam3_chipid.h b/bertos/cpu/cortex-m3/io/sam3_chipid.h new file mode 100644 index 00000000..ff2d1228 --- /dev/null +++ b/bertos/cpu/cortex-m3/io/sam3_chipid.h @@ -0,0 +1,78 @@ +/** + * \file + * + * + * \brief CHIP ID SAM3 definitions. + */ + +#ifndef SAM3_CHIPID_H +#define SAM3_CHIPID_H + +/** + * CHIP ID base registers addresses. + */ +#define CHIPID_CIDR (*((reg32_t *)(0x400E0940))) + +#define CHIPID_VERSION_MASK 0x1F +#define CHIPID_VERSION() ((CHIPID_CIDR) & CHIPID_VERSION_MASK) ///< Current version of the device. + +#define CHIPID_EPRCOC_SHIFT 5 +#define CHIPID_EPRCOC_MASK 0xE0 +#define CHIPID_EPRCOC() (((CHIPID_CIDR) & CHIPID_EPRCOC_MASK) >> CHIPID_EPRCOC_SHIFT) ///< Embedded processor. + +#define CHIPID_NVPSIZ_SHIFT 8 +#define CHIPID_NVPSIZ_MASK 0xF00 ///< Nonvolatile program memory size. +#define CHIPID_NVPSIZ() (((CHIPID_CIDR) & CHIPID_NVPSIZ_MASK) >> CHIPID_NVPSIZ_SHIFT) ///< Nonvolatile program memory size. + +#define CHIPID_NVPSIZ2_SHIFT 12 +#define CHIPID_NVPSIZ2_MASK 0xF000 ///< Second nonvolatile program memory size. +#define CHIPID_NVPSIZ2() (((CHIPID_CIDR) & CHIPID_NVPSIZ2_MASK) >> CHIPID_NVPSIZ2_SHIFT) ///< Second nonvolatile program memory size. + +#define CHIPID_SRAMSIZ_SHIFT 16 +#define CHIPID_SRAMSIZ_MASK 0xF0000 ///< Internal SRAM size. +#define CHIPID_SRAMSIZ() (((CHIPID_CIDR) & CHIPID_SRAMSIZ_MASK) >> CHIPID_SRAMSIZ_SHIFT) ///< Internal SRAM size. + +#define CHIPID_ARCH_SHIFT 20 +#define CHIPID_ARCH_MASK 0xFF00000 ///< Architecture identifier. +#define CHIPID_ARCH() (((CHIPID_CIDR) & CHIPID_ARCH_MASK) >> CHIPID_ARCH_SHIFT) ///< Architecture identifier. + +#define CHIPID_NVTYP_SHIFT 28 +#define CHIPID_NVTYP_MASK 0x70000000 ///< Nonvolatile program memory type. +#define CHIPID_NVTYP() (((CHIPID_CIDR) & CHIPID_NVTYP_MASK) >> CHIPID_NVTYP_SHIFT) ///< Nonvolatile program memory type. + + +const char *chipid_eproc_name(int idx); +const char *chipid_nvpsize(int idx); +const char *chipid_sramsize(int idx); +const char *chipid_archnames(unsigned value); +const char *chipid_nvptype(int idx); + +#endif /* SAM3_CHIPID_H */