From: batt Date: Fri, 2 Jul 2010 10:49:47 +0000 (+0000) Subject: Recode files to unix newlines. X-Git-Tag: 2.6.0~320 X-Git-Url: https://codewiz.org/gitweb?p=bertos.git;a=commitdiff_plain;h=d57ed7ecf592540f90a714813bd5619cac825306 Recode files to unix newlines. git-svn-id: https://src.develer.com/svnoss/bertos/trunk@3987 38d2e660-2303-0410-9eaa-f027e97ec537 --- diff --git a/bertos/cpu/arm/io/lpc23xx.h b/bertos/cpu/arm/io/lpc23xx.h index caee0953..3d0cdb10 100644 --- a/bertos/cpu/arm/io/lpc23xx.h +++ b/bertos/cpu/arm/io/lpc23xx.h @@ -1,1155 +1,1155 @@ -/** - * \file - * - * - * \author Francesco Sacchi - * - * LPC23xx I/O registers. - */ - -#ifndef LPC23XX_H -#define LPC23XX_H - -#include - -/* Vectored Interrupt Controller (VIC) */ -#define VIC_BASE_ADDR 0xFFFFF000 -#define VICIRQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x000)) -#define VICFIQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x004)) -#define VICRawIntr (*(reg32_t *)(VIC_BASE_ADDR + 0x008)) -#define VICIntSelect (*(reg32_t *)(VIC_BASE_ADDR + 0x00C)) -#define VICIntEnable (*(reg32_t *)(VIC_BASE_ADDR + 0x010)) -#define VICIntEnClr (*(reg32_t *)(VIC_BASE_ADDR + 0x014)) -#define VICSoftInt (*(reg32_t *)(VIC_BASE_ADDR + 0x018)) -#define VICSoftIntClr (*(reg32_t *)(VIC_BASE_ADDR + 0x01C)) -#define VICProtection (*(reg32_t *)(VIC_BASE_ADDR + 0x020)) -#define VICSWPrioMask (*(reg32_t *)(VIC_BASE_ADDR + 0x024)) - -#define VICVectAddr0 (*(reg32_t *)(VIC_BASE_ADDR + 0x100)) -#define VICVectAddr1 (*(reg32_t *)(VIC_BASE_ADDR + 0x104)) -#define VICVectAddr2 (*(reg32_t *)(VIC_BASE_ADDR + 0x108)) -#define VICVectAddr3 (*(reg32_t *)(VIC_BASE_ADDR + 0x10C)) -#define VICVectAddr4 (*(reg32_t *)(VIC_BASE_ADDR + 0x110)) -#define VICVectAddr5 (*(reg32_t *)(VIC_BASE_ADDR + 0x114)) -#define VICVectAddr6 (*(reg32_t *)(VIC_BASE_ADDR + 0x118)) -#define VICVectAddr7 (*(reg32_t *)(VIC_BASE_ADDR + 0x11C)) -#define VICVectAddr8 (*(reg32_t *)(VIC_BASE_ADDR + 0x120)) -#define VICVectAddr9 (*(reg32_t *)(VIC_BASE_ADDR + 0x124)) -#define VICVectAddr10 (*(reg32_t *)(VIC_BASE_ADDR + 0x128)) -#define VICVectAddr11 (*(reg32_t *)(VIC_BASE_ADDR + 0x12C)) -#define VICVectAddr12 (*(reg32_t *)(VIC_BASE_ADDR + 0x130)) -#define VICVectAddr13 (*(reg32_t *)(VIC_BASE_ADDR + 0x134)) -#define VICVectAddr14 (*(reg32_t *)(VIC_BASE_ADDR + 0x138)) -#define VICVectAddr15 (*(reg32_t *)(VIC_BASE_ADDR + 0x13C)) -#define VICVectAddr16 (*(reg32_t *)(VIC_BASE_ADDR + 0x140)) -#define VICVectAddr17 (*(reg32_t *)(VIC_BASE_ADDR + 0x144)) -#define VICVectAddr18 (*(reg32_t *)(VIC_BASE_ADDR + 0x148)) -#define VICVectAddr19 (*(reg32_t *)(VIC_BASE_ADDR + 0x14C)) -#define VICVectAddr20 (*(reg32_t *)(VIC_BASE_ADDR + 0x150)) -#define VICVectAddr21 (*(reg32_t *)(VIC_BASE_ADDR + 0x154)) -#define VICVectAddr22 (*(reg32_t *)(VIC_BASE_ADDR + 0x158)) -#define VICVectAddr23 (*(reg32_t *)(VIC_BASE_ADDR + 0x15C)) -#define VICVectAddr24 (*(reg32_t *)(VIC_BASE_ADDR + 0x160)) -#define VICVectAddr25 (*(reg32_t *)(VIC_BASE_ADDR + 0x164)) -#define VICVectAddr26 (*(reg32_t *)(VIC_BASE_ADDR + 0x168)) -#define VICVectAddr27 (*(reg32_t *)(VIC_BASE_ADDR + 0x16C)) -#define VICVectAddr28 (*(reg32_t *)(VIC_BASE_ADDR + 0x170)) -#define VICVectAddr29 (*(reg32_t *)(VIC_BASE_ADDR + 0x174)) -#define VICVectAddr30 (*(reg32_t *)(VIC_BASE_ADDR + 0x178)) -#define VICVectAddr31 (*(reg32_t *)(VIC_BASE_ADDR + 0x17C)) - -/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx, -these registers are known as "VICVectPriority(x)". */ -#define VICVectCntl0 (*(reg32_t *)(VIC_BASE_ADDR + 0x200)) -#define VICVectCntl1 (*(reg32_t *)(VIC_BASE_ADDR + 0x204)) -#define VICVectCntl2 (*(reg32_t *)(VIC_BASE_ADDR + 0x208)) -#define VICVectCntl3 (*(reg32_t *)(VIC_BASE_ADDR + 0x20C)) -#define VICVectCntl4 (*(reg32_t *)(VIC_BASE_ADDR + 0x210)) -#define VICVectCntl5 (*(reg32_t *)(VIC_BASE_ADDR + 0x214)) -#define VICVectCntl6 (*(reg32_t *)(VIC_BASE_ADDR + 0x218)) -#define VICVectCntl7 (*(reg32_t *)(VIC_BASE_ADDR + 0x21C)) -#define VICVectCntl8 (*(reg32_t *)(VIC_BASE_ADDR + 0x220)) -#define VICVectCntl9 (*(reg32_t *)(VIC_BASE_ADDR + 0x224)) -#define VICVectCntl10 (*(reg32_t *)(VIC_BASE_ADDR + 0x228)) -#define VICVectCntl11 (*(reg32_t *)(VIC_BASE_ADDR + 0x22C)) -#define VICVectCntl12 (*(reg32_t *)(VIC_BASE_ADDR + 0x230)) -#define VICVectCntl13 (*(reg32_t *)(VIC_BASE_ADDR + 0x234)) -#define VICVectCntl14 (*(reg32_t *)(VIC_BASE_ADDR + 0x238)) -#define VICVectCntl15 (*(reg32_t *)(VIC_BASE_ADDR + 0x23C)) -#define VICVectCntl16 (*(reg32_t *)(VIC_BASE_ADDR + 0x240)) -#define VICVectCntl17 (*(reg32_t *)(VIC_BASE_ADDR + 0x244)) -#define VICVectCntl18 (*(reg32_t *)(VIC_BASE_ADDR + 0x248)) -#define VICVectCntl19 (*(reg32_t *)(VIC_BASE_ADDR + 0x24C)) -#define VICVectCntl20 (*(reg32_t *)(VIC_BASE_ADDR + 0x250)) -#define VICVectCntl21 (*(reg32_t *)(VIC_BASE_ADDR + 0x254)) -#define VICVectCntl22 (*(reg32_t *)(VIC_BASE_ADDR + 0x258)) -#define VICVectCntl23 (*(reg32_t *)(VIC_BASE_ADDR + 0x25C)) -#define VICVectCntl24 (*(reg32_t *)(VIC_BASE_ADDR + 0x260)) -#define VICVectCntl25 (*(reg32_t *)(VIC_BASE_ADDR + 0x264)) -#define VICVectCntl26 (*(reg32_t *)(VIC_BASE_ADDR + 0x268)) -#define VICVectCntl27 (*(reg32_t *)(VIC_BASE_ADDR + 0x26C)) -#define VICVectCntl28 (*(reg32_t *)(VIC_BASE_ADDR + 0x270)) -#define VICVectCntl29 (*(reg32_t *)(VIC_BASE_ADDR + 0x274)) -#define VICVectCntl30 (*(reg32_t *)(VIC_BASE_ADDR + 0x278)) -#define VICVectCntl31 (*(reg32_t *)(VIC_BASE_ADDR + 0x27C)) - -#define VICVectAddr (*(reg32_t *)(VIC_BASE_ADDR + 0xF00)) - - -/* Pin Connect Block */ -#define PINSEL_BASE_ADDR 0xE002C000 -#define PINSEL0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x00)) -#define PINSEL1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x04)) -#define PINSEL2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x08)) -#define PINSEL3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x0C)) -#define PINSEL4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x10)) -#define PINSEL5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x14)) -#define PINSEL6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x18)) -#define PINSEL7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x1C)) -#define PINSEL8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x20)) -#define PINSEL9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x24)) -#define PINSEL10 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x28)) - -#define PINMODE0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x40)) -#define PINMODE1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x44)) -#define PINMODE2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x48)) -#define PINMODE3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x4C)) -#define PINMODE4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x50)) -#define PINMODE5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x54)) -#define PINMODE6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x58)) -#define PINMODE7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x5C)) -#define PINMODE8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x60)) -#define PINMODE9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x64)) - -/* General Purpose Input/Output (GPIO) */ -#define GPIO_BASE_ADDR 0xE0028000 -#define IOPIN0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x00)) -#define IOSET0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x04)) -#define IODIR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x08)) -#define IOCLR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x0C)) -#define IOPIN1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x10)) -#define IOSET1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x14)) -#define IODIR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x18)) -#define IOCLR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x1C)) - -/* GPIO Interrupt Registers */ -#define IO0_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x90)) -#define IO0_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x94)) -#define IO0_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x84)) -#define IO0_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x88)) -#define IO0_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0x8C)) - -#define IO2_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xB0)) -#define IO2_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xB4)) -#define IO2_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xA4)) -#define IO2_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xA8)) -#define IO2_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0xAC)) - -#define IO_INT_STAT (*(reg32_t *)(GPIO_BASE_ADDR + 0x80)) - -#define PARTCFG_BASE_ADDR 0x3FFF8000 -#define PARTCFG (*(reg32_t *)(PARTCFG_BASE_ADDR + 0x00)) - -/* Fast I/O setup */ -#define FIO_BASE_ADDR 0x3FFFC000 -#define FIO0DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x00)) -#define FIO0MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x10)) -#define FIO0PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x14)) -#define FIO0SET (*(reg32_t *)(FIO_BASE_ADDR + 0x18)) -#define FIO0CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x1C)) - -#define FIO1DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x20)) -#define FIO1MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x30)) -#define FIO1PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x34)) -#define FIO1SET (*(reg32_t *)(FIO_BASE_ADDR + 0x38)) -#define FIO1CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x3C)) - -#define FIO2DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x40)) -#define FIO2MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x50)) -#define FIO2PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x54)) -#define FIO2SET (*(reg32_t *)(FIO_BASE_ADDR + 0x58)) -#define FIO2CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x5C)) - -#define FIO3DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x60)) -#define FIO3MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x70)) -#define FIO3PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x74)) -#define FIO3SET (*(reg32_t *)(FIO_BASE_ADDR + 0x78)) -#define FIO3CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x7C)) - -#define FIO4DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x80)) -#define FIO4MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x90)) -#define FIO4PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x94)) -#define FIO4SET (*(reg32_t *)(FIO_BASE_ADDR + 0x98)) -#define FIO4CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x9C)) - -/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ -#define FIO0DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x80)) - -#define FIO0DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x01)) -#define FIO1DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21)) -#define FIO2DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x41)) -#define FIO3DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x61)) -#define FIO4DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x81)) - -#define FIO0DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x82)) - -#define FIO0DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x03)) -#define FIO1DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x23)) -#define FIO2DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x43)) -#define FIO3DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x63)) -#define FIO4DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x83)) - -#define FIO0DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x80)) - -#define FIO0DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x82)) - -#define FIO0MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x90)) - -#define FIO0MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x11)) -#define FIO1MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21)) -#define FIO2MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x51)) -#define FIO3MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x71)) -#define FIO4MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x91)) - -#define FIO0MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x92)) - -#define FIO0MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x13)) -#define FIO1MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x33)) -#define FIO2MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x53)) -#define FIO3MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x73)) -#define FIO4MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x93)) - -#define FIO0MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x90)) - -#define FIO0MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x92)) - -#define FIO0PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x94)) - -#define FIO0PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x15)) -#define FIO1PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x25)) -#define FIO2PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x55)) -#define FIO3PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x75)) -#define FIO4PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x95)) - -#define FIO0PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x96)) - -#define FIO0PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x17)) -#define FIO1PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x37)) -#define FIO2PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x57)) -#define FIO3PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x77)) -#define FIO4PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x97)) - -#define FIO0PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x94)) - -#define FIO0PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x96)) - -#define FIO0SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x98)) - -#define FIO0SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x19)) -#define FIO1SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x29)) -#define FIO2SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x59)) -#define FIO3SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x79)) -#define FIO4SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x99)) - -#define FIO0SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9A)) - -#define FIO0SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1B)) -#define FIO1SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3B)) -#define FIO2SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5B)) -#define FIO3SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7B)) -#define FIO4SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9B)) - -#define FIO0SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x98)) - -#define FIO0SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x9A)) - -#define FIO0CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x9C)) - -#define FIO0CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x1D)) -#define FIO1CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x2D)) -#define FIO2CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x5D)) -#define FIO3CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x7D)) -#define FIO4CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x9D)) - -#define FIO0CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9E)) - -#define FIO0CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1F)) -#define FIO1CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3F)) -#define FIO2CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5F)) -#define FIO3CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7F)) -#define FIO4CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9F)) - -#define FIO0CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x9C)) - -#define FIO0CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x9E)) - - -/* System Control Block(SCB) modules include Memory Accelerator Module, -Phase Locked Loop, VPB divider, Power Control, External Interrupt, -Reset, and Code Security/Debugging */ -#define SCB_BASE_ADDR 0xE01FC000 - -/* Memory Accelerator Module (MAM) */ -#define MAMCR (*(reg32_t *)(SCB_BASE_ADDR + 0x000)) -#define MAMTIM (*(reg32_t *)(SCB_BASE_ADDR + 0x004)) -#define MEMMAP (*(reg32_t *)(SCB_BASE_ADDR + 0x040)) - -/* Phase Locked Loop (PLL) */ -#define PLLCON (*(reg32_t *)(SCB_BASE_ADDR + 0x080)) -#define PLLCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x084)) -#define PLLSTAT (*(reg32_t *)(SCB_BASE_ADDR + 0x088)) -#define PLLFEED (*(reg32_t *)(SCB_BASE_ADDR + 0x08C)) - -/* Power Control */ -#define PCON (*(reg32_t *)(SCB_BASE_ADDR + 0x0C0)) -#define PCONP (*(reg32_t *)(SCB_BASE_ADDR + 0x0C4)) - -/* Clock Divider */ -// #define APBDIV (*(reg32_t *)(SCB_BASE_ADDR + 0x100)) -#define CCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x104)) -#define USBCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x108)) -#define CLKSRCSEL (*(reg32_t *)(SCB_BASE_ADDR + 0x10C)) -#define PCLKSEL0 (*(reg32_t *)(SCB_BASE_ADDR + 0x1A8)) -#define PCLKSEL1 (*(reg32_t *)(SCB_BASE_ADDR + 0x1AC)) - -/* External Interrupts */ -#define EXTINT (*(reg32_t *)(SCB_BASE_ADDR + 0x140)) -#define INTWAKE (*(reg32_t *)(SCB_BASE_ADDR + 0x144)) -#define EXTMODE (*(reg32_t *)(SCB_BASE_ADDR + 0x148)) -#define EXTPOLAR (*(reg32_t *)(SCB_BASE_ADDR + 0x14C)) - -/* Reset, reset source identification */ -#define RSIR (*(reg32_t *)(SCB_BASE_ADDR + 0x180)) - -/* RSID, code security protection */ -#define CSPR (*(reg32_t *)(SCB_BASE_ADDR + 0x184)) - -/* AHB configuration */ -#define AHBCFG1 (*(reg32_t *)(SCB_BASE_ADDR + 0x188)) -#define AHBCFG2 (*(reg32_t *)(SCB_BASE_ADDR + 0x18C)) - -/* System Controls and Status */ -#define SCS (*(reg32_t *)(SCB_BASE_ADDR + 0x1A0)) - -/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers -are for LPC24xx only. */ -#define STATIC_MEM0_BASE 0x80000000 -#define STATIC_MEM1_BASE 0x81000000 -#define STATIC_MEM2_BASE 0x82000000 -#define STATIC_MEM3_BASE 0x83000000 - -#define DYNAMIC_MEM0_BASE 0xA0000000 -#define DYNAMIC_MEM1_BASE 0xB0000000 -#define DYNAMIC_MEM2_BASE 0xC0000000 -#define DYNAMIC_MEM3_BASE 0xD0000000 - -/* External Memory Controller (EMC) */ -#define EMC_BASE_ADDR 0xFFE08000 -#define EMC_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x000)) -#define EMC_STAT (*(reg32_t *)(EMC_BASE_ADDR + 0x004)) -#define EMC_CONFIG (*(reg32_t *)(EMC_BASE_ADDR + 0x008)) - -/* Dynamic RAM access registers */ -#define EMC_DYN_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x020)) -#define EMC_DYN_RFSH (*(reg32_t *)(EMC_BASE_ADDR + 0x024)) -#define EMC_DYN_RD_CFG (*(reg32_t *)(EMC_BASE_ADDR + 0x028)) -#define EMC_DYN_RP (*(reg32_t *)(EMC_BASE_ADDR + 0x030)) -#define EMC_DYN_RAS (*(reg32_t *)(EMC_BASE_ADDR + 0x034)) -#define EMC_DYN_SREX (*(reg32_t *)(EMC_BASE_ADDR + 0x038)) -#define EMC_DYN_APR (*(reg32_t *)(EMC_BASE_ADDR + 0x03C)) -#define EMC_DYN_DAL (*(reg32_t *)(EMC_BASE_ADDR + 0x040)) -#define EMC_DYN_WR (*(reg32_t *)(EMC_BASE_ADDR + 0x044)) -#define EMC_DYN_RC (*(reg32_t *)(EMC_BASE_ADDR + 0x048)) -#define EMC_DYN_RFC (*(reg32_t *)(EMC_BASE_ADDR + 0x04C)) -#define EMC_DYN_XSR (*(reg32_t *)(EMC_BASE_ADDR + 0x050)) -#define EMC_DYN_RRD (*(reg32_t *)(EMC_BASE_ADDR + 0x054)) -#define EMC_DYN_MRD (*(reg32_t *)(EMC_BASE_ADDR + 0x058)) - -#define EMC_DYN_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x100)) -#define EMC_DYN_RASCAS0 (*(reg32_t *)(EMC_BASE_ADDR + 0x104)) -#define EMC_DYN_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x140)) -#define EMC_DYN_RASCAS1 (*(reg32_t *)(EMC_BASE_ADDR + 0x144)) -#define EMC_DYN_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x160)) -#define EMC_DYN_RASCAS2 (*(reg32_t *)(EMC_BASE_ADDR + 0x164)) -#define EMC_DYN_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x180)) -#define EMC_DYN_RASCAS3 (*(reg32_t *)(EMC_BASE_ADDR + 0x184)) - -/* static RAM access registers */ -#define EMC_STA_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x200)) -#define EMC_STA_WAITWEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x204)) -#define EMC_STA_WAITOEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x208)) -#define EMC_STA_WAITRD0 (*(reg32_t *)(EMC_BASE_ADDR + 0x20C)) -#define EMC_STA_WAITPAGE0 (*(reg32_t *)(EMC_BASE_ADDR + 0x210)) -#define EMC_STA_WAITWR0 (*(reg32_t *)(EMC_BASE_ADDR + 0x214)) -#define EMC_STA_WAITTURN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x218)) - -#define EMC_STA_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x220)) -#define EMC_STA_WAITWEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x224)) -#define EMC_STA_WAITOEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x228)) -#define EMC_STA_WAITRD1 (*(reg32_t *)(EMC_BASE_ADDR + 0x22C)) -#define EMC_STA_WAITPAGE1 (*(reg32_t *)(EMC_BASE_ADDR + 0x230)) -#define EMC_STA_WAITWR1 (*(reg32_t *)(EMC_BASE_ADDR + 0x234)) -#define EMC_STA_WAITTURN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x238)) - -#define EMC_STA_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x240)) -#define EMC_STA_WAITWEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x244)) -#define EMC_STA_WAITOEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x248)) -#define EMC_STA_WAITRD2 (*(reg32_t *)(EMC_BASE_ADDR + 0x24C)) -#define EMC_STA_WAITPAGE2 (*(reg32_t *)(EMC_BASE_ADDR + 0x250)) -#define EMC_STA_WAITWR2 (*(reg32_t *)(EMC_BASE_ADDR + 0x254)) -#define EMC_STA_WAITTURN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x258)) - -#define EMC_STA_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x260)) -#define EMC_STA_WAITWEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x264)) -#define EMC_STA_WAITOEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x268)) -#define EMC_STA_WAITRD3 (*(reg32_t *)(EMC_BASE_ADDR + 0x26C)) -#define EMC_STA_WAITPAGE3 (*(reg32_t *)(EMC_BASE_ADDR + 0x270)) -#define EMC_STA_WAITWR3 (*(reg32_t *)(EMC_BASE_ADDR + 0x274)) -#define EMC_STA_WAITTURN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x278)) - -#define EMC_STA_EXT_WAIT (*(reg32_t *)(EMC_BASE_ADDR + 0x880)) - - -/* Timer 0 */ -#define TMR0_BASE_ADDR 0xE0004000 -#define T0IR (*(reg32_t *)(TMR0_BASE_ADDR + 0x00)) -#define T0TCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x04)) -#define T0TC (*(reg32_t *)(TMR0_BASE_ADDR + 0x08)) -#define T0PR (*(reg32_t *)(TMR0_BASE_ADDR + 0x0C)) -#define T0PC (*(reg32_t *)(TMR0_BASE_ADDR + 0x10)) -#define T0MCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x14)) -#define T0MR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x18)) -#define T0MR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x1C)) -#define T0MR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x20)) -#define T0MR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x24)) -#define T0CCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x28)) -#define T0CR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x2C)) -#define T0CR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x30)) -#define T0CR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x34)) -#define T0CR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x38)) -#define T0EMR (*(reg32_t *)(TMR0_BASE_ADDR + 0x3C)) -#define T0CTCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x70)) - -/* Timer 1 */ -#define TMR1_BASE_ADDR 0xE0008000 -#define T1IR (*(reg32_t *)(TMR1_BASE_ADDR + 0x00)) -#define T1TCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x04)) -#define T1TC (*(reg32_t *)(TMR1_BASE_ADDR + 0x08)) -#define T1PR (*(reg32_t *)(TMR1_BASE_ADDR + 0x0C)) -#define T1PC (*(reg32_t *)(TMR1_BASE_ADDR + 0x10)) -#define T1MCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x14)) -#define T1MR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x18)) -#define T1MR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x1C)) -#define T1MR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x20)) -#define T1MR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x24)) -#define T1CCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x28)) -#define T1CR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x2C)) -#define T1CR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x30)) -#define T1CR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x34)) -#define T1CR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x38)) -#define T1EMR (*(reg32_t *)(TMR1_BASE_ADDR + 0x3C)) -#define T1CTCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x70)) - -/* Timer 2 */ -#define TMR2_BASE_ADDR 0xE0070000 -#define T2IR (*(reg32_t *)(TMR2_BASE_ADDR + 0x00)) -#define T2TCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x04)) -#define T2TC (*(reg32_t *)(TMR2_BASE_ADDR + 0x08)) -#define T2PR (*(reg32_t *)(TMR2_BASE_ADDR + 0x0C)) -#define T2PC (*(reg32_t *)(TMR2_BASE_ADDR + 0x10)) -#define T2MCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x14)) -#define T2MR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x18)) -#define T2MR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x1C)) -#define T2MR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x20)) -#define T2MR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x24)) -#define T2CCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x28)) -#define T2CR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x2C)) -#define T2CR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x30)) -#define T2CR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x34)) -#define T2CR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x38)) -#define T2EMR (*(reg32_t *)(TMR2_BASE_ADDR + 0x3C)) -#define T2CTCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x70)) - -/* Timer 3 */ -#define TMR3_BASE_ADDR 0xE0074000 -#define T3IR (*(reg32_t *)(TMR3_BASE_ADDR + 0x00)) -#define T3TCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x04)) -#define T3TC (*(reg32_t *)(TMR3_BASE_ADDR + 0x08)) -#define T3PR (*(reg32_t *)(TMR3_BASE_ADDR + 0x0C)) -#define T3PC (*(reg32_t *)(TMR3_BASE_ADDR + 0x10)) -#define T3MCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x14)) -#define T3MR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x18)) -#define T3MR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x1C)) -#define T3MR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x20)) -#define T3MR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x24)) -#define T3CCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x28)) -#define T3CR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x2C)) -#define T3CR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x30)) -#define T3CR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x34)) -#define T3CR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x38)) -#define T3EMR (*(reg32_t *)(TMR3_BASE_ADDR + 0x3C)) -#define T3CTCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x70)) - - -/* Pulse Width Modulator (PWM) */ -#define PWM0_BASE_ADDR 0xE0014000 -#define PWM0IR (*(reg32_t *)(PWM0_BASE_ADDR + 0x00)) -#define PWM0TCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x04)) -#define PWM0TC (*(reg32_t *)(PWM0_BASE_ADDR + 0x08)) -#define PWM0PR (*(reg32_t *)(PWM0_BASE_ADDR + 0x0C)) -#define PWM0PC (*(reg32_t *)(PWM0_BASE_ADDR + 0x10)) -#define PWM0MCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x14)) -#define PWM0MR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x18)) -#define PWM0MR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x1C)) -#define PWM0MR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x20)) -#define PWM0MR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x24)) -#define PWM0CCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x28)) -#define PWM0CR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x2C)) -#define PWM0CR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x30)) -#define PWM0CR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x34)) -#define PWM0CR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x38)) -#define PWM0EMR (*(reg32_t *)(PWM0_BASE_ADDR + 0x3C)) -#define PWM0MR4 (*(reg32_t *)(PWM0_BASE_ADDR + 0x40)) -#define PWM0MR5 (*(reg32_t *)(PWM0_BASE_ADDR + 0x44)) -#define PWM0MR6 (*(reg32_t *)(PWM0_BASE_ADDR + 0x48)) -#define PWM0PCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x4C)) -#define PWM0LER (*(reg32_t *)(PWM0_BASE_ADDR + 0x50)) -#define PWM0CTCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x70)) - -#define PWM1_BASE_ADDR 0xE0018000 -#define PWM1IR (*(reg32_t *)(PWM1_BASE_ADDR + 0x00)) -#define PWM1TCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x04)) -#define PWM1TC (*(reg32_t *)(PWM1_BASE_ADDR + 0x08)) -#define PWM1PR (*(reg32_t *)(PWM1_BASE_ADDR + 0x0C)) -#define PWM1PC (*(reg32_t *)(PWM1_BASE_ADDR + 0x10)) -#define PWM1MCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x14)) -#define PWM1MR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x18)) -#define PWM1MR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x1C)) -#define PWM1MR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x20)) -#define PWM1MR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x24)) -#define PWM1CCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x28)) -#define PWM1CR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x2C)) -#define PWM1CR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x30)) -#define PWM1CR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x34)) -#define PWM1CR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x38)) -#define PWM1EMR (*(reg32_t *)(PWM1_BASE_ADDR + 0x3C)) -#define PWM1MR4 (*(reg32_t *)(PWM1_BASE_ADDR + 0x40)) -#define PWM1MR5 (*(reg32_t *)(PWM1_BASE_ADDR + 0x44)) -#define PWM1MR6 (*(reg32_t *)(PWM1_BASE_ADDR + 0x48)) -#define PWM1PCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x4C)) -#define PWM1LER (*(reg32_t *)(PWM1_BASE_ADDR + 0x50)) -#define PWM1CTCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x70)) - - -/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ -#define UART0_BASE_ADDR 0xE000C000 -#define U0RBR (*(reg32_t *)(UART0_BASE_ADDR + 0x00)) -#define U0THR (*(reg32_t *)(UART0_BASE_ADDR + 0x00)) -#define U0DLL (*(reg32_t *)(UART0_BASE_ADDR + 0x00)) -#define U0DLM (*(reg32_t *)(UART0_BASE_ADDR + 0x04)) -#define U0IER (*(reg32_t *)(UART0_BASE_ADDR + 0x04)) -#define U0IIR (*(reg32_t *)(UART0_BASE_ADDR + 0x08)) -#define U0FCR (*(reg32_t *)(UART0_BASE_ADDR + 0x08)) -#define U0LCR (*(reg32_t *)(UART0_BASE_ADDR + 0x0C)) -#define U0LSR (*(reg32_t *)(UART0_BASE_ADDR + 0x14)) -#define U0SCR (*(reg32_t *)(UART0_BASE_ADDR + 0x1C)) -#define U0ACR (*(reg32_t *)(UART0_BASE_ADDR + 0x20)) -#define U0ICR (*(reg32_t *)(UART0_BASE_ADDR + 0x24)) -#define U0FDR (*(reg32_t *)(UART0_BASE_ADDR + 0x28)) -#define U0TER (*(reg32_t *)(UART0_BASE_ADDR + 0x30)) - -/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ -#define UART1_BASE_ADDR 0xE0010000 -#define U1RBR (*(reg32_t *)(UART1_BASE_ADDR + 0x00)) -#define U1THR (*(reg32_t *)(UART1_BASE_ADDR + 0x00)) -#define U1DLL (*(reg32_t *)(UART1_BASE_ADDR + 0x00)) -#define U1DLM (*(reg32_t *)(UART1_BASE_ADDR + 0x04)) -#define U1IER (*(reg32_t *)(UART1_BASE_ADDR + 0x04)) -#define U1IIR (*(reg32_t *)(UART1_BASE_ADDR + 0x08)) -#define U1FCR (*(reg32_t *)(UART1_BASE_ADDR + 0x08)) -#define U1LCR (*(reg32_t *)(UART1_BASE_ADDR + 0x0C)) -#define U1MCR (*(reg32_t *)(UART1_BASE_ADDR + 0x10)) -#define U1LSR (*(reg32_t *)(UART1_BASE_ADDR + 0x14)) -#define U1MSR (*(reg32_t *)(UART1_BASE_ADDR + 0x18)) -#define U1SCR (*(reg32_t *)(UART1_BASE_ADDR + 0x1C)) -#define U1ACR (*(reg32_t *)(UART1_BASE_ADDR + 0x20)) -#define U1FDR (*(reg32_t *)(UART1_BASE_ADDR + 0x28)) -#define U1TER (*(reg32_t *)(UART1_BASE_ADDR + 0x30)) - -/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ -#define UART2_BASE_ADDR 0xE0078000 -#define U2RBR (*(reg32_t *)(UART2_BASE_ADDR + 0x00)) -#define U2THR (*(reg32_t *)(UART2_BASE_ADDR + 0x00)) -#define U2DLL (*(reg32_t *)(UART2_BASE_ADDR + 0x00)) -#define U2DLM (*(reg32_t *)(UART2_BASE_ADDR + 0x04)) -#define U2IER (*(reg32_t *)(UART2_BASE_ADDR + 0x04)) -#define U2IIR (*(reg32_t *)(UART2_BASE_ADDR + 0x08)) -#define U2FCR (*(reg32_t *)(UART2_BASE_ADDR + 0x08)) -#define U2LCR (*(reg32_t *)(UART2_BASE_ADDR + 0x0C)) -#define U2LSR (*(reg32_t *)(UART2_BASE_ADDR + 0x14)) -#define U2SCR (*(reg32_t *)(UART2_BASE_ADDR + 0x1C)) -#define U2ACR (*(reg32_t *)(UART2_BASE_ADDR + 0x20)) -#define U2ICR (*(reg32_t *)(UART2_BASE_ADDR + 0x24)) -#define U2FDR (*(reg32_t *)(UART2_BASE_ADDR + 0x28)) -#define U2TER (*(reg32_t *)(UART2_BASE_ADDR + 0x30)) - -/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ -#define UART3_BASE_ADDR 0xE007C000 -#define U3RBR (*(reg32_t *)(UART3_BASE_ADDR + 0x00)) -#define U3THR (*(reg32_t *)(UART3_BASE_ADDR + 0x00)) -#define U3DLL (*(reg32_t *)(UART3_BASE_ADDR + 0x00)) -#define U3DLM (*(reg32_t *)(UART3_BASE_ADDR + 0x04)) -#define U3IER (*(reg32_t *)(UART3_BASE_ADDR + 0x04)) -#define U3IIR (*(reg32_t *)(UART3_BASE_ADDR + 0x08)) -#define U3FCR (*(reg32_t *)(UART3_BASE_ADDR + 0x08)) -#define U3LCR (*(reg32_t *)(UART3_BASE_ADDR + 0x0C)) -#define U3LSR (*(reg32_t *)(UART3_BASE_ADDR + 0x14)) -#define U3SCR (*(reg32_t *)(UART3_BASE_ADDR + 0x1C)) -#define U3ACR (*(reg32_t *)(UART3_BASE_ADDR + 0x20)) -#define U3ICR (*(reg32_t *)(UART3_BASE_ADDR + 0x24)) -#define U3FDR (*(reg32_t *)(UART3_BASE_ADDR + 0x28)) -#define U3TER (*(reg32_t *)(UART3_BASE_ADDR + 0x30)) - -/* I2C Interface 0 */ -#define I2C0_BASE_ADDR 0xE001C000 -#define I20CONSET (*(reg32_t *)(I2C0_BASE_ADDR + 0x00)) -#define I20STAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x04)) -#define I20DAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x08)) -#define I20ADR (*(reg32_t *)(I2C0_BASE_ADDR + 0x0C)) -#define I20SCLH (*(reg32_t *)(I2C0_BASE_ADDR + 0x10)) -#define I20SCLL (*(reg32_t *)(I2C0_BASE_ADDR + 0x14)) -#define I20CONCLR (*(reg32_t *)(I2C0_BASE_ADDR + 0x18)) - -/* I2C Interface 1 */ -#define I2C1_BASE_ADDR 0xE005C000 -#define I21CONSET (*(reg32_t *)(I2C1_BASE_ADDR + 0x00)) -#define I21STAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x04)) -#define I21DAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x08)) -#define I21ADR (*(reg32_t *)(I2C1_BASE_ADDR + 0x0C)) -#define I21SCLH (*(reg32_t *)(I2C1_BASE_ADDR + 0x10)) -#define I21SCLL (*(reg32_t *)(I2C1_BASE_ADDR + 0x14)) -#define I21CONCLR (*(reg32_t *)(I2C1_BASE_ADDR + 0x18)) - -/* I2C Interface 2 */ -#define I2C2_BASE_ADDR 0xE0080000 -#define I22CONSET (*(reg32_t *)(I2C2_BASE_ADDR + 0x00)) -#define I22STAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x04)) -#define I22DAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x08)) -#define I22ADR (*(reg32_t *)(I2C2_BASE_ADDR + 0x0C)) -#define I22SCLH (*(reg32_t *)(I2C2_BASE_ADDR + 0x10)) -#define I22SCLL (*(reg32_t *)(I2C2_BASE_ADDR + 0x14)) -#define I22CONCLR (*(reg32_t *)(I2C2_BASE_ADDR + 0x18)) - -/* SPI0 (Serial Peripheral Interface 0) */ -#define SPI0_BASE_ADDR 0xE0020000 -#define S0SPCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x00)) -#define S0SPSR (*(reg32_t *)(SPI0_BASE_ADDR + 0x04)) -#define S0SPDR (*(reg32_t *)(SPI0_BASE_ADDR + 0x08)) -#define S0SPCCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x0C)) -#define S0SPINT (*(reg32_t *)(SPI0_BASE_ADDR + 0x1C)) - -/* SSP0 Controller */ -#define SSP0_BASE_ADDR 0xE0068000 -#define SSP0CR0 (*(reg32_t *)(SSP0_BASE_ADDR + 0x00)) -#define SSP0CR1 (*(reg32_t *)(SSP0_BASE_ADDR + 0x04)) -#define SSP0DR (*(reg32_t *)(SSP0_BASE_ADDR + 0x08)) -#define SSP0SR (*(reg32_t *)(SSP0_BASE_ADDR + 0x0C)) -#define SSP0CPSR (*(reg32_t *)(SSP0_BASE_ADDR + 0x10)) -#define SSP0IMSC (*(reg32_t *)(SSP0_BASE_ADDR + 0x14)) -#define SSP0RIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x18)) -#define SSP0MIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x1C)) -#define SSP0ICR (*(reg32_t *)(SSP0_BASE_ADDR + 0x20)) -#define SSP0DMACR (*(reg32_t *)(SSP0_BASE_ADDR + 0x24)) - -/* SSP1 Controller */ -#define SSP1_BASE_ADDR 0xE0030000 -#define SSP1CR0 (*(reg32_t *)(SSP1_BASE_ADDR + 0x00)) -#define SSP1CR1 (*(reg32_t *)(SSP1_BASE_ADDR + 0x04)) -#define SSP1DR (*(reg32_t *)(SSP1_BASE_ADDR + 0x08)) -#define SSP1SR (*(reg32_t *)(SSP1_BASE_ADDR + 0x0C)) -#define SSP1CPSR (*(reg32_t *)(SSP1_BASE_ADDR + 0x10)) -#define SSP1IMSC (*(reg32_t *)(SSP1_BASE_ADDR + 0x14)) -#define SSP1RIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x18)) -#define SSP1MIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x1C)) -#define SSP1ICR (*(reg32_t *)(SSP1_BASE_ADDR + 0x20)) -#define SSP1DMACR (*(reg32_t *)(SSP1_BASE_ADDR + 0x24)) - - -/* Real Time Clock */ -#define RTC_BASE_ADDR 0xE0024000 -#define RTC_ILR (*(reg32_t *)(RTC_BASE_ADDR + 0x00)) -#define RTC_CTC (*(reg32_t *)(RTC_BASE_ADDR + 0x04)) -#define RTC_CCR (*(reg32_t *)(RTC_BASE_ADDR + 0x08)) -#define RTC_CIIR (*(reg32_t *)(RTC_BASE_ADDR + 0x0C)) -#define RTC_AMR (*(reg32_t *)(RTC_BASE_ADDR + 0x10)) -#define RTC_CTIME0 (*(reg32_t *)(RTC_BASE_ADDR + 0x14)) -#define RTC_CTIME1 (*(reg32_t *)(RTC_BASE_ADDR + 0x18)) -#define RTC_CTIME2 (*(reg32_t *)(RTC_BASE_ADDR + 0x1C)) -#define RTC_SEC (*(reg32_t *)(RTC_BASE_ADDR + 0x20)) -#define RTC_MIN (*(reg32_t *)(RTC_BASE_ADDR + 0x24)) -#define RTC_HOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x28)) -#define RTC_DOM (*(reg32_t *)(RTC_BASE_ADDR + 0x2C)) -#define RTC_DOW (*(reg32_t *)(RTC_BASE_ADDR + 0x30)) -#define RTC_DOY (*(reg32_t *)(RTC_BASE_ADDR + 0x34)) -#define RTC_MONTH (*(reg32_t *)(RTC_BASE_ADDR + 0x38)) -#define RTC_YEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x3C)) -#define RTC_CISS (*(reg32_t *)(RTC_BASE_ADDR + 0x40)) -#define RTC_ALSEC (*(reg32_t *)(RTC_BASE_ADDR + 0x60)) -#define RTC_ALMIN (*(reg32_t *)(RTC_BASE_ADDR + 0x64)) -#define RTC_ALHOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x68)) -#define RTC_ALDOM (*(reg32_t *)(RTC_BASE_ADDR + 0x6C)) -#define RTC_ALDOW (*(reg32_t *)(RTC_BASE_ADDR + 0x70)) -#define RTC_ALDOY (*(reg32_t *)(RTC_BASE_ADDR + 0x74)) -#define RTC_ALMON (*(reg32_t *)(RTC_BASE_ADDR + 0x78)) -#define RTC_ALYEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x7C)) -#define RTC_PREINT (*(reg32_t *)(RTC_BASE_ADDR + 0x80)) -#define RTC_PREFRAC (*(reg32_t *)(RTC_BASE_ADDR + 0x84)) - - -/* A/D Converter 0 (AD0) */ -#define AD0_BASE_ADDR 0xE0034000 -#define AD0CR (*(reg32_t *)(AD0_BASE_ADDR + 0x00)) -#define AD0GDR (*(reg32_t *)(AD0_BASE_ADDR + 0x04)) -#define AD0INTEN (*(reg32_t *)(AD0_BASE_ADDR + 0x0C)) -#define AD0DR0 (*(reg32_t *)(AD0_BASE_ADDR + 0x10)) -#define AD0DR1 (*(reg32_t *)(AD0_BASE_ADDR + 0x14)) -#define AD0DR2 (*(reg32_t *)(AD0_BASE_ADDR + 0x18)) -#define AD0DR3 (*(reg32_t *)(AD0_BASE_ADDR + 0x1C)) -#define AD0DR4 (*(reg32_t *)(AD0_BASE_ADDR + 0x20)) -#define AD0DR5 (*(reg32_t *)(AD0_BASE_ADDR + 0x24)) -#define AD0DR6 (*(reg32_t *)(AD0_BASE_ADDR + 0x28)) -#define AD0DR7 (*(reg32_t *)(AD0_BASE_ADDR + 0x2C)) -#define AD0STAT (*(reg32_t *)(AD0_BASE_ADDR + 0x30)) - - -/* D/A Converter */ -#define DAC_BASE_ADDR 0xE006C000 -#define DACR (*(reg32_t *)(DAC_BASE_ADDR + 0x00)) - - -/* Watchdog */ -#define WDG_BASE_ADDR 0xE0000000 -#define WDMOD (*(reg32_t *)(WDG_BASE_ADDR + 0x00)) -#define WDTC (*(reg32_t *)(WDG_BASE_ADDR + 0x04)) -#define WDFEED (*(reg32_t *)(WDG_BASE_ADDR + 0x08)) -#define WDTV (*(reg32_t *)(WDG_BASE_ADDR + 0x0C)) -#define WDCLKSEL (*(reg32_t *)(WDG_BASE_ADDR + 0x10)) - -/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ -#define CAN_ACCEPT_BASE_ADDR 0xE003C000 -#define CAN_AFMR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x00)) -#define CAN_SFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x04)) -#define CAN_SFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x08)) -#define CAN_EFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) -#define CAN_EFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x10)) -#define CAN_EOT (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x14)) -#define CAN_LUT_ERR_ADR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x18)) -#define CAN_LUT_ERR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) - -#define CAN_CENTRAL_BASE_ADDR 0xE0040000 -#define CAN_TX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x00)) -#define CAN_RX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x04)) -#define CAN_MSR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x08)) - -#define CAN1_BASE_ADDR 0xE0044000 -#define CAN1MOD (*(reg32_t *)(CAN1_BASE_ADDR + 0x00)) -#define CAN1CMR (*(reg32_t *)(CAN1_BASE_ADDR + 0x04)) -#define CAN1GSR (*(reg32_t *)(CAN1_BASE_ADDR + 0x08)) -#define CAN1ICR (*(reg32_t *)(CAN1_BASE_ADDR + 0x0C)) -#define CAN1IER (*(reg32_t *)(CAN1_BASE_ADDR + 0x10)) -#define CAN1BTR (*(reg32_t *)(CAN1_BASE_ADDR + 0x14)) -#define CAN1EWL (*(reg32_t *)(CAN1_BASE_ADDR + 0x18)) -#define CAN1SR (*(reg32_t *)(CAN1_BASE_ADDR + 0x1C)) -#define CAN1RFS (*(reg32_t *)(CAN1_BASE_ADDR + 0x20)) -#define CAN1RID (*(reg32_t *)(CAN1_BASE_ADDR + 0x24)) -#define CAN1RDA (*(reg32_t *)(CAN1_BASE_ADDR + 0x28)) -#define CAN1RDB (*(reg32_t *)(CAN1_BASE_ADDR + 0x2C)) - -#define CAN1TFI1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x30)) -#define CAN1TID1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x34)) -#define CAN1TDA1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x38)) -#define CAN1TDB1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x3C)) -#define CAN1TFI2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x40)) -#define CAN1TID2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x44)) -#define CAN1TDA2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x48)) -#define CAN1TDB2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x4C)) -#define CAN1TFI3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x50)) -#define CAN1TID3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x54)) -#define CAN1TDA3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x58)) -#define CAN1TDB3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x5C)) - -#define CAN2_BASE_ADDR 0xE0048000 -#define CAN2MOD (*(reg32_t *)(CAN2_BASE_ADDR + 0x00)) -#define CAN2CMR (*(reg32_t *)(CAN2_BASE_ADDR + 0x04)) -#define CAN2GSR (*(reg32_t *)(CAN2_BASE_ADDR + 0x08)) -#define CAN2ICR (*(reg32_t *)(CAN2_BASE_ADDR + 0x0C)) -#define CAN2IER (*(reg32_t *)(CAN2_BASE_ADDR + 0x10)) -#define CAN2BTR (*(reg32_t *)(CAN2_BASE_ADDR + 0x14)) -#define CAN2EWL (*(reg32_t *)(CAN2_BASE_ADDR + 0x18)) -#define CAN2SR (*(reg32_t *)(CAN2_BASE_ADDR + 0x1C)) -#define CAN2RFS (*(reg32_t *)(CAN2_BASE_ADDR + 0x20)) -#define CAN2RID (*(reg32_t *)(CAN2_BASE_ADDR + 0x24)) -#define CAN2RDA (*(reg32_t *)(CAN2_BASE_ADDR + 0x28)) -#define CAN2RDB (*(reg32_t *)(CAN2_BASE_ADDR + 0x2C)) - -#define CAN2TFI1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x30)) -#define CAN2TID1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x34)) -#define CAN2TDA1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x38)) -#define CAN2TDB1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x3C)) -#define CAN2TFI2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x40)) -#define CAN2TID2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x44)) -#define CAN2TDA2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x48)) -#define CAN2TDB2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x4C)) -#define CAN2TFI3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x50)) -#define CAN2TID3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x54)) -#define CAN2TDA3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x58)) -#define CAN2TDB3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x5C)) - - -/* MultiMedia Card Interface(MCI) Controller */ -#define MCI_BASE_ADDR 0xE008C000 -#define MCI_POWER (*(reg32_t *)(MCI_BASE_ADDR + 0x00)) -#define MCI_CLOCK (*(reg32_t *)(MCI_BASE_ADDR + 0x04)) -#define MCI_ARGUMENT (*(reg32_t *)(MCI_BASE_ADDR + 0x08)) -#define MCI_COMMAND (*(reg32_t *)(MCI_BASE_ADDR + 0x0C)) -#define MCI_RESP_CMD (*(reg32_t *)(MCI_BASE_ADDR + 0x10)) -#define MCI_RESP0 (*(reg32_t *)(MCI_BASE_ADDR + 0x14)) -#define MCI_RESP1 (*(reg32_t *)(MCI_BASE_ADDR + 0x18)) -#define MCI_RESP2 (*(reg32_t *)(MCI_BASE_ADDR + 0x1C)) -#define MCI_RESP3 (*(reg32_t *)(MCI_BASE_ADDR + 0x20)) -#define MCI_DATA_TMR (*(reg32_t *)(MCI_BASE_ADDR + 0x24)) -#define MCI_DATA_LEN (*(reg32_t *)(MCI_BASE_ADDR + 0x28)) -#define MCI_DATA_CTRL (*(reg32_t *)(MCI_BASE_ADDR + 0x2C)) -#define MCI_DATA_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x30)) -#define MCI_STATUS (*(reg32_t *)(MCI_BASE_ADDR + 0x34)) -#define MCI_CLEAR (*(reg32_t *)(MCI_BASE_ADDR + 0x38)) -#define MCI_MASK0 (*(reg32_t *)(MCI_BASE_ADDR + 0x3C)) -#define MCI_MASK1 (*(reg32_t *)(MCI_BASE_ADDR + 0x40)) -#define MCI_FIFO_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x48)) -#define MCI_FIFO (*(reg32_t *)(MCI_BASE_ADDR + 0x80)) - - -/* I2S Interface Controller (I2S) */ -#define I2S_BASE_ADDR 0xE0088000 -#define I2S_DAO (*(reg32_t *)(I2S_BASE_ADDR + 0x00)) -#define I2S_DAI (*(reg32_t *)(I2S_BASE_ADDR + 0x04)) -#define I2S_TX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x08)) -#define I2S_RX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x0C)) -#define I2S_STATE (*(reg32_t *)(I2S_BASE_ADDR + 0x10)) -#define I2S_DMA1 (*(reg32_t *)(I2S_BASE_ADDR + 0x14)) -#define I2S_DMA2 (*(reg32_t *)(I2S_BASE_ADDR + 0x18)) -#define I2S_IRQ (*(reg32_t *)(I2S_BASE_ADDR + 0x1C)) -#define I2S_TXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x20)) -#define I2S_RXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x24)) - - -/* General-purpose DMA Controller */ -#define DMA_BASE_ADDR 0xFFE04000 -#define GPDMA_INT_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x000)) -#define GPDMA_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x004)) -#define GPDMA_INT_TCCLR (*(reg32_t *)(DMA_BASE_ADDR + 0x008)) -#define GPDMA_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x00C)) -#define GPDMA_INT_ERR_CLR (*(reg32_t *)(DMA_BASE_ADDR + 0x010)) -#define GPDMA_RAW_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x014)) -#define GPDMA_RAW_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x018)) -#define GPDMA_ENABLED_CHNS (*(reg32_t *)(DMA_BASE_ADDR + 0x01C)) -#define GPDMA_SOFT_BREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x020)) -#define GPDMA_SOFT_SREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x024)) -#define GPDMA_SOFT_LBREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x028)) -#define GPDMA_SOFT_LSREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x02C)) -#define GPDMA_CONFIG (*(reg32_t *)(DMA_BASE_ADDR + 0x030)) -#define GPDMA_SYNC (*(reg32_t *)(DMA_BASE_ADDR + 0x034)) - -/* DMA channel 0 registers */ -#define GPDMA_CH0_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x100)) -#define GPDMA_CH0_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x104)) -#define GPDMA_CH0_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x108)) -#define GPDMA_CH0_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x10C)) -#define GPDMA_CH0_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x110)) - -/* DMA channel 1 registers */ -#define GPDMA_CH1_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x120)) -#define GPDMA_CH1_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x124)) -#define GPDMA_CH1_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x128)) -#define GPDMA_CH1_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x12C)) -#define GPDMA_CH1_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x130)) - - -/* USB Controller */ -#define USB_INT_BASE_ADDR 0xE01FC1C0 -#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ - -#define USB_INT_STAT (*(reg32_t *)(USB_INT_BASE_ADDR + 0x00)) - -/* USB Device Interrupt Registers */ -#define DEV_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x00)) -#define DEV_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x04)) -#define DEV_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x08)) -#define DEV_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x0C)) -#define DEV_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x2C)) - -/* USB Device Endpoint Interrupt Registers */ -#define EP_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x30)) -#define EP_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x34)) -#define EP_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x38)) -#define EP_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x3C)) -#define EP_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x40)) - -/* USB Device Endpoint Realization Registers */ -#define REALIZE_EP (*(reg32_t *)(USB_BASE_ADDR + 0x44)) -#define EP_INDEX (*(reg32_t *)(USB_BASE_ADDR + 0x48)) -#define MAXPACKET_SIZE (*(reg32_t *)(USB_BASE_ADDR + 0x4C)) - -/* USB Device Command Reagisters */ -#define CMD_CODE (*(reg32_t *)(USB_BASE_ADDR + 0x10)) -#define CMD_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x14)) - -/* USB Device Data Transfer Registers */ -#define RX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x18)) -#define TX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x1C)) -#define RX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x20)) -#define TX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x24)) -#define USB_CTRL (*(reg32_t *)(USB_BASE_ADDR + 0x28)) - -/* USB Device DMA Registers */ -#define DMA_REQ_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x50)) -#define DMA_REQ_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x54)) -#define DMA_REQ_SET (*(reg32_t *)(USB_BASE_ADDR + 0x58)) -#define UDCA_HEAD (*(reg32_t *)(USB_BASE_ADDR + 0x80)) -#define EP_DMA_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x84)) -#define EP_DMA_EN (*(reg32_t *)(USB_BASE_ADDR + 0x88)) -#define EP_DMA_DIS (*(reg32_t *)(USB_BASE_ADDR + 0x8C)) -#define DMA_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x90)) -#define DMA_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x94)) -#define EOT_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xA0)) -#define EOT_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xA4)) -#define EOT_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xA8)) -#define NDD_REQ_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xAC)) -#define NDD_REQ_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xB0)) -#define NDD_REQ_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xB4)) -#define SYS_ERR_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xB8)) -#define SYS_ERR_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xBC)) -#define SYS_ERR_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xC0)) - -/* USB Host and OTG registers are for LPC24xx only */ -/* USB Host Controller */ -#define USBHC_BASE_ADDR 0xFFE0C000 -#define HC_REVISION (*(reg32_t *)(USBHC_BASE_ADDR + 0x00)) -#define HC_CONTROL (*(reg32_t *)(USBHC_BASE_ADDR + 0x04)) -#define HC_CMD_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x08)) -#define HC_INT_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x0C)) -#define HC_INT_EN (*(reg32_t *)(USBHC_BASE_ADDR + 0x10)) -#define HC_INT_DIS (*(reg32_t *)(USBHC_BASE_ADDR + 0x14)) -#define HC_HCCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x18)) -#define HC_PERIOD_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x1C)) -#define HC_CTRL_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x20)) -#define HC_CTRL_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x24)) -#define HC_BULK_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x28)) -#define HC_BULK_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x2C)) -#define HC_DONE_HEAD (*(reg32_t *)(USBHC_BASE_ADDR + 0x30)) -#define HC_FM_INTERVAL (*(reg32_t *)(USBHC_BASE_ADDR + 0x34)) -#define HC_FM_REMAINING (*(reg32_t *)(USBHC_BASE_ADDR + 0x38)) -#define HC_FM_NUMBER (*(reg32_t *)(USBHC_BASE_ADDR + 0x3C)) -#define HC_PERIOD_START (*(reg32_t *)(USBHC_BASE_ADDR + 0x40)) -#define HC_LS_THRHLD (*(reg32_t *)(USBHC_BASE_ADDR + 0x44)) -#define HC_RH_DESCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x48)) -#define HC_RH_DESCB (*(reg32_t *)(USBHC_BASE_ADDR + 0x4C)) -#define HC_RH_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x50)) -#define HC_RH_PORT_STAT1 (*(reg32_t *)(USBHC_BASE_ADDR + 0x54)) -#define HC_RH_PORT_STAT2 (*(reg32_t *)(USBHC_BASE_ADDR + 0x58)) - -/* USB OTG Controller */ -#define USBOTG_BASE_ADDR 0xFFE0C100 -#define OTG_INT_STAT (*(reg32_t *)(USBOTG_BASE_ADDR + 0x00)) -#define OTG_INT_EN (*(reg32_t *)(USBOTG_BASE_ADDR + 0x04)) -#define OTG_INT_SET (*(reg32_t *)(USBOTG_BASE_ADDR + 0x08)) -#define OTG_INT_CLR (*(reg32_t *)(USBOTG_BASE_ADDR + 0x0C)) -/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ -#define OTG_STAT_CTRL (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10)) -#define OTG_TIMER (*(reg32_t *)(USBOTG_BASE_ADDR + 0x14)) - -#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 -#define OTG_I2C_RX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00)) -#define OTG_I2C_TX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00)) -#define OTG_I2C_STS (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x04)) -#define OTG_I2C_CTL (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x08)) -#define OTG_I2C_CLKHI (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x0C)) -#define OTG_I2C_CLKLO (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x10)) - -/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are -OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ -#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 -#define OTG_CLK_CTRL (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04)) -#define OTG_CLK_STAT (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08)) - -/* Note: below three register name convention is for LPC23xx USB device only, match -with the spec. update in USB Device Section. */ -#define USBPortSel (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10)) -#define USBClkCtrl (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04)) -#define USBClkSt (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08)) - -/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ -#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ -#define MAC_MAC1 (*(reg32_t *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ -#define MAC_MAC2 (*(reg32_t *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ -#define MAC_IPGT (*(reg32_t *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ -#define MAC_IPGR (*(reg32_t *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ -#define MAC_CLRT (*(reg32_t *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ -#define MAC_MAXF (*(reg32_t *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ -#define MAC_SUPP (*(reg32_t *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ -#define MAC_TEST (*(reg32_t *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ -#define MAC_MCFG (*(reg32_t *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ -#define MAC_MCMD (*(reg32_t *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ -#define MAC_MADR (*(reg32_t *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ -#define MAC_MWTD (*(reg32_t *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ -#define MAC_MRDD (*(reg32_t *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ -#define MAC_MIND (*(reg32_t *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ - -#define MAC_SA0 (*(reg32_t *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ -#define MAC_SA1 (*(reg32_t *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ -#define MAC_SA2 (*(reg32_t *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ - -#define MAC_COMMAND (*(reg32_t *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ -#define MAC_STATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ -#define MAC_RXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ -#define MAC_RXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ -#define MAC_RXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ -#define MAC_RXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ -#define MAC_RXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ -#define MAC_TXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ -#define MAC_TXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ -#define MAC_TXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ -#define MAC_TXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ -#define MAC_TXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ - -#define MAC_TSV0 (*(reg32_t *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ -#define MAC_TSV1 (*(reg32_t *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ -#define MAC_RSV (*(reg32_t *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ - -#define MAC_FLOWCONTROLCNT (*(reg32_t *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ -#define MAC_FLOWCONTROLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ - -#define MAC_RXFILTERCTRL (*(reg32_t *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ -#define MAC_RXFILTERWOLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ -#define MAC_RXFILTERWOLCLR (*(reg32_t *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ - -#define MAC_HASHFILTERL (*(reg32_t *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ -#define MAC_HASHFILTERH (*(reg32_t *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ - -#define MAC_INTSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ -#define MAC_INTENABLE (*(reg32_t *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ -#define MAC_INTCLEAR (*(reg32_t *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ -#define MAC_INTSET (*(reg32_t *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ - -#define MAC_POWERDOWN (*(reg32_t *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ -#define MAC_MODULEID (*(reg32_t *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ - -#endif /* LPC23XX_H */ +/** + * \file + * + * + * \author Francesco Sacchi + * + * LPC23xx I/O registers. + */ + +#ifndef LPC23XX_H +#define LPC23XX_H + +#include + +/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(reg32_t *)(VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(reg32_t *)(VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(reg32_t *)(VIC_BASE_ADDR + 0x010)) +#define VICIntEnClr (*(reg32_t *)(VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(reg32_t *)(VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClr (*(reg32_t *)(VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(reg32_t *)(VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(reg32_t *)(VIC_BASE_ADDR + 0x024)) + +#define VICVectAddr0 (*(reg32_t *)(VIC_BASE_ADDR + 0x100)) +#define VICVectAddr1 (*(reg32_t *)(VIC_BASE_ADDR + 0x104)) +#define VICVectAddr2 (*(reg32_t *)(VIC_BASE_ADDR + 0x108)) +#define VICVectAddr3 (*(reg32_t *)(VIC_BASE_ADDR + 0x10C)) +#define VICVectAddr4 (*(reg32_t *)(VIC_BASE_ADDR + 0x110)) +#define VICVectAddr5 (*(reg32_t *)(VIC_BASE_ADDR + 0x114)) +#define VICVectAddr6 (*(reg32_t *)(VIC_BASE_ADDR + 0x118)) +#define VICVectAddr7 (*(reg32_t *)(VIC_BASE_ADDR + 0x11C)) +#define VICVectAddr8 (*(reg32_t *)(VIC_BASE_ADDR + 0x120)) +#define VICVectAddr9 (*(reg32_t *)(VIC_BASE_ADDR + 0x124)) +#define VICVectAddr10 (*(reg32_t *)(VIC_BASE_ADDR + 0x128)) +#define VICVectAddr11 (*(reg32_t *)(VIC_BASE_ADDR + 0x12C)) +#define VICVectAddr12 (*(reg32_t *)(VIC_BASE_ADDR + 0x130)) +#define VICVectAddr13 (*(reg32_t *)(VIC_BASE_ADDR + 0x134)) +#define VICVectAddr14 (*(reg32_t *)(VIC_BASE_ADDR + 0x138)) +#define VICVectAddr15 (*(reg32_t *)(VIC_BASE_ADDR + 0x13C)) +#define VICVectAddr16 (*(reg32_t *)(VIC_BASE_ADDR + 0x140)) +#define VICVectAddr17 (*(reg32_t *)(VIC_BASE_ADDR + 0x144)) +#define VICVectAddr18 (*(reg32_t *)(VIC_BASE_ADDR + 0x148)) +#define VICVectAddr19 (*(reg32_t *)(VIC_BASE_ADDR + 0x14C)) +#define VICVectAddr20 (*(reg32_t *)(VIC_BASE_ADDR + 0x150)) +#define VICVectAddr21 (*(reg32_t *)(VIC_BASE_ADDR + 0x154)) +#define VICVectAddr22 (*(reg32_t *)(VIC_BASE_ADDR + 0x158)) +#define VICVectAddr23 (*(reg32_t *)(VIC_BASE_ADDR + 0x15C)) +#define VICVectAddr24 (*(reg32_t *)(VIC_BASE_ADDR + 0x160)) +#define VICVectAddr25 (*(reg32_t *)(VIC_BASE_ADDR + 0x164)) +#define VICVectAddr26 (*(reg32_t *)(VIC_BASE_ADDR + 0x168)) +#define VICVectAddr27 (*(reg32_t *)(VIC_BASE_ADDR + 0x16C)) +#define VICVectAddr28 (*(reg32_t *)(VIC_BASE_ADDR + 0x170)) +#define VICVectAddr29 (*(reg32_t *)(VIC_BASE_ADDR + 0x174)) +#define VICVectAddr30 (*(reg32_t *)(VIC_BASE_ADDR + 0x178)) +#define VICVectAddr31 (*(reg32_t *)(VIC_BASE_ADDR + 0x17C)) + +/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx, +these registers are known as "VICVectPriority(x)". */ +#define VICVectCntl0 (*(reg32_t *)(VIC_BASE_ADDR + 0x200)) +#define VICVectCntl1 (*(reg32_t *)(VIC_BASE_ADDR + 0x204)) +#define VICVectCntl2 (*(reg32_t *)(VIC_BASE_ADDR + 0x208)) +#define VICVectCntl3 (*(reg32_t *)(VIC_BASE_ADDR + 0x20C)) +#define VICVectCntl4 (*(reg32_t *)(VIC_BASE_ADDR + 0x210)) +#define VICVectCntl5 (*(reg32_t *)(VIC_BASE_ADDR + 0x214)) +#define VICVectCntl6 (*(reg32_t *)(VIC_BASE_ADDR + 0x218)) +#define VICVectCntl7 (*(reg32_t *)(VIC_BASE_ADDR + 0x21C)) +#define VICVectCntl8 (*(reg32_t *)(VIC_BASE_ADDR + 0x220)) +#define VICVectCntl9 (*(reg32_t *)(VIC_BASE_ADDR + 0x224)) +#define VICVectCntl10 (*(reg32_t *)(VIC_BASE_ADDR + 0x228)) +#define VICVectCntl11 (*(reg32_t *)(VIC_BASE_ADDR + 0x22C)) +#define VICVectCntl12 (*(reg32_t *)(VIC_BASE_ADDR + 0x230)) +#define VICVectCntl13 (*(reg32_t *)(VIC_BASE_ADDR + 0x234)) +#define VICVectCntl14 (*(reg32_t *)(VIC_BASE_ADDR + 0x238)) +#define VICVectCntl15 (*(reg32_t *)(VIC_BASE_ADDR + 0x23C)) +#define VICVectCntl16 (*(reg32_t *)(VIC_BASE_ADDR + 0x240)) +#define VICVectCntl17 (*(reg32_t *)(VIC_BASE_ADDR + 0x244)) +#define VICVectCntl18 (*(reg32_t *)(VIC_BASE_ADDR + 0x248)) +#define VICVectCntl19 (*(reg32_t *)(VIC_BASE_ADDR + 0x24C)) +#define VICVectCntl20 (*(reg32_t *)(VIC_BASE_ADDR + 0x250)) +#define VICVectCntl21 (*(reg32_t *)(VIC_BASE_ADDR + 0x254)) +#define VICVectCntl22 (*(reg32_t *)(VIC_BASE_ADDR + 0x258)) +#define VICVectCntl23 (*(reg32_t *)(VIC_BASE_ADDR + 0x25C)) +#define VICVectCntl24 (*(reg32_t *)(VIC_BASE_ADDR + 0x260)) +#define VICVectCntl25 (*(reg32_t *)(VIC_BASE_ADDR + 0x264)) +#define VICVectCntl26 (*(reg32_t *)(VIC_BASE_ADDR + 0x268)) +#define VICVectCntl27 (*(reg32_t *)(VIC_BASE_ADDR + 0x26C)) +#define VICVectCntl28 (*(reg32_t *)(VIC_BASE_ADDR + 0x270)) +#define VICVectCntl29 (*(reg32_t *)(VIC_BASE_ADDR + 0x274)) +#define VICVectCntl30 (*(reg32_t *)(VIC_BASE_ADDR + 0x278)) +#define VICVectCntl31 (*(reg32_t *)(VIC_BASE_ADDR + 0x27C)) + +#define VICVectAddr (*(reg32_t *)(VIC_BASE_ADDR + 0xF00)) + + +/* Pin Connect Block */ +#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x00)) +#define PINSEL1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x04)) +#define PINSEL2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x08)) +#define PINSEL3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x0C)) +#define PINSEL4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x10)) +#define PINSEL5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x14)) +#define PINSEL6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x18)) +#define PINSEL7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x1C)) +#define PINSEL8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x20)) +#define PINSEL9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x24)) +#define PINSEL10 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x28)) + +#define PINMODE0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x40)) +#define PINMODE1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x44)) +#define PINMODE2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x48)) +#define PINMODE3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x4C)) +#define PINMODE4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x50)) +#define PINMODE5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x54)) +#define PINMODE6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x58)) +#define PINMODE7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x5C)) +#define PINMODE8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x60)) +#define PINMODE9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x64)) + +/* General Purpose Input/Output (GPIO) */ +#define GPIO_BASE_ADDR 0xE0028000 +#define IOPIN0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x00)) +#define IOSET0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x04)) +#define IODIR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x08)) +#define IOCLR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x0C)) +#define IOPIN1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x10)) +#define IOSET1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x14)) +#define IODIR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x18)) +#define IOCLR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x1C)) + +/* GPIO Interrupt Registers */ +#define IO0_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x94)) +#define IO0_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x84)) +#define IO0_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x88)) +#define IO0_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0x8C)) + +#define IO2_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xB4)) +#define IO2_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xA4)) +#define IO2_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xA8)) +#define IO2_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0xAC)) + +#define IO_INT_STAT (*(reg32_t *)(GPIO_BASE_ADDR + 0x80)) + +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(reg32_t *)(PARTCFG_BASE_ADDR + 0x00)) + +/* Fast I/O setup */ +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x00)) +#define FIO0MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x10)) +#define FIO0PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x14)) +#define FIO0SET (*(reg32_t *)(FIO_BASE_ADDR + 0x18)) +#define FIO0CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x1C)) + +#define FIO1DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x20)) +#define FIO1MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x30)) +#define FIO1PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x34)) +#define FIO1SET (*(reg32_t *)(FIO_BASE_ADDR + 0x38)) +#define FIO1CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x3C)) + +#define FIO2DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x40)) +#define FIO2MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x50)) +#define FIO2PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x54)) +#define FIO2SET (*(reg32_t *)(FIO_BASE_ADDR + 0x58)) +#define FIO2CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x5C)) + +#define FIO3DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x60)) +#define FIO3MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x70)) +#define FIO3PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x74)) +#define FIO3SET (*(reg32_t *)(FIO_BASE_ADDR + 0x78)) +#define FIO3CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x7C)) + +#define FIO4DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x80)) +#define FIO4MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x90)) +#define FIO4PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x94)) +#define FIO4SET (*(reg32_t *)(FIO_BASE_ADDR + 0x98)) +#define FIO4CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x9C)) + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x81)) + +#define FIO0DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x83)) + +#define FIO0DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x91)) + +#define FIO0MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x93)) + +#define FIO0MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x25)) +#define FIO2PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x95)) + +#define FIO0PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x97)) + +#define FIO0PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x99)) + +#define FIO0SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9B)) + +#define FIO0SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x9D)) + +#define FIO0CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9E)) + +#define FIO0CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9F)) + +#define FIO0CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x9E)) + + +/* System Control Block(SCB) modules include Memory Accelerator Module, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Reset, and Code Security/Debugging */ +#define SCB_BASE_ADDR 0xE01FC000 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*(reg32_t *)(SCB_BASE_ADDR + 0x000)) +#define MAMTIM (*(reg32_t *)(SCB_BASE_ADDR + 0x004)) +#define MEMMAP (*(reg32_t *)(SCB_BASE_ADDR + 0x040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*(reg32_t *)(SCB_BASE_ADDR + 0x080)) +#define PLLCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x084)) +#define PLLSTAT (*(reg32_t *)(SCB_BASE_ADDR + 0x088)) +#define PLLFEED (*(reg32_t *)(SCB_BASE_ADDR + 0x08C)) + +/* Power Control */ +#define PCON (*(reg32_t *)(SCB_BASE_ADDR + 0x0C0)) +#define PCONP (*(reg32_t *)(SCB_BASE_ADDR + 0x0C4)) + +/* Clock Divider */ +// #define APBDIV (*(reg32_t *)(SCB_BASE_ADDR + 0x100)) +#define CCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x104)) +#define USBCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x108)) +#define CLKSRCSEL (*(reg32_t *)(SCB_BASE_ADDR + 0x10C)) +#define PCLKSEL0 (*(reg32_t *)(SCB_BASE_ADDR + 0x1A8)) +#define PCLKSEL1 (*(reg32_t *)(SCB_BASE_ADDR + 0x1AC)) + +/* External Interrupts */ +#define EXTINT (*(reg32_t *)(SCB_BASE_ADDR + 0x140)) +#define INTWAKE (*(reg32_t *)(SCB_BASE_ADDR + 0x144)) +#define EXTMODE (*(reg32_t *)(SCB_BASE_ADDR + 0x148)) +#define EXTPOLAR (*(reg32_t *)(SCB_BASE_ADDR + 0x14C)) + +/* Reset, reset source identification */ +#define RSIR (*(reg32_t *)(SCB_BASE_ADDR + 0x180)) + +/* RSID, code security protection */ +#define CSPR (*(reg32_t *)(SCB_BASE_ADDR + 0x184)) + +/* AHB configuration */ +#define AHBCFG1 (*(reg32_t *)(SCB_BASE_ADDR + 0x188)) +#define AHBCFG2 (*(reg32_t *)(SCB_BASE_ADDR + 0x18C)) + +/* System Controls and Status */ +#define SCS (*(reg32_t *)(SCB_BASE_ADDR + 0x1A0)) + +/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers +are for LPC24xx only. */ +#define STATIC_MEM0_BASE 0x80000000 +#define STATIC_MEM1_BASE 0x81000000 +#define STATIC_MEM2_BASE 0x82000000 +#define STATIC_MEM3_BASE 0x83000000 + +#define DYNAMIC_MEM0_BASE 0xA0000000 +#define DYNAMIC_MEM1_BASE 0xB0000000 +#define DYNAMIC_MEM2_BASE 0xC0000000 +#define DYNAMIC_MEM3_BASE 0xD0000000 + +/* External Memory Controller (EMC) */ +#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x000)) +#define EMC_STAT (*(reg32_t *)(EMC_BASE_ADDR + 0x004)) +#define EMC_CONFIG (*(reg32_t *)(EMC_BASE_ADDR + 0x008)) + +/* Dynamic RAM access registers */ +#define EMC_DYN_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x020)) +#define EMC_DYN_RFSH (*(reg32_t *)(EMC_BASE_ADDR + 0x024)) +#define EMC_DYN_RD_CFG (*(reg32_t *)(EMC_BASE_ADDR + 0x028)) +#define EMC_DYN_RP (*(reg32_t *)(EMC_BASE_ADDR + 0x030)) +#define EMC_DYN_RAS (*(reg32_t *)(EMC_BASE_ADDR + 0x034)) +#define EMC_DYN_SREX (*(reg32_t *)(EMC_BASE_ADDR + 0x038)) +#define EMC_DYN_APR (*(reg32_t *)(EMC_BASE_ADDR + 0x03C)) +#define EMC_DYN_DAL (*(reg32_t *)(EMC_BASE_ADDR + 0x040)) +#define EMC_DYN_WR (*(reg32_t *)(EMC_BASE_ADDR + 0x044)) +#define EMC_DYN_RC (*(reg32_t *)(EMC_BASE_ADDR + 0x048)) +#define EMC_DYN_RFC (*(reg32_t *)(EMC_BASE_ADDR + 0x04C)) +#define EMC_DYN_XSR (*(reg32_t *)(EMC_BASE_ADDR + 0x050)) +#define EMC_DYN_RRD (*(reg32_t *)(EMC_BASE_ADDR + 0x054)) +#define EMC_DYN_MRD (*(reg32_t *)(EMC_BASE_ADDR + 0x058)) + +#define EMC_DYN_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x100)) +#define EMC_DYN_RASCAS0 (*(reg32_t *)(EMC_BASE_ADDR + 0x104)) +#define EMC_DYN_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x140)) +#define EMC_DYN_RASCAS1 (*(reg32_t *)(EMC_BASE_ADDR + 0x144)) +#define EMC_DYN_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x160)) +#define EMC_DYN_RASCAS2 (*(reg32_t *)(EMC_BASE_ADDR + 0x164)) +#define EMC_DYN_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x180)) +#define EMC_DYN_RASCAS3 (*(reg32_t *)(EMC_BASE_ADDR + 0x184)) + +/* static RAM access registers */ +#define EMC_STA_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x200)) +#define EMC_STA_WAITWEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x204)) +#define EMC_STA_WAITOEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x208)) +#define EMC_STA_WAITRD0 (*(reg32_t *)(EMC_BASE_ADDR + 0x20C)) +#define EMC_STA_WAITPAGE0 (*(reg32_t *)(EMC_BASE_ADDR + 0x210)) +#define EMC_STA_WAITWR0 (*(reg32_t *)(EMC_BASE_ADDR + 0x214)) +#define EMC_STA_WAITTURN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x218)) + +#define EMC_STA_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x220)) +#define EMC_STA_WAITWEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x224)) +#define EMC_STA_WAITOEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x228)) +#define EMC_STA_WAITRD1 (*(reg32_t *)(EMC_BASE_ADDR + 0x22C)) +#define EMC_STA_WAITPAGE1 (*(reg32_t *)(EMC_BASE_ADDR + 0x230)) +#define EMC_STA_WAITWR1 (*(reg32_t *)(EMC_BASE_ADDR + 0x234)) +#define EMC_STA_WAITTURN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x238)) + +#define EMC_STA_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x240)) +#define EMC_STA_WAITWEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x244)) +#define EMC_STA_WAITOEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x248)) +#define EMC_STA_WAITRD2 (*(reg32_t *)(EMC_BASE_ADDR + 0x24C)) +#define EMC_STA_WAITPAGE2 (*(reg32_t *)(EMC_BASE_ADDR + 0x250)) +#define EMC_STA_WAITWR2 (*(reg32_t *)(EMC_BASE_ADDR + 0x254)) +#define EMC_STA_WAITTURN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x258)) + +#define EMC_STA_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x260)) +#define EMC_STA_WAITWEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x264)) +#define EMC_STA_WAITOEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x268)) +#define EMC_STA_WAITRD3 (*(reg32_t *)(EMC_BASE_ADDR + 0x26C)) +#define EMC_STA_WAITPAGE3 (*(reg32_t *)(EMC_BASE_ADDR + 0x270)) +#define EMC_STA_WAITWR3 (*(reg32_t *)(EMC_BASE_ADDR + 0x274)) +#define EMC_STA_WAITTURN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x278)) + +#define EMC_STA_EXT_WAIT (*(reg32_t *)(EMC_BASE_ADDR + 0x880)) + + +/* Timer 0 */ +#define TMR0_BASE_ADDR 0xE0004000 +#define T0IR (*(reg32_t *)(TMR0_BASE_ADDR + 0x00)) +#define T0TCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x04)) +#define T0TC (*(reg32_t *)(TMR0_BASE_ADDR + 0x08)) +#define T0PR (*(reg32_t *)(TMR0_BASE_ADDR + 0x0C)) +#define T0PC (*(reg32_t *)(TMR0_BASE_ADDR + 0x10)) +#define T0MCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x14)) +#define T0MR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x18)) +#define T0MR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x1C)) +#define T0MR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x20)) +#define T0MR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x24)) +#define T0CCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x28)) +#define T0CR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x2C)) +#define T0CR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x30)) +#define T0CR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x34)) +#define T0CR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x38)) +#define T0EMR (*(reg32_t *)(TMR0_BASE_ADDR + 0x3C)) +#define T0CTCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x70)) + +/* Timer 1 */ +#define TMR1_BASE_ADDR 0xE0008000 +#define T1IR (*(reg32_t *)(TMR1_BASE_ADDR + 0x00)) +#define T1TCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x04)) +#define T1TC (*(reg32_t *)(TMR1_BASE_ADDR + 0x08)) +#define T1PR (*(reg32_t *)(TMR1_BASE_ADDR + 0x0C)) +#define T1PC (*(reg32_t *)(TMR1_BASE_ADDR + 0x10)) +#define T1MCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x14)) +#define T1MR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x18)) +#define T1MR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x1C)) +#define T1MR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x20)) +#define T1MR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x24)) +#define T1CCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x28)) +#define T1CR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x2C)) +#define T1CR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x30)) +#define T1CR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x34)) +#define T1CR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x38)) +#define T1EMR (*(reg32_t *)(TMR1_BASE_ADDR + 0x3C)) +#define T1CTCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x70)) + +/* Timer 2 */ +#define TMR2_BASE_ADDR 0xE0070000 +#define T2IR (*(reg32_t *)(TMR2_BASE_ADDR + 0x00)) +#define T2TCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x04)) +#define T2TC (*(reg32_t *)(TMR2_BASE_ADDR + 0x08)) +#define T2PR (*(reg32_t *)(TMR2_BASE_ADDR + 0x0C)) +#define T2PC (*(reg32_t *)(TMR2_BASE_ADDR + 0x10)) +#define T2MCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x14)) +#define T2MR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x18)) +#define T2MR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x1C)) +#define T2MR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x20)) +#define T2MR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x24)) +#define T2CCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x28)) +#define T2CR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x2C)) +#define T2CR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x30)) +#define T2CR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x34)) +#define T2CR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x38)) +#define T2EMR (*(reg32_t *)(TMR2_BASE_ADDR + 0x3C)) +#define T2CTCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x70)) + +/* Timer 3 */ +#define TMR3_BASE_ADDR 0xE0074000 +#define T3IR (*(reg32_t *)(TMR3_BASE_ADDR + 0x00)) +#define T3TCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x04)) +#define T3TC (*(reg32_t *)(TMR3_BASE_ADDR + 0x08)) +#define T3PR (*(reg32_t *)(TMR3_BASE_ADDR + 0x0C)) +#define T3PC (*(reg32_t *)(TMR3_BASE_ADDR + 0x10)) +#define T3MCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x14)) +#define T3MR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x18)) +#define T3MR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x1C)) +#define T3MR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x20)) +#define T3MR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x24)) +#define T3CCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x28)) +#define T3CR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x2C)) +#define T3CR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x30)) +#define T3CR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x34)) +#define T3CR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x38)) +#define T3EMR (*(reg32_t *)(TMR3_BASE_ADDR + 0x3C)) +#define T3CTCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x70)) + + +/* Pulse Width Modulator (PWM) */ +#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0IR (*(reg32_t *)(PWM0_BASE_ADDR + 0x00)) +#define PWM0TCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x04)) +#define PWM0TC (*(reg32_t *)(PWM0_BASE_ADDR + 0x08)) +#define PWM0PR (*(reg32_t *)(PWM0_BASE_ADDR + 0x0C)) +#define PWM0PC (*(reg32_t *)(PWM0_BASE_ADDR + 0x10)) +#define PWM0MCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x14)) +#define PWM0MR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x18)) +#define PWM0MR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x1C)) +#define PWM0MR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x20)) +#define PWM0MR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x24)) +#define PWM0CCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x28)) +#define PWM0CR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x2C)) +#define PWM0CR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x30)) +#define PWM0CR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x34)) +#define PWM0CR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x38)) +#define PWM0EMR (*(reg32_t *)(PWM0_BASE_ADDR + 0x3C)) +#define PWM0MR4 (*(reg32_t *)(PWM0_BASE_ADDR + 0x40)) +#define PWM0MR5 (*(reg32_t *)(PWM0_BASE_ADDR + 0x44)) +#define PWM0MR6 (*(reg32_t *)(PWM0_BASE_ADDR + 0x48)) +#define PWM0PCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x4C)) +#define PWM0LER (*(reg32_t *)(PWM0_BASE_ADDR + 0x50)) +#define PWM0CTCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x70)) + +#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1IR (*(reg32_t *)(PWM1_BASE_ADDR + 0x00)) +#define PWM1TCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x04)) +#define PWM1TC (*(reg32_t *)(PWM1_BASE_ADDR + 0x08)) +#define PWM1PR (*(reg32_t *)(PWM1_BASE_ADDR + 0x0C)) +#define PWM1PC (*(reg32_t *)(PWM1_BASE_ADDR + 0x10)) +#define PWM1MCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x14)) +#define PWM1MR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x18)) +#define PWM1MR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x1C)) +#define PWM1MR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x20)) +#define PWM1MR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x24)) +#define PWM1CCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x28)) +#define PWM1CR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x2C)) +#define PWM1CR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x30)) +#define PWM1CR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x34)) +#define PWM1CR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x38)) +#define PWM1EMR (*(reg32_t *)(PWM1_BASE_ADDR + 0x3C)) +#define PWM1MR4 (*(reg32_t *)(PWM1_BASE_ADDR + 0x40)) +#define PWM1MR5 (*(reg32_t *)(PWM1_BASE_ADDR + 0x44)) +#define PWM1MR6 (*(reg32_t *)(PWM1_BASE_ADDR + 0x48)) +#define PWM1PCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x4C)) +#define PWM1LER (*(reg32_t *)(PWM1_BASE_ADDR + 0x50)) +#define PWM1CTCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x70)) + + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define UART0_BASE_ADDR 0xE000C000 +#define U0RBR (*(reg32_t *)(UART0_BASE_ADDR + 0x00)) +#define U0THR (*(reg32_t *)(UART0_BASE_ADDR + 0x00)) +#define U0DLL (*(reg32_t *)(UART0_BASE_ADDR + 0x00)) +#define U0DLM (*(reg32_t *)(UART0_BASE_ADDR + 0x04)) +#define U0IER (*(reg32_t *)(UART0_BASE_ADDR + 0x04)) +#define U0IIR (*(reg32_t *)(UART0_BASE_ADDR + 0x08)) +#define U0FCR (*(reg32_t *)(UART0_BASE_ADDR + 0x08)) +#define U0LCR (*(reg32_t *)(UART0_BASE_ADDR + 0x0C)) +#define U0LSR (*(reg32_t *)(UART0_BASE_ADDR + 0x14)) +#define U0SCR (*(reg32_t *)(UART0_BASE_ADDR + 0x1C)) +#define U0ACR (*(reg32_t *)(UART0_BASE_ADDR + 0x20)) +#define U0ICR (*(reg32_t *)(UART0_BASE_ADDR + 0x24)) +#define U0FDR (*(reg32_t *)(UART0_BASE_ADDR + 0x28)) +#define U0TER (*(reg32_t *)(UART0_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define UART1_BASE_ADDR 0xE0010000 +#define U1RBR (*(reg32_t *)(UART1_BASE_ADDR + 0x00)) +#define U1THR (*(reg32_t *)(UART1_BASE_ADDR + 0x00)) +#define U1DLL (*(reg32_t *)(UART1_BASE_ADDR + 0x00)) +#define U1DLM (*(reg32_t *)(UART1_BASE_ADDR + 0x04)) +#define U1IER (*(reg32_t *)(UART1_BASE_ADDR + 0x04)) +#define U1IIR (*(reg32_t *)(UART1_BASE_ADDR + 0x08)) +#define U1FCR (*(reg32_t *)(UART1_BASE_ADDR + 0x08)) +#define U1LCR (*(reg32_t *)(UART1_BASE_ADDR + 0x0C)) +#define U1MCR (*(reg32_t *)(UART1_BASE_ADDR + 0x10)) +#define U1LSR (*(reg32_t *)(UART1_BASE_ADDR + 0x14)) +#define U1MSR (*(reg32_t *)(UART1_BASE_ADDR + 0x18)) +#define U1SCR (*(reg32_t *)(UART1_BASE_ADDR + 0x1C)) +#define U1ACR (*(reg32_t *)(UART1_BASE_ADDR + 0x20)) +#define U1FDR (*(reg32_t *)(UART1_BASE_ADDR + 0x28)) +#define U1TER (*(reg32_t *)(UART1_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#define UART2_BASE_ADDR 0xE0078000 +#define U2RBR (*(reg32_t *)(UART2_BASE_ADDR + 0x00)) +#define U2THR (*(reg32_t *)(UART2_BASE_ADDR + 0x00)) +#define U2DLL (*(reg32_t *)(UART2_BASE_ADDR + 0x00)) +#define U2DLM (*(reg32_t *)(UART2_BASE_ADDR + 0x04)) +#define U2IER (*(reg32_t *)(UART2_BASE_ADDR + 0x04)) +#define U2IIR (*(reg32_t *)(UART2_BASE_ADDR + 0x08)) +#define U2FCR (*(reg32_t *)(UART2_BASE_ADDR + 0x08)) +#define U2LCR (*(reg32_t *)(UART2_BASE_ADDR + 0x0C)) +#define U2LSR (*(reg32_t *)(UART2_BASE_ADDR + 0x14)) +#define U2SCR (*(reg32_t *)(UART2_BASE_ADDR + 0x1C)) +#define U2ACR (*(reg32_t *)(UART2_BASE_ADDR + 0x20)) +#define U2ICR (*(reg32_t *)(UART2_BASE_ADDR + 0x24)) +#define U2FDR (*(reg32_t *)(UART2_BASE_ADDR + 0x28)) +#define U2TER (*(reg32_t *)(UART2_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#define UART3_BASE_ADDR 0xE007C000 +#define U3RBR (*(reg32_t *)(UART3_BASE_ADDR + 0x00)) +#define U3THR (*(reg32_t *)(UART3_BASE_ADDR + 0x00)) +#define U3DLL (*(reg32_t *)(UART3_BASE_ADDR + 0x00)) +#define U3DLM (*(reg32_t *)(UART3_BASE_ADDR + 0x04)) +#define U3IER (*(reg32_t *)(UART3_BASE_ADDR + 0x04)) +#define U3IIR (*(reg32_t *)(UART3_BASE_ADDR + 0x08)) +#define U3FCR (*(reg32_t *)(UART3_BASE_ADDR + 0x08)) +#define U3LCR (*(reg32_t *)(UART3_BASE_ADDR + 0x0C)) +#define U3LSR (*(reg32_t *)(UART3_BASE_ADDR + 0x14)) +#define U3SCR (*(reg32_t *)(UART3_BASE_ADDR + 0x1C)) +#define U3ACR (*(reg32_t *)(UART3_BASE_ADDR + 0x20)) +#define U3ICR (*(reg32_t *)(UART3_BASE_ADDR + 0x24)) +#define U3FDR (*(reg32_t *)(UART3_BASE_ADDR + 0x28)) +#define U3TER (*(reg32_t *)(UART3_BASE_ADDR + 0x30)) + +/* I2C Interface 0 */ +#define I2C0_BASE_ADDR 0xE001C000 +#define I20CONSET (*(reg32_t *)(I2C0_BASE_ADDR + 0x00)) +#define I20STAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x04)) +#define I20DAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x08)) +#define I20ADR (*(reg32_t *)(I2C0_BASE_ADDR + 0x0C)) +#define I20SCLH (*(reg32_t *)(I2C0_BASE_ADDR + 0x10)) +#define I20SCLL (*(reg32_t *)(I2C0_BASE_ADDR + 0x14)) +#define I20CONCLR (*(reg32_t *)(I2C0_BASE_ADDR + 0x18)) + +/* I2C Interface 1 */ +#define I2C1_BASE_ADDR 0xE005C000 +#define I21CONSET (*(reg32_t *)(I2C1_BASE_ADDR + 0x00)) +#define I21STAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x04)) +#define I21DAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x08)) +#define I21ADR (*(reg32_t *)(I2C1_BASE_ADDR + 0x0C)) +#define I21SCLH (*(reg32_t *)(I2C1_BASE_ADDR + 0x10)) +#define I21SCLL (*(reg32_t *)(I2C1_BASE_ADDR + 0x14)) +#define I21CONCLR (*(reg32_t *)(I2C1_BASE_ADDR + 0x18)) + +/* I2C Interface 2 */ +#define I2C2_BASE_ADDR 0xE0080000 +#define I22CONSET (*(reg32_t *)(I2C2_BASE_ADDR + 0x00)) +#define I22STAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x04)) +#define I22DAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x08)) +#define I22ADR (*(reg32_t *)(I2C2_BASE_ADDR + 0x0C)) +#define I22SCLH (*(reg32_t *)(I2C2_BASE_ADDR + 0x10)) +#define I22SCLL (*(reg32_t *)(I2C2_BASE_ADDR + 0x14)) +#define I22CONCLR (*(reg32_t *)(I2C2_BASE_ADDR + 0x18)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x00)) +#define S0SPSR (*(reg32_t *)(SPI0_BASE_ADDR + 0x04)) +#define S0SPDR (*(reg32_t *)(SPI0_BASE_ADDR + 0x08)) +#define S0SPCCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x0C)) +#define S0SPINT (*(reg32_t *)(SPI0_BASE_ADDR + 0x1C)) + +/* SSP0 Controller */ +#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0CR0 (*(reg32_t *)(SSP0_BASE_ADDR + 0x00)) +#define SSP0CR1 (*(reg32_t *)(SSP0_BASE_ADDR + 0x04)) +#define SSP0DR (*(reg32_t *)(SSP0_BASE_ADDR + 0x08)) +#define SSP0SR (*(reg32_t *)(SSP0_BASE_ADDR + 0x0C)) +#define SSP0CPSR (*(reg32_t *)(SSP0_BASE_ADDR + 0x10)) +#define SSP0IMSC (*(reg32_t *)(SSP0_BASE_ADDR + 0x14)) +#define SSP0RIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x18)) +#define SSP0MIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x1C)) +#define SSP0ICR (*(reg32_t *)(SSP0_BASE_ADDR + 0x20)) +#define SSP0DMACR (*(reg32_t *)(SSP0_BASE_ADDR + 0x24)) + +/* SSP1 Controller */ +#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1CR0 (*(reg32_t *)(SSP1_BASE_ADDR + 0x00)) +#define SSP1CR1 (*(reg32_t *)(SSP1_BASE_ADDR + 0x04)) +#define SSP1DR (*(reg32_t *)(SSP1_BASE_ADDR + 0x08)) +#define SSP1SR (*(reg32_t *)(SSP1_BASE_ADDR + 0x0C)) +#define SSP1CPSR (*(reg32_t *)(SSP1_BASE_ADDR + 0x10)) +#define SSP1IMSC (*(reg32_t *)(SSP1_BASE_ADDR + 0x14)) +#define SSP1RIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x18)) +#define SSP1MIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x1C)) +#define SSP1ICR (*(reg32_t *)(SSP1_BASE_ADDR + 0x20)) +#define SSP1DMACR (*(reg32_t *)(SSP1_BASE_ADDR + 0x24)) + + +/* Real Time Clock */ +#define RTC_BASE_ADDR 0xE0024000 +#define RTC_ILR (*(reg32_t *)(RTC_BASE_ADDR + 0x00)) +#define RTC_CTC (*(reg32_t *)(RTC_BASE_ADDR + 0x04)) +#define RTC_CCR (*(reg32_t *)(RTC_BASE_ADDR + 0x08)) +#define RTC_CIIR (*(reg32_t *)(RTC_BASE_ADDR + 0x0C)) +#define RTC_AMR (*(reg32_t *)(RTC_BASE_ADDR + 0x10)) +#define RTC_CTIME0 (*(reg32_t *)(RTC_BASE_ADDR + 0x14)) +#define RTC_CTIME1 (*(reg32_t *)(RTC_BASE_ADDR + 0x18)) +#define RTC_CTIME2 (*(reg32_t *)(RTC_BASE_ADDR + 0x1C)) +#define RTC_SEC (*(reg32_t *)(RTC_BASE_ADDR + 0x20)) +#define RTC_MIN (*(reg32_t *)(RTC_BASE_ADDR + 0x24)) +#define RTC_HOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x28)) +#define RTC_DOM (*(reg32_t *)(RTC_BASE_ADDR + 0x2C)) +#define RTC_DOW (*(reg32_t *)(RTC_BASE_ADDR + 0x30)) +#define RTC_DOY (*(reg32_t *)(RTC_BASE_ADDR + 0x34)) +#define RTC_MONTH (*(reg32_t *)(RTC_BASE_ADDR + 0x38)) +#define RTC_YEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x3C)) +#define RTC_CISS (*(reg32_t *)(RTC_BASE_ADDR + 0x40)) +#define RTC_ALSEC (*(reg32_t *)(RTC_BASE_ADDR + 0x60)) +#define RTC_ALMIN (*(reg32_t *)(RTC_BASE_ADDR + 0x64)) +#define RTC_ALHOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x68)) +#define RTC_ALDOM (*(reg32_t *)(RTC_BASE_ADDR + 0x6C)) +#define RTC_ALDOW (*(reg32_t *)(RTC_BASE_ADDR + 0x70)) +#define RTC_ALDOY (*(reg32_t *)(RTC_BASE_ADDR + 0x74)) +#define RTC_ALMON (*(reg32_t *)(RTC_BASE_ADDR + 0x78)) +#define RTC_ALYEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x7C)) +#define RTC_PREINT (*(reg32_t *)(RTC_BASE_ADDR + 0x80)) +#define RTC_PREFRAC (*(reg32_t *)(RTC_BASE_ADDR + 0x84)) + + +/* A/D Converter 0 (AD0) */ +#define AD0_BASE_ADDR 0xE0034000 +#define AD0CR (*(reg32_t *)(AD0_BASE_ADDR + 0x00)) +#define AD0GDR (*(reg32_t *)(AD0_BASE_ADDR + 0x04)) +#define AD0INTEN (*(reg32_t *)(AD0_BASE_ADDR + 0x0C)) +#define AD0DR0 (*(reg32_t *)(AD0_BASE_ADDR + 0x10)) +#define AD0DR1 (*(reg32_t *)(AD0_BASE_ADDR + 0x14)) +#define AD0DR2 (*(reg32_t *)(AD0_BASE_ADDR + 0x18)) +#define AD0DR3 (*(reg32_t *)(AD0_BASE_ADDR + 0x1C)) +#define AD0DR4 (*(reg32_t *)(AD0_BASE_ADDR + 0x20)) +#define AD0DR5 (*(reg32_t *)(AD0_BASE_ADDR + 0x24)) +#define AD0DR6 (*(reg32_t *)(AD0_BASE_ADDR + 0x28)) +#define AD0DR7 (*(reg32_t *)(AD0_BASE_ADDR + 0x2C)) +#define AD0STAT (*(reg32_t *)(AD0_BASE_ADDR + 0x30)) + + +/* D/A Converter */ +#define DAC_BASE_ADDR 0xE006C000 +#define DACR (*(reg32_t *)(DAC_BASE_ADDR + 0x00)) + + +/* Watchdog */ +#define WDG_BASE_ADDR 0xE0000000 +#define WDMOD (*(reg32_t *)(WDG_BASE_ADDR + 0x00)) +#define WDTC (*(reg32_t *)(WDG_BASE_ADDR + 0x04)) +#define WDFEED (*(reg32_t *)(WDG_BASE_ADDR + 0x08)) +#define WDTV (*(reg32_t *)(WDG_BASE_ADDR + 0x0C)) +#define WDCLKSEL (*(reg32_t *)(WDG_BASE_ADDR + 0x10)) + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x08)) + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD (*(reg32_t *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(reg32_t *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(reg32_t *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(reg32_t *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(reg32_t *)(CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(reg32_t *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(reg32_t *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(reg32_t *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(reg32_t *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(reg32_t *)(CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(reg32_t *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(reg32_t *)(CAN1_BASE_ADDR + 0x2C)) + +#define CAN1TFI1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x5C)) + +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD (*(reg32_t *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(reg32_t *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(reg32_t *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(reg32_t *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(reg32_t *)(CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(reg32_t *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(reg32_t *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(reg32_t *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(reg32_t *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(reg32_t *)(CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(reg32_t *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(reg32_t *)(CAN2_BASE_ADDR + 0x2C)) + +#define CAN2TFI1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x5C)) + + +/* MultiMedia Card Interface(MCI) Controller */ +#define MCI_BASE_ADDR 0xE008C000 +#define MCI_POWER (*(reg32_t *)(MCI_BASE_ADDR + 0x00)) +#define MCI_CLOCK (*(reg32_t *)(MCI_BASE_ADDR + 0x04)) +#define MCI_ARGUMENT (*(reg32_t *)(MCI_BASE_ADDR + 0x08)) +#define MCI_COMMAND (*(reg32_t *)(MCI_BASE_ADDR + 0x0C)) +#define MCI_RESP_CMD (*(reg32_t *)(MCI_BASE_ADDR + 0x10)) +#define MCI_RESP0 (*(reg32_t *)(MCI_BASE_ADDR + 0x14)) +#define MCI_RESP1 (*(reg32_t *)(MCI_BASE_ADDR + 0x18)) +#define MCI_RESP2 (*(reg32_t *)(MCI_BASE_ADDR + 0x1C)) +#define MCI_RESP3 (*(reg32_t *)(MCI_BASE_ADDR + 0x20)) +#define MCI_DATA_TMR (*(reg32_t *)(MCI_BASE_ADDR + 0x24)) +#define MCI_DATA_LEN (*(reg32_t *)(MCI_BASE_ADDR + 0x28)) +#define MCI_DATA_CTRL (*(reg32_t *)(MCI_BASE_ADDR + 0x2C)) +#define MCI_DATA_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x30)) +#define MCI_STATUS (*(reg32_t *)(MCI_BASE_ADDR + 0x34)) +#define MCI_CLEAR (*(reg32_t *)(MCI_BASE_ADDR + 0x38)) +#define MCI_MASK0 (*(reg32_t *)(MCI_BASE_ADDR + 0x3C)) +#define MCI_MASK1 (*(reg32_t *)(MCI_BASE_ADDR + 0x40)) +#define MCI_FIFO_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x48)) +#define MCI_FIFO (*(reg32_t *)(MCI_BASE_ADDR + 0x80)) + + +/* I2S Interface Controller (I2S) */ +#define I2S_BASE_ADDR 0xE0088000 +#define I2S_DAO (*(reg32_t *)(I2S_BASE_ADDR + 0x00)) +#define I2S_DAI (*(reg32_t *)(I2S_BASE_ADDR + 0x04)) +#define I2S_TX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x08)) +#define I2S_RX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x0C)) +#define I2S_STATE (*(reg32_t *)(I2S_BASE_ADDR + 0x10)) +#define I2S_DMA1 (*(reg32_t *)(I2S_BASE_ADDR + 0x14)) +#define I2S_DMA2 (*(reg32_t *)(I2S_BASE_ADDR + 0x18)) +#define I2S_IRQ (*(reg32_t *)(I2S_BASE_ADDR + 0x1C)) +#define I2S_TXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x20)) +#define I2S_RXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x24)) + + +/* General-purpose DMA Controller */ +#define DMA_BASE_ADDR 0xFFE04000 +#define GPDMA_INT_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x000)) +#define GPDMA_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x004)) +#define GPDMA_INT_TCCLR (*(reg32_t *)(DMA_BASE_ADDR + 0x008)) +#define GPDMA_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x00C)) +#define GPDMA_INT_ERR_CLR (*(reg32_t *)(DMA_BASE_ADDR + 0x010)) +#define GPDMA_RAW_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x014)) +#define GPDMA_RAW_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x018)) +#define GPDMA_ENABLED_CHNS (*(reg32_t *)(DMA_BASE_ADDR + 0x01C)) +#define GPDMA_SOFT_BREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x020)) +#define GPDMA_SOFT_SREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x024)) +#define GPDMA_SOFT_LBREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x028)) +#define GPDMA_SOFT_LSREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x02C)) +#define GPDMA_CONFIG (*(reg32_t *)(DMA_BASE_ADDR + 0x030)) +#define GPDMA_SYNC (*(reg32_t *)(DMA_BASE_ADDR + 0x034)) + +/* DMA channel 0 registers */ +#define GPDMA_CH0_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x100)) +#define GPDMA_CH0_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x104)) +#define GPDMA_CH0_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x108)) +#define GPDMA_CH0_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x10C)) +#define GPDMA_CH0_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x110)) + +/* DMA channel 1 registers */ +#define GPDMA_CH1_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x120)) +#define GPDMA_CH1_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x124)) +#define GPDMA_CH1_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x128)) +#define GPDMA_CH1_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x12C)) +#define GPDMA_CH1_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x130)) + + +/* USB Controller */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ + +#define USB_INT_STAT (*(reg32_t *)(USB_INT_BASE_ADDR + 0x00)) + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x00)) +#define DEV_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x04)) +#define DEV_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x08)) +#define DEV_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x0C)) +#define DEV_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x2C)) + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x30)) +#define EP_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x34)) +#define EP_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x38)) +#define EP_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x3C)) +#define EP_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x40)) + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP (*(reg32_t *)(USB_BASE_ADDR + 0x44)) +#define EP_INDEX (*(reg32_t *)(USB_BASE_ADDR + 0x48)) +#define MAXPACKET_SIZE (*(reg32_t *)(USB_BASE_ADDR + 0x4C)) + +/* USB Device Command Reagisters */ +#define CMD_CODE (*(reg32_t *)(USB_BASE_ADDR + 0x10)) +#define CMD_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x14)) + +/* USB Device Data Transfer Registers */ +#define RX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x18)) +#define TX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x1C)) +#define RX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x20)) +#define TX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x24)) +#define USB_CTRL (*(reg32_t *)(USB_BASE_ADDR + 0x28)) + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x50)) +#define DMA_REQ_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x54)) +#define DMA_REQ_SET (*(reg32_t *)(USB_BASE_ADDR + 0x58)) +#define UDCA_HEAD (*(reg32_t *)(USB_BASE_ADDR + 0x80)) +#define EP_DMA_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x84)) +#define EP_DMA_EN (*(reg32_t *)(USB_BASE_ADDR + 0x88)) +#define EP_DMA_DIS (*(reg32_t *)(USB_BASE_ADDR + 0x8C)) +#define DMA_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x90)) +#define DMA_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x94)) +#define EOT_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xA0)) +#define EOT_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xA4)) +#define EOT_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xA8)) +#define NDD_REQ_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xAC)) +#define NDD_REQ_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xB0)) +#define NDD_REQ_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xB4)) +#define SYS_ERR_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xB8)) +#define SYS_ERR_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xBC)) +#define SYS_ERR_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xC0)) + +/* USB Host and OTG registers are for LPC24xx only */ +/* USB Host Controller */ +#define USBHC_BASE_ADDR 0xFFE0C000 +#define HC_REVISION (*(reg32_t *)(USBHC_BASE_ADDR + 0x00)) +#define HC_CONTROL (*(reg32_t *)(USBHC_BASE_ADDR + 0x04)) +#define HC_CMD_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x08)) +#define HC_INT_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x0C)) +#define HC_INT_EN (*(reg32_t *)(USBHC_BASE_ADDR + 0x10)) +#define HC_INT_DIS (*(reg32_t *)(USBHC_BASE_ADDR + 0x14)) +#define HC_HCCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x18)) +#define HC_PERIOD_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x1C)) +#define HC_CTRL_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x20)) +#define HC_CTRL_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x24)) +#define HC_BULK_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x28)) +#define HC_BULK_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x2C)) +#define HC_DONE_HEAD (*(reg32_t *)(USBHC_BASE_ADDR + 0x30)) +#define HC_FM_INTERVAL (*(reg32_t *)(USBHC_BASE_ADDR + 0x34)) +#define HC_FM_REMAINING (*(reg32_t *)(USBHC_BASE_ADDR + 0x38)) +#define HC_FM_NUMBER (*(reg32_t *)(USBHC_BASE_ADDR + 0x3C)) +#define HC_PERIOD_START (*(reg32_t *)(USBHC_BASE_ADDR + 0x40)) +#define HC_LS_THRHLD (*(reg32_t *)(USBHC_BASE_ADDR + 0x44)) +#define HC_RH_DESCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x48)) +#define HC_RH_DESCB (*(reg32_t *)(USBHC_BASE_ADDR + 0x4C)) +#define HC_RH_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x50)) +#define HC_RH_PORT_STAT1 (*(reg32_t *)(USBHC_BASE_ADDR + 0x54)) +#define HC_RH_PORT_STAT2 (*(reg32_t *)(USBHC_BASE_ADDR + 0x58)) + +/* USB OTG Controller */ +#define USBOTG_BASE_ADDR 0xFFE0C100 +#define OTG_INT_STAT (*(reg32_t *)(USBOTG_BASE_ADDR + 0x00)) +#define OTG_INT_EN (*(reg32_t *)(USBOTG_BASE_ADDR + 0x04)) +#define OTG_INT_SET (*(reg32_t *)(USBOTG_BASE_ADDR + 0x08)) +#define OTG_INT_CLR (*(reg32_t *)(USBOTG_BASE_ADDR + 0x0C)) +/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ +#define OTG_STAT_CTRL (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10)) +#define OTG_TIMER (*(reg32_t *)(USBOTG_BASE_ADDR + 0x14)) + +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define OTG_I2C_RX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_TX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_STS (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x04)) +#define OTG_I2C_CTL (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x08)) +#define OTG_I2C_CLKHI (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x0C)) +#define OTG_I2C_CLKLO (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x10)) + +/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are +OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define OTG_CLK_CTRL (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04)) +#define OTG_CLK_STAT (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08)) + +/* Note: below three register name convention is for LPC23xx USB device only, match +with the spec. update in USB Device Section. */ +#define USBPortSel (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10)) +#define USBClkCtrl (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04)) +#define USBClkSt (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08)) + +/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_MAC1 (*(reg32_t *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ +#define MAC_MAC2 (*(reg32_t *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ +#define MAC_IPGT (*(reg32_t *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ +#define MAC_IPGR (*(reg32_t *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ +#define MAC_CLRT (*(reg32_t *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ +#define MAC_MAXF (*(reg32_t *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ +#define MAC_SUPP (*(reg32_t *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ +#define MAC_TEST (*(reg32_t *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ +#define MAC_MCFG (*(reg32_t *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ +#define MAC_MCMD (*(reg32_t *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ +#define MAC_MADR (*(reg32_t *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ +#define MAC_MWTD (*(reg32_t *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ +#define MAC_MRDD (*(reg32_t *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ +#define MAC_MIND (*(reg32_t *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ + +#define MAC_SA0 (*(reg32_t *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ +#define MAC_SA1 (*(reg32_t *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ +#define MAC_SA2 (*(reg32_t *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ + +#define MAC_COMMAND (*(reg32_t *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ +#define MAC_STATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ +#define MAC_RXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ +#define MAC_RXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ +#define MAC_RXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ +#define MAC_RXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ +#define MAC_RXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ +#define MAC_TXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ +#define MAC_TXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ +#define MAC_TXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ +#define MAC_TXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ +#define MAC_TXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ + +#define MAC_TSV0 (*(reg32_t *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ +#define MAC_TSV1 (*(reg32_t *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ +#define MAC_RSV (*(reg32_t *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ + +#define MAC_FLOWCONTROLCNT (*(reg32_t *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ +#define MAC_FLOWCONTROLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ + +#define MAC_RXFILTERCTRL (*(reg32_t *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ +#define MAC_RXFILTERWOLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ +#define MAC_RXFILTERWOLCLR (*(reg32_t *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ + +#define MAC_HASHFILTERL (*(reg32_t *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ +#define MAC_HASHFILTERH (*(reg32_t *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ + +#define MAC_INTSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ +#define MAC_INTENABLE (*(reg32_t *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ +#define MAC_INTCLEAR (*(reg32_t *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ +#define MAC_INTSET (*(reg32_t *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ + +#define MAC_POWERDOWN (*(reg32_t *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ +#define MAC_MODULEID (*(reg32_t *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ + +#endif /* LPC23XX_H */ diff --git a/bertos/cpu/cortex-m3/io/lm3s_pwm.h b/bertos/cpu/cortex-m3/io/lm3s_pwm.h index ec19d2f4..db2aaf2f 100644 --- a/bertos/cpu/cortex-m3/io/lm3s_pwm.h +++ b/bertos/cpu/cortex-m3/io/lm3s_pwm.h @@ -1,543 +1,543 @@ -/** - * \file - * - * - * \brief LM3S1968 PWM hardware definitions. - */ - -#ifndef L3MS_PWM_H -#define L3MS_PWM_H - -/** - * The following are defines for the PWM register offsets. - */ -#define PWM_O_CTL (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< PWM Master Control -#define PWM_O_SYNC (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< PWM Time Base Sync -#define PWM_O_ENABLE (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< PWM Output Enable -#define PWM_O_INVERT (*((reg32_t *)(PWMC_BASE + 0x0000000C))) //< PWM Output Inversion -#define PWM_O_FAULT (*((reg32_t *)(PWMC_BASE + 0x00000010))) //< PWM Output Fault -#define PWM_O_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000014))) //< PWM Interrupt Enable -#define PWM_O_RIS (*((reg32_t *)(PWMC_BASE + 0x00000018))) //< PWM Raw Interrupt Status -#define PWM_O_ISC (*((reg32_t *)(PWMC_BASE + 0x0000001C))) //< PWM Interrupt Status and Clear -#define PWM_O_STATUS (*((reg32_t *)(PWMC_BASE + 0x00000020))) //< PWM Status -#define PWM_O_FAULTVAL (*((reg32_t *)(PWMC_BASE + 0x00000024))) //< PWM Fault Condition Value -#define PWM_O_ENUPD (*((reg32_t *)(PWMC_BASE + 0x00000028))) //< PWM Enable Update -#define PWM_O_0_CTL (*((reg32_t *)(PWMC_BASE + 0x00000040))) //< PWM0 Control -#define PWM_O_0_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000044))) //< PWM0 Interrupt and Trigger Enable -#define PWM_O_0_RIS (*((reg32_t *)(PWMC_BASE + 0x00000048))) //< PWM0 Raw Interrupt Status -#define PWM_O_0_ISC (*((reg32_t *)(PWMC_BASE + 0x0000004C))) //< PWM0 Interrupt Status and Clear -#define PWM_O_0_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000050))) //< PWM0 Load -#define PWM_O_0_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000054))) //< PWM0 Counter -#define PWM_O_0_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000058))) //< PWM0 Compare A -#define PWM_O_0_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000005C))) //< PWM0 Compare B -#define PWM_O_0_GENA (*((reg32_t *)(PWMC_BASE + 0x00000060))) //< PWM0 Generator A Control -#define PWM_O_0_GENB (*((reg32_t *)(PWMC_BASE + 0x00000064))) //< PWM0 Generator B Control -#define PWM_O_0_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000068))) //< PWM0 Dead-Band Control -#define PWM_O_0_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000006C))) //< PWM0 Dead-Band Rising-Edge Delay -#define PWM_O_0_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000070))) //< PWM0 Dead-Band Falling-Edge-Delay -#define PWM_O_0_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000074))) //< PWM0 Fault Source 0 -#define PWM_O_0_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000078))) //< PWM0 Fault Source 1 -#define PWM_O_0_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000007C))) //< PWM0 Minimum Fault Period -#define PWM_O_1_CTL (*((reg32_t *)(PWMC_BASE + 0x00000080))) //< PWM1 Control -#define PWM_O_1_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000084))) //< PWM1 Interrupt and Trigger Enable -#define PWM_O_1_RIS (*((reg32_t *)(PWMC_BASE + 0x00000088))) //< PWM1 Raw Interrupt Status -#define PWM_O_1_ISC (*((reg32_t *)(PWMC_BASE + 0x0000008C))) //< PWM1 Interrupt Status and Clear -#define PWM_O_1_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000090))) //< PWM1 Load -#define PWM_O_1_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000094))) //< PWM1 Counter -#define PWM_O_1_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000098))) //< PWM1 Compare A -#define PWM_O_1_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000009C))) //< PWM1 Compare B -#define PWM_O_1_GENA (*((reg32_t *)(PWMC_BASE + 0x000000A0))) //< PWM1 Generator A Control -#define PWM_O_1_GENB (*((reg32_t *)(PWMC_BASE + 0x000000A4))) //< PWM1 Generator B Control -#define PWM_O_1_DBCTL (*((reg32_t *)(PWMC_BASE + 0x000000A8))) //< PWM1 Dead-Band Control -#define PWM_O_1_DBRISE (*((reg32_t *)(PWMC_BASE + 0x000000AC))) //< PWM1 Dead-Band Rising-Edge Delay -#define PWM_O_1_DBFALL (*((reg32_t *)(PWMC_BASE + 0x000000B0))) //< PWM1 Dead-Band Falling-Edge-Delay -#define PWM_O_1_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x000000B4))) //< PWM1 Fault Source 0 -#define PWM_O_1_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x000000B8))) //< PWM1 Fault Source 1 -#define PWM_O_1_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x000000BC))) //< PWM1 Minimum Fault Period -#define PWM_O_2_CTL (*((reg32_t *)(PWMC_BASE + 0x000000C0))) //< PWM2 Control -#define PWM_O_2_INTEN (*((reg32_t *)(PWMC_BASE + 0x000000C4))) //< PWM2 Interrupt and Trigger Enable -#define PWM_O_2_RIS (*((reg32_t *)(PWMC_BASE + 0x000000C8))) //< PWM2 Raw Interrupt Status -#define PWM_O_2_ISC (*((reg32_t *)(PWMC_BASE + 0x000000CC))) //< PWM2 Interrupt Status and Clear -#define PWM_O_2_LOAD (*((reg32_t *)(PWMC_BASE + 0x000000D0))) //< PWM2 Load -#define PWM_O_2_COUNT (*((reg32_t *)(PWMC_BASE + 0x000000D4))) //< PWM2 Counter -#define PWM_O_2_CMPA (*((reg32_t *)(PWMC_BASE + 0x000000D8))) //< PWM2 Compare A -#define PWM_O_2_CMPB (*((reg32_t *)(PWMC_BASE + 0x000000DC))) //< PWM2 Compare B -#define PWM_O_2_GENA (*((reg32_t *)(PWMC_BASE + 0x000000E0))) //< PWM2 Generator A Control -#define PWM_O_2_GENB (*((reg32_t *)(PWMC_BASE + 0x000000E4))) //< PWM2 Generator B Control -#define PWM_O_2_DBCTL (*((reg32_t *)(PWMC_BASE + 0x000000E8))) //< PWM2 Dead-Band Control -#define PWM_O_2_DBRISE (*((reg32_t *)(PWMC_BASE + 0x000000EC))) //< PWM2 Dead-Band Rising-Edge Delay -#define PWM_O_2_DBFALL (*((reg32_t *)(PWMC_BASE + 0x000000F0))) //< PWM2 Dead-Band Falling-Edge-Delay -#define PWM_O_2_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x000000F4))) //< PWM2 Fault Source 0 -#define PWM_O_2_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x000000F8))) //< PWM2 Fault Source 1 -#define PWM_O_2_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x000000FC))) //< PWM2 Minimum Fault Period -#define PWM_O_3_CTL (*((reg32_t *)(PWMC_BASE + 0x00000100))) //< PWM3 Control -#define PWM_O_3_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000104))) //< PWM3 Interrupt and Trigger Enable -#define PWM_O_3_RIS (*((reg32_t *)(PWMC_BASE + 0x00000108))) //< PWM3 Raw Interrupt Status -#define PWM_O_3_ISC (*((reg32_t *)(PWMC_BASE + 0x0000010C))) //< PWM3 Interrupt Status and Clear -#define PWM_O_3_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000110))) //< PWM3 Load -#define PWM_O_3_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000114))) //< PWM3 Counter -#define PWM_O_3_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000118))) //< PWM3 Compare A -#define PWM_O_3_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000011C))) //< PWM3 Compare B -#define PWM_O_3_GENA (*((reg32_t *)(PWMC_BASE + 0x00000120))) //< PWM3 Generator A Control -#define PWM_O_3_GENB (*((reg32_t *)(PWMC_BASE + 0x00000124))) //< PWM3 Generator B Control -#define PWM_O_3_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000128))) //< PWM3 Dead-Band Control -#define PWM_O_3_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000012C))) //< PWM3 Dead-Band Rising-Edge Delay -#define PWM_O_3_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000130))) //< PWM3 Dead-Band Falling-Edge-Delay -#define PWM_O_3_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000134))) //< PWM3 Fault Source 0 -#define PWM_O_3_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000138))) //< PWM3 Fault Source 1 -#define PWM_O_3_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000013C))) //< PWM3 Minimum Fault Period -#define PWM_O_0_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000800))) //< PWM0 Fault Pin Logic Sense -#define PWM_O_0_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000804))) //< PWM0 Fault Status 0 -#define PWM_O_0_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000808))) //< PWM0 Fault Status 1 -#define PWM_O_1_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000880))) //< PWM1 Fault Pin Logic Sense -#define PWM_O_1_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000884))) //< PWM1 Fault Status 0 -#define PWM_O_1_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000888))) //< PWM1 Fault Status 1 -#define PWM_O_2_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000900))) //< PWM2 Fault Pin Logic Sense -#define PWM_O_2_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000904))) //< PWM2 Fault Status 0 -#define PWM_O_2_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000908))) //< PWM2 Fault Status 1 -#define PWM_O_3_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000980))) //< PWM3 Fault Pin Logic Sense -#define PWM_O_3_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000984))) //< PWM3 Fault Status 0 -#define PWM_O_3_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000988))) //< PWM3 Fault Status 1 - -/** - * Defines for the bit fields in the PWM_O_CTL register. - */ -#define PWM_CTL_GLOBALSYNC3 3 //< Update PWM Generator 3 -#define PWM_CTL_GLOBALSYNC2 2 //< Update PWM Generator 2 -#define PWM_CTL_GLOBALSYNC1 1 //< Update PWM Generator 1 -#define PWM_CTL_GLOBALSYNC0 0 //< Update PWM Generator 0 - -/** - * Defines for the bit fields in the PWM_O_SYNC register. - */ -#define PWM_SYNC_SYNC3 3 //< Reset Generator 3 Counter -#define PWM_SYNC_SYNC2 2 //< Reset Generator 2 Counter -#define PWM_SYNC_SYNC1 1 //< Reset Generator 1 Counter -#define PWM_SYNC_SYNC0 0 //< Reset Generator 0 Counter - -/** - * Defines for the bit fields in the PWM_O_ENABLE register. - */ -#define PWM_ENABLE_PWM7EN 7 //< PWM7 Output Enable -#define PWM_ENABLE_PWM6EN 6 //< PWM6 Output Enable -#define PWM_ENABLE_PWM5EN 5 //< PWM5 Output Enable -#define PWM_ENABLE_PWM4EN 4 //< PWM4 Output Enable -#define PWM_ENABLE_PWM3EN 3 //< PWM3 Output Enable -#define PWM_ENABLE_PWM2EN 2 //< PWM2 Output Enable -#define PWM_ENABLE_PWM1EN 1 //< PWM1 Output Enable -#define PWM_ENABLE_PWM0EN 0 //< PWM0 Output Enable - -/** - * Defines for the bit fields in the PWM_O_INVERT register. - */ -#define PWM_INVERT_PWM7INV 7 //< Invert PWM7 Signal -#define PWM_INVERT_PWM6INV 6 //< Invert PWM6 Signal -#define PWM_INVERT_PWM5INV 5 //< Invert PWM5 Signal -#define PWM_INVERT_PWM4INV 4 //< Invert PWM4 Signal -#define PWM_INVERT_PWM3INV 3 //< Invert PWM3 Signal -#define PWM_INVERT_PWM2INV 2 //< Invert PWM2 Signal -#define PWM_INVERT_PWM1INV 1 //< Invert PWM1 Signal -#define PWM_INVERT_PWM0INV 0 //< Invert PWM0 Signal - -/** - * Defines for the bit fields in the PWM_O_FAULT register. - */ -#define PWM_FAULT_FAULT7 7 //< PWM7 Fault -#define PWM_FAULT_FAULT6 6 //< PWM6 Fault -#define PWM_FAULT_FAULT5 5 //< PWM5 Fault -#define PWM_FAULT_FAULT4 4 //< PWM4 Fault -#define PWM_FAULT_FAULT3 3 //< PWM3 Fault -#define PWM_FAULT_FAULT2 2 //< PWM2 Fault -#define PWM_FAULT_FAULT1 1 //< PWM1 Fault -#define PWM_FAULT_FAULT0 0 //< PWM0 Fault - -/** - * Defines for the bit fields in the PWM_O_INTEN register. - */ -#define PWM_INTEN_INTFAULT3 19 //< Interrupt Fault 3 -#define PWM_INTEN_INTFAULT2 18 //< Interrupt Fault 2 -#define PWM_INTEN_INTFAULT1 17 //< Interrupt Fault 1 -#define PWM_INTEN_INTFAULT 16 //< Fault Interrupt Enable -#define PWM_INTEN_INTFAULT0 16 //< Interrupt Fault 0 -#define PWM_INTEN_INTPWM3 3 //< PWM3 Interrupt Enable -#define PWM_INTEN_INTPWM2 2 //< PWM2 Interrupt Enable -#define PWM_INTEN_INTPWM1 1 //< PWM1 Interrupt Enable -#define PWM_INTEN_INTPWM0 0 //< PWM0 Interrupt Enable - -/** - * Defines for the bit fields in the PWM_O_RIS register. - */ -#define PWM_RIS_INTFAULT3 19 //< Interrupt Fault PWM 3 -#define PWM_RIS_INTFAULT2 18 //< Interrupt Fault PWM 2 -#define PWM_RIS_INTFAULT1 17 //< Interrupt Fault PWM 1 -#define PWM_RIS_INTFAULT0 16 //< Interrupt Fault PWM 0 -#define PWM_RIS_INTFAULT 16 //< Fault Interrupt Asserted -#define PWM_RIS_INTPWM3 3 //< PWM3 Interrupt Asserted -#define PWM_RIS_INTPWM2 2 //< PWM2 Interrupt Asserted -#define PWM_RIS_INTPWM1 1 //< PWM1 Interrupt Asserted -#define PWM_RIS_INTPWM0 0 //< PWM0 Interrupt Asserted - -/** - * Defines for the bit fields in the PWM_O_ISC register. - */ -#define PWM_ISC_INTFAULT3 19 //< FAULT3 Interrupt Asserted -#define PWM_ISC_INTFAULT2 18 //< FAULT2 Interrupt Asserted -#define PWM_ISC_INTFAULT1 17 //< FAULT1 Interrupt Asserted -#define PWM_ISC_INTFAULT 16 //< Fault Interrupt Asserted -#define PWM_ISC_INTFAULT0 16 //< FAULT0 Interrupt Asserted -#define PWM_ISC_INTPWM3 3 //< PWM3 Interrupt Status -#define PWM_ISC_INTPWM2 2 //< PWM2 Interrupt Status -#define PWM_ISC_INTPWM1 1 //< PWM1 Interrupt Status -#define PWM_ISC_INTPWM0 0 //< PWM0 Interrupt Status - -/** - * Defines for the bit fields in the PWM_O_STATUS register. - */ -#define PWM_STATUS_FAULT3 3 //< Generator 3 Fault Status -#define PWM_STATUS_FAULT2 2 //< Generator 2 Fault Status -#define PWM_STATUS_FAULT1 1 //< Generator 1 Fault Status -#define PWM_STATUS_FAULT0 0 //< Generator 0 Fault Status - -/** - * Defines for the bit fields in the PWM_O_FAULTVAL register. - */ -#define PWM_FAULTVAL_PWM7 7 //< PWM7 Fault Value -#define PWM_FAULTVAL_PWM6 6 //< PWM6 Fault Value -#define PWM_FAULTVAL_PWM5 5 //< PWM5 Fault Value -#define PWM_FAULTVAL_PWM4 4 //< PWM4 Fault Value -#define PWM_FAULTVAL_PWM3 3 //< PWM3 Fault Value -#define PWM_FAULTVAL_PWM2 2 //< PWM2 Fault Value -#define PWM_FAULTVAL_PWM1 1 //< PWM1 Fault Value -#define PWM_FAULTVAL_PWM0 0 //< PWM0 Fault Value - -/** - * Defines for the bit fields in the PWM_O_ENUPD register. - */ -#define PWM_ENUPD_ENUPD7_M 0x0000C000 //< PWM7 Enable Update Mode -#define PWM_ENUPD_ENUPD7_IMM 0x00000000 //< Immediate -#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 //< Locally Synchronized -#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 //< Globally Synchronized -#define PWM_ENUPD_ENUPD6_M 0x00003000 //< PWM6 Enable Update Mode -#define PWM_ENUPD_ENUPD6_IMM 0x00000000 //< Immediate -#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 //< Locally Synchronized -#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 //< Globally Synchronized -#define PWM_ENUPD_ENUPD5_M 0x00000C00 //< PWM5 Enable Update Mode -#define PWM_ENUPD_ENUPD5_IMM 0x00000000 //< Immediate -#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 //< Locally Synchronized -#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 //< Globally Synchronized -#define PWM_ENUPD_ENUPD4_M 0x00000300 //< PWM4 Enable Update Mode -#define PWM_ENUPD_ENUPD4_IMM 0x00000000 //< Immediate -#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 //< Locally Synchronized -#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 //< Globally Synchronized -#define PWM_ENUPD_ENUPD3_M 0x000000C0 //< PWM3 Enable Update Mode -#define PWM_ENUPD_ENUPD3_IMM 0x00000000 //< Immediate -#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 //< Locally Synchronized -#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 //< Globally Synchronized -#define PWM_ENUPD_ENUPD2_M 0x00000030 //< PWM2 Enable Update Mode -#define PWM_ENUPD_ENUPD2_IMM 0x00000000 //< Immediate -#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 //< Locally Synchronized -#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 //< Globally Synchronized -#define PWM_ENUPD_ENUPD1_M 0x0000000C //< PWM1 Enable Update Mode -#define PWM_ENUPD_ENUPD1_IMM 0x00000000 //< Immediate -#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 //< Locally Synchronized -#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C //< Globally Synchronized -#define PWM_ENUPD_ENUPD0_M 0x00000003 //< PWM0 Enable Update Mode -#define PWM_ENUPD_ENUPD0_IMM 0x00000000 //< Immediate -#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 //< Locally Synchronized -#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 //< Globally Synchronized - -/** - * Defines for the bit fields in the PWM_O_X_CTL register. - */ -#define PWM_X_CTL_LATCH 0x00040000 //< Latch Fault Input -#define PWM_X_CTL_MINFLTPER 0x00020000 //< Minimum Fault Period -#define PWM_X_CTL_FLTSRC 0x00010000 //< Fault Condition Source -#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 //< PWMnDBFALL Update Mode -#define PWM_X_CTL_DBFALLUPD_I 0x00000000 //< Immediate -#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 //< Locally Synchronized -#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 //< Globally Synchronized -#define PWM_X_CTL_DBRISEUPD_M 0x00003000 //< PWMnDBRISE Update Mode -#define PWM_X_CTL_DBRISEUPD_I 0x00000000 //< Immediate -#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 //< Locally Synchronized -#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 //< Globally Synchronized -#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 //< PWMnDBCTL Update Mode -#define PWM_X_CTL_DBCTLUPD_I 0x00000000 //< Immediate -#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 //< Locally Synchronized -#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 //< Globally Synchronized -#define PWM_X_CTL_GENBUPD_M 0x00000300 //< PWMnGENB Update Mode -#define PWM_X_CTL_GENBUPD_I 0x00000000 //< Immediate -#define PWM_X_CTL_GENBUPD_LS 0x00000200 //< Locally Synchronized -#define PWM_X_CTL_GENBUPD_GS 0x00000300 //< Globally Synchronized -#define PWM_X_CTL_GENAUPD_M 0x000000C0 //< PWMnGENA Update Mode -#define PWM_X_CTL_GENAUPD_I 0x00000000 //< Immediate -#define PWM_X_CTL_GENAUPD_LS 0x00000080 //< Locally Synchronized -#define PWM_X_CTL_GENAUPD_GS 0x000000C0 //< Globally Synchronized -#define PWM_X_CTL_CMPBUPD 0x00000020 //< Comparator B Update Mode -#define PWM_X_CTL_CMPAUPD 0x00000010 //< Comparator A Update Mode -#define PWM_X_CTL_LOADUPD 0x00000008 //< Load Register Update Mode -#define PWM_X_CTL_DEBUG 0x00000004 //< Debug Mode -#define PWM_X_CTL_MODE 0x00000002 //< Counter Mode -#define PWM_X_CTL_ENABLE 0x00000001 //< PWM Block Enable - -/** - * Defines for the bit fields in the PWM_O_X_INTEN register. - */ -#define PWM_X_INTEN_TRCMPBD 0x00002000 //< Trigger for Counter=PWMnCMPB Down -#define PWM_X_INTEN_TRCMPBU 0x00001000 //< Trigger for Counter=PWMnCMPB Up -#define PWM_X_INTEN_TRCMPAD 0x00000800 //< Trigger for Counter=PWMnCMPA Down -#define PWM_X_INTEN_TRCMPAU 0x00000400 //< Trigger for Counter=PWMnCMPA Up -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 //< Trigger for Counter=PWMnLOAD -#define PWM_X_INTEN_TRCNTZERO 0x00000100 //< Trigger for Counter=0 -#define PWM_X_INTEN_INTCMPBD 0x00000020 //< Interrupt for Counter=PWMnCMPB Down -#define PWM_X_INTEN_INTCMPBU 0x00000010 //< Interrupt for Counter=PWMnCMPB Up -#define PWM_X_INTEN_INTCMPAD 0x00000008 //< Interrupt for Counter=PWMnCMPA Down -#define PWM_X_INTEN_INTCMPAU 0x00000004 //< Interrupt for Counter=PWMnCMPA Up -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 //< Interrupt for Counter=PWMnLOAD -#define PWM_X_INTEN_INTCNTZERO 0x00000001 //< Interrupt for Counter=0 - -/** - * Defines for the bit fields in the PWM_O_X_RIS register. - */ -#define PWM_X_RIS_INTCMPBD 0x00000020 //< Comparator B Down Interrupt Status -#define PWM_X_RIS_INTCMPBU 0x00000010 //< Comparator B Up Interrupt Status -#define PWM_X_RIS_INTCMPAD 0x00000008 //< Comparator A Down Interrupt Status -#define PWM_X_RIS_INTCMPAU 0x00000004 //< Comparator A Up Interrupt Status -#define PWM_X_RIS_INTCNTLOAD 0x00000002 //< Counter=Load Interrupt Status -#define PWM_X_RIS_INTCNTZERO 0x00000001 //< Counter=0 Interrupt Status - -/** - * Defines for the bit fields in the PWM_O_X_ISC register. - */ -#define PWM_X_ISC_INTCMPBD 0x00000020 //< Comparator B Down Interrupt -#define PWM_X_ISC_INTCMPBU 0x00000010 //< Comparator B Up Interrupt -#define PWM_X_ISC_INTCMPAD 0x00000008 //< Comparator A Down Interrupt -#define PWM_X_ISC_INTCMPAU 0x00000004 //< Comparator A Up Interrupt -#define PWM_X_ISC_INTCNTLOAD 0x00000002 //< Counter=Load Interrupt -#define PWM_X_ISC_INTCNTZERO 0x00000001 //< Counter=0 Interrupt - -/** - * Defines for the bit fields in the PWM_O_X_LOAD register. - */ -#define PWM_X_LOAD_M 0x0000FFFF //< Counter Load Value -#define PWM_X_LOAD_S 0 - -/** - * Defines for the bit fields in the PWM_O_X_COUNT register. - */ -#define PWM_X_COUNT_M 0x0000FFFF //< Counter Value -#define PWM_X_COUNT_S 0 - -/** - * Defines for the bit fields in the PWM_O_X_CMPA register. - */ -#define PWM_X_CMPA_M 0x0000FFFF //< Comparator A Value -#define PWM_X_CMPA_S 0 - -/** - * Defines for the bit fields in the PWM_O_X_CMPB register. - */ -#define PWM_X_CMPB_M 0x0000FFFF //< Comparator B Value -#define PWM_X_CMPB_S 0 - -/** - * Defines for the bit fields in the PWM_O_X_GENA register. - */ -#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 //< Action for Comparator B Down -#define PWM_X_GENA_ACTCMPBD_NONE 0x00000000 //< Do nothing -#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 //< Invert pwmA -#define PWM_X_GENA_ACTCMPBD_ZERO 0x00000800 //< Drive pwmA Low -#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 //< Drive pwmA High -#define PWM_X_GENA_ACTCMPBU_M 0x00000300 //< Action for Comparator B Up -#define PWM_X_GENA_ACTCMPBU_NONE 0x00000000 //< Do nothing -#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 //< Invert pwmA -#define PWM_X_GENA_ACTCMPBU_ZERO 0x00000200 //< Drive pwmA Low -#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 //< Drive pwmA High -#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 //< Action for Comparator A Down -#define PWM_X_GENA_ACTCMPAD_NONE 0x00000000 //< Do nothing -#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 //< Invert pwmA -#define PWM_X_GENA_ACTCMPAD_ZERO 0x00000080 //< Drive pwmA Low -#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 //< Drive pwmA High -#define PWM_X_GENA_ACTCMPAU_M 0x00000030 //< Action for Comparator A Up -#define PWM_X_GENA_ACTCMPAU_NONE 0x00000000 //< Do nothing -#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 //< Invert pwmA -#define PWM_X_GENA_ACTCMPAU_ZERO 0x00000020 //< Drive pwmA Low -#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 //< Drive pwmA High -#define PWM_X_GENA_ACTLOAD_M 0x0000000C //< Action for Counter=LOAD -#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 //< Do nothing -#define PWM_X_GENA_ACTLOAD_INV 0x00000004 //< Invert pwmA -#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 //< Drive pwmA Low -#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C //< Drive pwmA High -#define PWM_X_GENA_ACTZERO_M 0x00000003 //< Action for Counter=0 -#define PWM_X_GENA_ACTZERO_NONE 0x00000000 //< Do nothing -#define PWM_X_GENA_ACTZERO_INV 0x00000001 //< Invert pwmA -#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 //< Drive pwmA Low -#define PWM_X_GENA_ACTZERO_ONE 0x00000003 //< Drive pwmA High - -/** - * Defines for the bit fields in the PWM_O_X_GENB register. - */ -#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 //< Action for Comparator B Down -#define PWM_X_GENB_ACTCMPBD_NONE 0x00000000 //< Do nothing -#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 //< Invert pwmB -#define PWM_X_GENB_ACTCMPBD_ZERO 0x00000800 //< Drive pwmB Low -#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 //< Drive pwmB High -#define PWM_X_GENB_ACTCMPBU_M 0x00000300 //< Action for Comparator B Up -#define PWM_X_GENB_ACTCMPBU_NONE 0x00000000 //< Do nothing -#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 //< Invert pwmB -#define PWM_X_GENB_ACTCMPBU_ZERO 0x00000200 //< Drive pwmB Low -#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 //< Drive pwmB High -#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 //< Action for Comparator A Down -#define PWM_X_GENB_ACTCMPAD_NONE 0x00000000 //< Do nothing -#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 //< Invert pwmB -#define PWM_X_GENB_ACTCMPAD_ZERO 0x00000080 //< Drive pwmB Low -#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 //< Drive pwmB High -#define PWM_X_GENB_ACTCMPAU_M 0x00000030 //< Action for Comparator A Up -#define PWM_X_GENB_ACTCMPAU_NONE 0x00000000 //< Do nothing -#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 //< Invert pwmB -#define PWM_X_GENB_ACTCMPAU_ZERO 0x00000020 //< Drive pwmB Low -#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 //< Drive pwmB High -#define PWM_X_GENB_ACTLOAD_M 0x0000000C //< Action for Counter=LOAD -#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 //< Do nothing -#define PWM_X_GENB_ACTLOAD_INV 0x00000004 //< Invert pwmB -#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 //< Drive pwmB Low -#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C //< Drive pwmB High -#define PWM_X_GENB_ACTZERO_M 0x00000003 //< Action for Counter=0 -#define PWM_X_GENB_ACTZERO_NONE 0x00000000 //< Do nothing -#define PWM_X_GENB_ACTZERO_INV 0x00000001 //< Invert pwmB -#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 //< Drive pwmB Low -#define PWM_X_GENB_ACTZERO_ONE 0x00000003 //< Drive pwmB High - -/** - * Defines for the bit fields in the PWM_O_X_DBCTL register. - */ -#define PWM_X_DBCTL_ENABLE 0x00000001 //< Dead-Band Generator Enable -/** - * Defines for the bit fields in the PWM_O_X_DBRISE register. - */ -#define PWM_X_DBRISE_DELAY_M 0x00000FFF //< Dead-Band Rise Delay -#define PWM_X_DBRISE_DELAY_S 0 - -/** - * Defines for the bit fields in the PWM_O_X_DBFALL register. - */ -#define PWM_X_DBFALL_DELAY_M 0x00000FFF //< Dead-Band Fall Delay -#define PWM_X_DBFALL_DELAY_S 0 - -/** - * Defines for the bit fields in the PWM_O_X_FLTSRC0 register. - */ -#define PWM_X_FLTSRC0_FAULT3 0x00000008 //< Fault3 Input -#define PWM_X_FLTSRC0_FAULT2 0x00000004 //< Fault2 Input -#define PWM_X_FLTSRC0_FAULT1 0x00000002 //< Fault1 Input -#define PWM_X_FLTSRC0_FAULT0 0x00000001 //< Fault0 Input - -/** - * The following are defines for the bit fields in the PWM_O_X_FLTSRC1 register. - */ -#define PWM_X_FLTSRC1_DCMP7 0x00000080 //< Digital Comparator 7 -#define PWM_X_FLTSRC1_DCMP6 0x00000040 //< Digital Comparator 6 -#define PWM_X_FLTSRC1_DCMP5 0x00000020 //< Digital Comparator 5 -#define PWM_X_FLTSRC1_DCMP4 0x00000010 //< Digital Comparator 4 -#define PWM_X_FLTSRC1_DCMP3 0x00000008 //< Digital Comparator 3 -#define PWM_X_FLTSRC1_DCMP2 0x00000004 //< Digital Comparator 2 -#define PWM_X_FLTSRC1_DCMP1 0x00000002 //< Digital Comparator 1 -#define PWM_X_FLTSRC1_DCMP0 0x00000001 //< Digital Comparator 0 - -/** - * Defines for the bit fields in the PWM_O_X_MINFLTPER register. - */ -#define PWM_X_MINFLTPER_M 0x0000FFFF //< Minimum Fault Period -#define PWM_X_MINFLTPER_S 0 - -/** - * Defines for the bit fields in the PWM_O_X_FLTSEN register. - */ -#define PWM_X_FLTSEN_FAULT3 0x00000008 //< Fault3 Sense -#define PWM_X_FLTSEN_FAULT2 0x00000004 //< Fault2 Sense -#define PWM_X_FLTSEN_FAULT1 0x00000002 //< Fault1 Sense -#define PWM_X_FLTSEN_FAULT0 0x00000001 //< Fault0 Sense - -/** - * Defines for the bit fields in the PWM_O_X_FLTSTAT0 register. - */ -#define PWM_X_FLTSTAT0_FAULT3 0x00000008 //< Fault Input 3 -#define PWM_X_FLTSTAT0_FAULT2 0x00000004 //< Fault Input 2 -#define PWM_X_FLTSTAT0_FAULT1 0x00000002 //< Fault Input 1 -#define PWM_X_FLTSTAT0_FAULT0 0x00000001 //< Fault Input 0 - -/** - * Defines for the bit fields in the PWM_O_X_FLTSTAT1 register. - */ -#define PWM_X_FLTSTAT1_DCMP7 0x00000080 //< Digital Comparator 7 Trigger -#define PWM_X_FLTSTAT1_DCMP6 0x00000040 //< Digital Comparator 6 Trigger -#define PWM_X_FLTSTAT1_DCMP5 0x00000020 //< Digital Comparator 5 Trigger -#define PWM_X_FLTSTAT1_DCMP4 0x00000010 //< Digital Comparator 4 Trigger -#define PWM_X_FLTSTAT1_DCMP3 0x00000008 //< Digital Comparator 3 Trigger -#define PWM_X_FLTSTAT1_DCMP2 0x00000004 //< Digital Comparator 2 Trigger -#define PWM_X_FLTSTAT1_DCMP1 0x00000002 //< Digital Comparator 1 Trigger -#define PWM_X_FLTSTAT1_DCMP0 0x00000001 //< Digital Comparator 0 Trigger - -/** - * Defines for the PWM Generator standard offsets. - */ -#define PWM_O_X_CTL (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< Gen Control Reg -#define PWM_O_X_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< Gen Int/Trig Enable Reg -#define PWM_O_X_RIS (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< Gen Raw Int Status Reg -#define PWM_O_X_ISC (*((reg32_t *)(PWMC_BASE + 0x0000000C))) //< Gen Int Status Reg -#define PWM_O_X_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000010))) //< Gen Load Reg -#define PWM_O_X_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000014))) //< Gen Counter Reg -#define PWM_O_X_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000018))) //< Gen Compare A Reg -#define PWM_O_X_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000001C))) //< Gen Compare B Reg -#define PWM_O_X_GENA (*((reg32_t *)(PWMC_BASE + 0x00000020))) //< Gen Generator A Ctrl Reg -#define PWM_O_X_GENB (*((reg32_t *)(PWMC_BASE + 0x00000024))) //< Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000028))) //< Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000002C))) //< Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000030))) //< Gen DB Falling Edge Delay Reg -#define PWM_O_X_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000034))) //< Fault pin, comparator condition -#define PWM_O_X_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000038))) //< Digital comparator condition -#define PWM_O_X_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000003C))) //< Fault minimum period extension -#define PWM_GEN_0_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000040))) //< PWM0 base -#define PWM_GEN_1_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000080))) //< PWM1 base -#define PWM_GEN_2_OFFSET (*((reg32_t *)(PWMC_BASE + 0x000000C0))) //< PWM2 base -#define PWM_GEN_3_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000100))) //< PWM3 base - -/** - * Defines for the PWM Generator extended offsets. - */ -#define PWM_O_X_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< Fault logic sense -#define PWM_O_X_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< Pin and comparator status -#define PWM_O_X_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< Digital comparator status -#define PWM_EXT_0_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000800))) //< PWM0 extended base -#define PWM_EXT_1_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000880))) //< PWM1 extended base -#define PWM_EXT_2_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000900))) //< PWM2 extended base -#define PWM_EXT_3_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000980))) //< PWM3 extended base - -#endif /* LM3S_PWM_H */ +/** + * \file + * + * + * \brief LM3S1968 PWM hardware definitions. + */ + +#ifndef L3MS_PWM_H +#define L3MS_PWM_H + +/** + * The following are defines for the PWM register offsets. + */ +#define PWM_O_CTL (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< PWM Master Control +#define PWM_O_SYNC (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< PWM Time Base Sync +#define PWM_O_ENABLE (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< PWM Output Enable +#define PWM_O_INVERT (*((reg32_t *)(PWMC_BASE + 0x0000000C))) //< PWM Output Inversion +#define PWM_O_FAULT (*((reg32_t *)(PWMC_BASE + 0x00000010))) //< PWM Output Fault +#define PWM_O_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000014))) //< PWM Interrupt Enable +#define PWM_O_RIS (*((reg32_t *)(PWMC_BASE + 0x00000018))) //< PWM Raw Interrupt Status +#define PWM_O_ISC (*((reg32_t *)(PWMC_BASE + 0x0000001C))) //< PWM Interrupt Status and Clear +#define PWM_O_STATUS (*((reg32_t *)(PWMC_BASE + 0x00000020))) //< PWM Status +#define PWM_O_FAULTVAL (*((reg32_t *)(PWMC_BASE + 0x00000024))) //< PWM Fault Condition Value +#define PWM_O_ENUPD (*((reg32_t *)(PWMC_BASE + 0x00000028))) //< PWM Enable Update +#define PWM_O_0_CTL (*((reg32_t *)(PWMC_BASE + 0x00000040))) //< PWM0 Control +#define PWM_O_0_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000044))) //< PWM0 Interrupt and Trigger Enable +#define PWM_O_0_RIS (*((reg32_t *)(PWMC_BASE + 0x00000048))) //< PWM0 Raw Interrupt Status +#define PWM_O_0_ISC (*((reg32_t *)(PWMC_BASE + 0x0000004C))) //< PWM0 Interrupt Status and Clear +#define PWM_O_0_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000050))) //< PWM0 Load +#define PWM_O_0_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000054))) //< PWM0 Counter +#define PWM_O_0_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000058))) //< PWM0 Compare A +#define PWM_O_0_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000005C))) //< PWM0 Compare B +#define PWM_O_0_GENA (*((reg32_t *)(PWMC_BASE + 0x00000060))) //< PWM0 Generator A Control +#define PWM_O_0_GENB (*((reg32_t *)(PWMC_BASE + 0x00000064))) //< PWM0 Generator B Control +#define PWM_O_0_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000068))) //< PWM0 Dead-Band Control +#define PWM_O_0_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000006C))) //< PWM0 Dead-Band Rising-Edge Delay +#define PWM_O_0_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000070))) //< PWM0 Dead-Band Falling-Edge-Delay +#define PWM_O_0_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000074))) //< PWM0 Fault Source 0 +#define PWM_O_0_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000078))) //< PWM0 Fault Source 1 +#define PWM_O_0_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000007C))) //< PWM0 Minimum Fault Period +#define PWM_O_1_CTL (*((reg32_t *)(PWMC_BASE + 0x00000080))) //< PWM1 Control +#define PWM_O_1_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000084))) //< PWM1 Interrupt and Trigger Enable +#define PWM_O_1_RIS (*((reg32_t *)(PWMC_BASE + 0x00000088))) //< PWM1 Raw Interrupt Status +#define PWM_O_1_ISC (*((reg32_t *)(PWMC_BASE + 0x0000008C))) //< PWM1 Interrupt Status and Clear +#define PWM_O_1_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000090))) //< PWM1 Load +#define PWM_O_1_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000094))) //< PWM1 Counter +#define PWM_O_1_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000098))) //< PWM1 Compare A +#define PWM_O_1_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000009C))) //< PWM1 Compare B +#define PWM_O_1_GENA (*((reg32_t *)(PWMC_BASE + 0x000000A0))) //< PWM1 Generator A Control +#define PWM_O_1_GENB (*((reg32_t *)(PWMC_BASE + 0x000000A4))) //< PWM1 Generator B Control +#define PWM_O_1_DBCTL (*((reg32_t *)(PWMC_BASE + 0x000000A8))) //< PWM1 Dead-Band Control +#define PWM_O_1_DBRISE (*((reg32_t *)(PWMC_BASE + 0x000000AC))) //< PWM1 Dead-Band Rising-Edge Delay +#define PWM_O_1_DBFALL (*((reg32_t *)(PWMC_BASE + 0x000000B0))) //< PWM1 Dead-Band Falling-Edge-Delay +#define PWM_O_1_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x000000B4))) //< PWM1 Fault Source 0 +#define PWM_O_1_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x000000B8))) //< PWM1 Fault Source 1 +#define PWM_O_1_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x000000BC))) //< PWM1 Minimum Fault Period +#define PWM_O_2_CTL (*((reg32_t *)(PWMC_BASE + 0x000000C0))) //< PWM2 Control +#define PWM_O_2_INTEN (*((reg32_t *)(PWMC_BASE + 0x000000C4))) //< PWM2 Interrupt and Trigger Enable +#define PWM_O_2_RIS (*((reg32_t *)(PWMC_BASE + 0x000000C8))) //< PWM2 Raw Interrupt Status +#define PWM_O_2_ISC (*((reg32_t *)(PWMC_BASE + 0x000000CC))) //< PWM2 Interrupt Status and Clear +#define PWM_O_2_LOAD (*((reg32_t *)(PWMC_BASE + 0x000000D0))) //< PWM2 Load +#define PWM_O_2_COUNT (*((reg32_t *)(PWMC_BASE + 0x000000D4))) //< PWM2 Counter +#define PWM_O_2_CMPA (*((reg32_t *)(PWMC_BASE + 0x000000D8))) //< PWM2 Compare A +#define PWM_O_2_CMPB (*((reg32_t *)(PWMC_BASE + 0x000000DC))) //< PWM2 Compare B +#define PWM_O_2_GENA (*((reg32_t *)(PWMC_BASE + 0x000000E0))) //< PWM2 Generator A Control +#define PWM_O_2_GENB (*((reg32_t *)(PWMC_BASE + 0x000000E4))) //< PWM2 Generator B Control +#define PWM_O_2_DBCTL (*((reg32_t *)(PWMC_BASE + 0x000000E8))) //< PWM2 Dead-Band Control +#define PWM_O_2_DBRISE (*((reg32_t *)(PWMC_BASE + 0x000000EC))) //< PWM2 Dead-Band Rising-Edge Delay +#define PWM_O_2_DBFALL (*((reg32_t *)(PWMC_BASE + 0x000000F0))) //< PWM2 Dead-Band Falling-Edge-Delay +#define PWM_O_2_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x000000F4))) //< PWM2 Fault Source 0 +#define PWM_O_2_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x000000F8))) //< PWM2 Fault Source 1 +#define PWM_O_2_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x000000FC))) //< PWM2 Minimum Fault Period +#define PWM_O_3_CTL (*((reg32_t *)(PWMC_BASE + 0x00000100))) //< PWM3 Control +#define PWM_O_3_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000104))) //< PWM3 Interrupt and Trigger Enable +#define PWM_O_3_RIS (*((reg32_t *)(PWMC_BASE + 0x00000108))) //< PWM3 Raw Interrupt Status +#define PWM_O_3_ISC (*((reg32_t *)(PWMC_BASE + 0x0000010C))) //< PWM3 Interrupt Status and Clear +#define PWM_O_3_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000110))) //< PWM3 Load +#define PWM_O_3_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000114))) //< PWM3 Counter +#define PWM_O_3_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000118))) //< PWM3 Compare A +#define PWM_O_3_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000011C))) //< PWM3 Compare B +#define PWM_O_3_GENA (*((reg32_t *)(PWMC_BASE + 0x00000120))) //< PWM3 Generator A Control +#define PWM_O_3_GENB (*((reg32_t *)(PWMC_BASE + 0x00000124))) //< PWM3 Generator B Control +#define PWM_O_3_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000128))) //< PWM3 Dead-Band Control +#define PWM_O_3_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000012C))) //< PWM3 Dead-Band Rising-Edge Delay +#define PWM_O_3_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000130))) //< PWM3 Dead-Band Falling-Edge-Delay +#define PWM_O_3_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000134))) //< PWM3 Fault Source 0 +#define PWM_O_3_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000138))) //< PWM3 Fault Source 1 +#define PWM_O_3_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000013C))) //< PWM3 Minimum Fault Period +#define PWM_O_0_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000800))) //< PWM0 Fault Pin Logic Sense +#define PWM_O_0_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000804))) //< PWM0 Fault Status 0 +#define PWM_O_0_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000808))) //< PWM0 Fault Status 1 +#define PWM_O_1_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000880))) //< PWM1 Fault Pin Logic Sense +#define PWM_O_1_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000884))) //< PWM1 Fault Status 0 +#define PWM_O_1_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000888))) //< PWM1 Fault Status 1 +#define PWM_O_2_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000900))) //< PWM2 Fault Pin Logic Sense +#define PWM_O_2_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000904))) //< PWM2 Fault Status 0 +#define PWM_O_2_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000908))) //< PWM2 Fault Status 1 +#define PWM_O_3_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000980))) //< PWM3 Fault Pin Logic Sense +#define PWM_O_3_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000984))) //< PWM3 Fault Status 0 +#define PWM_O_3_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000988))) //< PWM3 Fault Status 1 + +/** + * Defines for the bit fields in the PWM_O_CTL register. + */ +#define PWM_CTL_GLOBALSYNC3 3 //< Update PWM Generator 3 +#define PWM_CTL_GLOBALSYNC2 2 //< Update PWM Generator 2 +#define PWM_CTL_GLOBALSYNC1 1 //< Update PWM Generator 1 +#define PWM_CTL_GLOBALSYNC0 0 //< Update PWM Generator 0 + +/** + * Defines for the bit fields in the PWM_O_SYNC register. + */ +#define PWM_SYNC_SYNC3 3 //< Reset Generator 3 Counter +#define PWM_SYNC_SYNC2 2 //< Reset Generator 2 Counter +#define PWM_SYNC_SYNC1 1 //< Reset Generator 1 Counter +#define PWM_SYNC_SYNC0 0 //< Reset Generator 0 Counter + +/** + * Defines for the bit fields in the PWM_O_ENABLE register. + */ +#define PWM_ENABLE_PWM7EN 7 //< PWM7 Output Enable +#define PWM_ENABLE_PWM6EN 6 //< PWM6 Output Enable +#define PWM_ENABLE_PWM5EN 5 //< PWM5 Output Enable +#define PWM_ENABLE_PWM4EN 4 //< PWM4 Output Enable +#define PWM_ENABLE_PWM3EN 3 //< PWM3 Output Enable +#define PWM_ENABLE_PWM2EN 2 //< PWM2 Output Enable +#define PWM_ENABLE_PWM1EN 1 //< PWM1 Output Enable +#define PWM_ENABLE_PWM0EN 0 //< PWM0 Output Enable + +/** + * Defines for the bit fields in the PWM_O_INVERT register. + */ +#define PWM_INVERT_PWM7INV 7 //< Invert PWM7 Signal +#define PWM_INVERT_PWM6INV 6 //< Invert PWM6 Signal +#define PWM_INVERT_PWM5INV 5 //< Invert PWM5 Signal +#define PWM_INVERT_PWM4INV 4 //< Invert PWM4 Signal +#define PWM_INVERT_PWM3INV 3 //< Invert PWM3 Signal +#define PWM_INVERT_PWM2INV 2 //< Invert PWM2 Signal +#define PWM_INVERT_PWM1INV 1 //< Invert PWM1 Signal +#define PWM_INVERT_PWM0INV 0 //< Invert PWM0 Signal + +/** + * Defines for the bit fields in the PWM_O_FAULT register. + */ +#define PWM_FAULT_FAULT7 7 //< PWM7 Fault +#define PWM_FAULT_FAULT6 6 //< PWM6 Fault +#define PWM_FAULT_FAULT5 5 //< PWM5 Fault +#define PWM_FAULT_FAULT4 4 //< PWM4 Fault +#define PWM_FAULT_FAULT3 3 //< PWM3 Fault +#define PWM_FAULT_FAULT2 2 //< PWM2 Fault +#define PWM_FAULT_FAULT1 1 //< PWM1 Fault +#define PWM_FAULT_FAULT0 0 //< PWM0 Fault + +/** + * Defines for the bit fields in the PWM_O_INTEN register. + */ +#define PWM_INTEN_INTFAULT3 19 //< Interrupt Fault 3 +#define PWM_INTEN_INTFAULT2 18 //< Interrupt Fault 2 +#define PWM_INTEN_INTFAULT1 17 //< Interrupt Fault 1 +#define PWM_INTEN_INTFAULT 16 //< Fault Interrupt Enable +#define PWM_INTEN_INTFAULT0 16 //< Interrupt Fault 0 +#define PWM_INTEN_INTPWM3 3 //< PWM3 Interrupt Enable +#define PWM_INTEN_INTPWM2 2 //< PWM2 Interrupt Enable +#define PWM_INTEN_INTPWM1 1 //< PWM1 Interrupt Enable +#define PWM_INTEN_INTPWM0 0 //< PWM0 Interrupt Enable + +/** + * Defines for the bit fields in the PWM_O_RIS register. + */ +#define PWM_RIS_INTFAULT3 19 //< Interrupt Fault PWM 3 +#define PWM_RIS_INTFAULT2 18 //< Interrupt Fault PWM 2 +#define PWM_RIS_INTFAULT1 17 //< Interrupt Fault PWM 1 +#define PWM_RIS_INTFAULT0 16 //< Interrupt Fault PWM 0 +#define PWM_RIS_INTFAULT 16 //< Fault Interrupt Asserted +#define PWM_RIS_INTPWM3 3 //< PWM3 Interrupt Asserted +#define PWM_RIS_INTPWM2 2 //< PWM2 Interrupt Asserted +#define PWM_RIS_INTPWM1 1 //< PWM1 Interrupt Asserted +#define PWM_RIS_INTPWM0 0 //< PWM0 Interrupt Asserted + +/** + * Defines for the bit fields in the PWM_O_ISC register. + */ +#define PWM_ISC_INTFAULT3 19 //< FAULT3 Interrupt Asserted +#define PWM_ISC_INTFAULT2 18 //< FAULT2 Interrupt Asserted +#define PWM_ISC_INTFAULT1 17 //< FAULT1 Interrupt Asserted +#define PWM_ISC_INTFAULT 16 //< Fault Interrupt Asserted +#define PWM_ISC_INTFAULT0 16 //< FAULT0 Interrupt Asserted +#define PWM_ISC_INTPWM3 3 //< PWM3 Interrupt Status +#define PWM_ISC_INTPWM2 2 //< PWM2 Interrupt Status +#define PWM_ISC_INTPWM1 1 //< PWM1 Interrupt Status +#define PWM_ISC_INTPWM0 0 //< PWM0 Interrupt Status + +/** + * Defines for the bit fields in the PWM_O_STATUS register. + */ +#define PWM_STATUS_FAULT3 3 //< Generator 3 Fault Status +#define PWM_STATUS_FAULT2 2 //< Generator 2 Fault Status +#define PWM_STATUS_FAULT1 1 //< Generator 1 Fault Status +#define PWM_STATUS_FAULT0 0 //< Generator 0 Fault Status + +/** + * Defines for the bit fields in the PWM_O_FAULTVAL register. + */ +#define PWM_FAULTVAL_PWM7 7 //< PWM7 Fault Value +#define PWM_FAULTVAL_PWM6 6 //< PWM6 Fault Value +#define PWM_FAULTVAL_PWM5 5 //< PWM5 Fault Value +#define PWM_FAULTVAL_PWM4 4 //< PWM4 Fault Value +#define PWM_FAULTVAL_PWM3 3 //< PWM3 Fault Value +#define PWM_FAULTVAL_PWM2 2 //< PWM2 Fault Value +#define PWM_FAULTVAL_PWM1 1 //< PWM1 Fault Value +#define PWM_FAULTVAL_PWM0 0 //< PWM0 Fault Value + +/** + * Defines for the bit fields in the PWM_O_ENUPD register. + */ +#define PWM_ENUPD_ENUPD7_M 0x0000C000 //< PWM7 Enable Update Mode +#define PWM_ENUPD_ENUPD7_IMM 0x00000000 //< Immediate +#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 //< Locally Synchronized +#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 //< Globally Synchronized +#define PWM_ENUPD_ENUPD6_M 0x00003000 //< PWM6 Enable Update Mode +#define PWM_ENUPD_ENUPD6_IMM 0x00000000 //< Immediate +#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 //< Locally Synchronized +#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 //< Globally Synchronized +#define PWM_ENUPD_ENUPD5_M 0x00000C00 //< PWM5 Enable Update Mode +#define PWM_ENUPD_ENUPD5_IMM 0x00000000 //< Immediate +#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 //< Locally Synchronized +#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 //< Globally Synchronized +#define PWM_ENUPD_ENUPD4_M 0x00000300 //< PWM4 Enable Update Mode +#define PWM_ENUPD_ENUPD4_IMM 0x00000000 //< Immediate +#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 //< Locally Synchronized +#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 //< Globally Synchronized +#define PWM_ENUPD_ENUPD3_M 0x000000C0 //< PWM3 Enable Update Mode +#define PWM_ENUPD_ENUPD3_IMM 0x00000000 //< Immediate +#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 //< Locally Synchronized +#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 //< Globally Synchronized +#define PWM_ENUPD_ENUPD2_M 0x00000030 //< PWM2 Enable Update Mode +#define PWM_ENUPD_ENUPD2_IMM 0x00000000 //< Immediate +#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 //< Locally Synchronized +#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 //< Globally Synchronized +#define PWM_ENUPD_ENUPD1_M 0x0000000C //< PWM1 Enable Update Mode +#define PWM_ENUPD_ENUPD1_IMM 0x00000000 //< Immediate +#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 //< Locally Synchronized +#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C //< Globally Synchronized +#define PWM_ENUPD_ENUPD0_M 0x00000003 //< PWM0 Enable Update Mode +#define PWM_ENUPD_ENUPD0_IMM 0x00000000 //< Immediate +#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 //< Locally Synchronized +#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 //< Globally Synchronized + +/** + * Defines for the bit fields in the PWM_O_X_CTL register. + */ +#define PWM_X_CTL_LATCH 0x00040000 //< Latch Fault Input +#define PWM_X_CTL_MINFLTPER 0x00020000 //< Minimum Fault Period +#define PWM_X_CTL_FLTSRC 0x00010000 //< Fault Condition Source +#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 //< PWMnDBFALL Update Mode +#define PWM_X_CTL_DBFALLUPD_I 0x00000000 //< Immediate +#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 //< Locally Synchronized +#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 //< Globally Synchronized +#define PWM_X_CTL_DBRISEUPD_M 0x00003000 //< PWMnDBRISE Update Mode +#define PWM_X_CTL_DBRISEUPD_I 0x00000000 //< Immediate +#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 //< Locally Synchronized +#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 //< Globally Synchronized +#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 //< PWMnDBCTL Update Mode +#define PWM_X_CTL_DBCTLUPD_I 0x00000000 //< Immediate +#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 //< Locally Synchronized +#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 //< Globally Synchronized +#define PWM_X_CTL_GENBUPD_M 0x00000300 //< PWMnGENB Update Mode +#define PWM_X_CTL_GENBUPD_I 0x00000000 //< Immediate +#define PWM_X_CTL_GENBUPD_LS 0x00000200 //< Locally Synchronized +#define PWM_X_CTL_GENBUPD_GS 0x00000300 //< Globally Synchronized +#define PWM_X_CTL_GENAUPD_M 0x000000C0 //< PWMnGENA Update Mode +#define PWM_X_CTL_GENAUPD_I 0x00000000 //< Immediate +#define PWM_X_CTL_GENAUPD_LS 0x00000080 //< Locally Synchronized +#define PWM_X_CTL_GENAUPD_GS 0x000000C0 //< Globally Synchronized +#define PWM_X_CTL_CMPBUPD 0x00000020 //< Comparator B Update Mode +#define PWM_X_CTL_CMPAUPD 0x00000010 //< Comparator A Update Mode +#define PWM_X_CTL_LOADUPD 0x00000008 //< Load Register Update Mode +#define PWM_X_CTL_DEBUG 0x00000004 //< Debug Mode +#define PWM_X_CTL_MODE 0x00000002 //< Counter Mode +#define PWM_X_CTL_ENABLE 0x00000001 //< PWM Block Enable + +/** + * Defines for the bit fields in the PWM_O_X_INTEN register. + */ +#define PWM_X_INTEN_TRCMPBD 0x00002000 //< Trigger for Counter=PWMnCMPB Down +#define PWM_X_INTEN_TRCMPBU 0x00001000 //< Trigger for Counter=PWMnCMPB Up +#define PWM_X_INTEN_TRCMPAD 0x00000800 //< Trigger for Counter=PWMnCMPA Down +#define PWM_X_INTEN_TRCMPAU 0x00000400 //< Trigger for Counter=PWMnCMPA Up +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 //< Trigger for Counter=PWMnLOAD +#define PWM_X_INTEN_TRCNTZERO 0x00000100 //< Trigger for Counter=0 +#define PWM_X_INTEN_INTCMPBD 0x00000020 //< Interrupt for Counter=PWMnCMPB Down +#define PWM_X_INTEN_INTCMPBU 0x00000010 //< Interrupt for Counter=PWMnCMPB Up +#define PWM_X_INTEN_INTCMPAD 0x00000008 //< Interrupt for Counter=PWMnCMPA Down +#define PWM_X_INTEN_INTCMPAU 0x00000004 //< Interrupt for Counter=PWMnCMPA Up +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 //< Interrupt for Counter=PWMnLOAD +#define PWM_X_INTEN_INTCNTZERO 0x00000001 //< Interrupt for Counter=0 + +/** + * Defines for the bit fields in the PWM_O_X_RIS register. + */ +#define PWM_X_RIS_INTCMPBD 0x00000020 //< Comparator B Down Interrupt Status +#define PWM_X_RIS_INTCMPBU 0x00000010 //< Comparator B Up Interrupt Status +#define PWM_X_RIS_INTCMPAD 0x00000008 //< Comparator A Down Interrupt Status +#define PWM_X_RIS_INTCMPAU 0x00000004 //< Comparator A Up Interrupt Status +#define PWM_X_RIS_INTCNTLOAD 0x00000002 //< Counter=Load Interrupt Status +#define PWM_X_RIS_INTCNTZERO 0x00000001 //< Counter=0 Interrupt Status + +/** + * Defines for the bit fields in the PWM_O_X_ISC register. + */ +#define PWM_X_ISC_INTCMPBD 0x00000020 //< Comparator B Down Interrupt +#define PWM_X_ISC_INTCMPBU 0x00000010 //< Comparator B Up Interrupt +#define PWM_X_ISC_INTCMPAD 0x00000008 //< Comparator A Down Interrupt +#define PWM_X_ISC_INTCMPAU 0x00000004 //< Comparator A Up Interrupt +#define PWM_X_ISC_INTCNTLOAD 0x00000002 //< Counter=Load Interrupt +#define PWM_X_ISC_INTCNTZERO 0x00000001 //< Counter=0 Interrupt + +/** + * Defines for the bit fields in the PWM_O_X_LOAD register. + */ +#define PWM_X_LOAD_M 0x0000FFFF //< Counter Load Value +#define PWM_X_LOAD_S 0 + +/** + * Defines for the bit fields in the PWM_O_X_COUNT register. + */ +#define PWM_X_COUNT_M 0x0000FFFF //< Counter Value +#define PWM_X_COUNT_S 0 + +/** + * Defines for the bit fields in the PWM_O_X_CMPA register. + */ +#define PWM_X_CMPA_M 0x0000FFFF //< Comparator A Value +#define PWM_X_CMPA_S 0 + +/** + * Defines for the bit fields in the PWM_O_X_CMPB register. + */ +#define PWM_X_CMPB_M 0x0000FFFF //< Comparator B Value +#define PWM_X_CMPB_S 0 + +/** + * Defines for the bit fields in the PWM_O_X_GENA register. + */ +#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 //< Action for Comparator B Down +#define PWM_X_GENA_ACTCMPBD_NONE 0x00000000 //< Do nothing +#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 //< Invert pwmA +#define PWM_X_GENA_ACTCMPBD_ZERO 0x00000800 //< Drive pwmA Low +#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 //< Drive pwmA High +#define PWM_X_GENA_ACTCMPBU_M 0x00000300 //< Action for Comparator B Up +#define PWM_X_GENA_ACTCMPBU_NONE 0x00000000 //< Do nothing +#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 //< Invert pwmA +#define PWM_X_GENA_ACTCMPBU_ZERO 0x00000200 //< Drive pwmA Low +#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 //< Drive pwmA High +#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 //< Action for Comparator A Down +#define PWM_X_GENA_ACTCMPAD_NONE 0x00000000 //< Do nothing +#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 //< Invert pwmA +#define PWM_X_GENA_ACTCMPAD_ZERO 0x00000080 //< Drive pwmA Low +#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 //< Drive pwmA High +#define PWM_X_GENA_ACTCMPAU_M 0x00000030 //< Action for Comparator A Up +#define PWM_X_GENA_ACTCMPAU_NONE 0x00000000 //< Do nothing +#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 //< Invert pwmA +#define PWM_X_GENA_ACTCMPAU_ZERO 0x00000020 //< Drive pwmA Low +#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 //< Drive pwmA High +#define PWM_X_GENA_ACTLOAD_M 0x0000000C //< Action for Counter=LOAD +#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 //< Do nothing +#define PWM_X_GENA_ACTLOAD_INV 0x00000004 //< Invert pwmA +#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 //< Drive pwmA Low +#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C //< Drive pwmA High +#define PWM_X_GENA_ACTZERO_M 0x00000003 //< Action for Counter=0 +#define PWM_X_GENA_ACTZERO_NONE 0x00000000 //< Do nothing +#define PWM_X_GENA_ACTZERO_INV 0x00000001 //< Invert pwmA +#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 //< Drive pwmA Low +#define PWM_X_GENA_ACTZERO_ONE 0x00000003 //< Drive pwmA High + +/** + * Defines for the bit fields in the PWM_O_X_GENB register. + */ +#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 //< Action for Comparator B Down +#define PWM_X_GENB_ACTCMPBD_NONE 0x00000000 //< Do nothing +#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 //< Invert pwmB +#define PWM_X_GENB_ACTCMPBD_ZERO 0x00000800 //< Drive pwmB Low +#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 //< Drive pwmB High +#define PWM_X_GENB_ACTCMPBU_M 0x00000300 //< Action for Comparator B Up +#define PWM_X_GENB_ACTCMPBU_NONE 0x00000000 //< Do nothing +#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 //< Invert pwmB +#define PWM_X_GENB_ACTCMPBU_ZERO 0x00000200 //< Drive pwmB Low +#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 //< Drive pwmB High +#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 //< Action for Comparator A Down +#define PWM_X_GENB_ACTCMPAD_NONE 0x00000000 //< Do nothing +#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 //< Invert pwmB +#define PWM_X_GENB_ACTCMPAD_ZERO 0x00000080 //< Drive pwmB Low +#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 //< Drive pwmB High +#define PWM_X_GENB_ACTCMPAU_M 0x00000030 //< Action for Comparator A Up +#define PWM_X_GENB_ACTCMPAU_NONE 0x00000000 //< Do nothing +#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 //< Invert pwmB +#define PWM_X_GENB_ACTCMPAU_ZERO 0x00000020 //< Drive pwmB Low +#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 //< Drive pwmB High +#define PWM_X_GENB_ACTLOAD_M 0x0000000C //< Action for Counter=LOAD +#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 //< Do nothing +#define PWM_X_GENB_ACTLOAD_INV 0x00000004 //< Invert pwmB +#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 //< Drive pwmB Low +#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C //< Drive pwmB High +#define PWM_X_GENB_ACTZERO_M 0x00000003 //< Action for Counter=0 +#define PWM_X_GENB_ACTZERO_NONE 0x00000000 //< Do nothing +#define PWM_X_GENB_ACTZERO_INV 0x00000001 //< Invert pwmB +#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 //< Drive pwmB Low +#define PWM_X_GENB_ACTZERO_ONE 0x00000003 //< Drive pwmB High + +/** + * Defines for the bit fields in the PWM_O_X_DBCTL register. + */ +#define PWM_X_DBCTL_ENABLE 0x00000001 //< Dead-Band Generator Enable +/** + * Defines for the bit fields in the PWM_O_X_DBRISE register. + */ +#define PWM_X_DBRISE_DELAY_M 0x00000FFF //< Dead-Band Rise Delay +#define PWM_X_DBRISE_DELAY_S 0 + +/** + * Defines for the bit fields in the PWM_O_X_DBFALL register. + */ +#define PWM_X_DBFALL_DELAY_M 0x00000FFF //< Dead-Band Fall Delay +#define PWM_X_DBFALL_DELAY_S 0 + +/** + * Defines for the bit fields in the PWM_O_X_FLTSRC0 register. + */ +#define PWM_X_FLTSRC0_FAULT3 0x00000008 //< Fault3 Input +#define PWM_X_FLTSRC0_FAULT2 0x00000004 //< Fault2 Input +#define PWM_X_FLTSRC0_FAULT1 0x00000002 //< Fault1 Input +#define PWM_X_FLTSRC0_FAULT0 0x00000001 //< Fault0 Input + +/** + * The following are defines for the bit fields in the PWM_O_X_FLTSRC1 register. + */ +#define PWM_X_FLTSRC1_DCMP7 0x00000080 //< Digital Comparator 7 +#define PWM_X_FLTSRC1_DCMP6 0x00000040 //< Digital Comparator 6 +#define PWM_X_FLTSRC1_DCMP5 0x00000020 //< Digital Comparator 5 +#define PWM_X_FLTSRC1_DCMP4 0x00000010 //< Digital Comparator 4 +#define PWM_X_FLTSRC1_DCMP3 0x00000008 //< Digital Comparator 3 +#define PWM_X_FLTSRC1_DCMP2 0x00000004 //< Digital Comparator 2 +#define PWM_X_FLTSRC1_DCMP1 0x00000002 //< Digital Comparator 1 +#define PWM_X_FLTSRC1_DCMP0 0x00000001 //< Digital Comparator 0 + +/** + * Defines for the bit fields in the PWM_O_X_MINFLTPER register. + */ +#define PWM_X_MINFLTPER_M 0x0000FFFF //< Minimum Fault Period +#define PWM_X_MINFLTPER_S 0 + +/** + * Defines for the bit fields in the PWM_O_X_FLTSEN register. + */ +#define PWM_X_FLTSEN_FAULT3 0x00000008 //< Fault3 Sense +#define PWM_X_FLTSEN_FAULT2 0x00000004 //< Fault2 Sense +#define PWM_X_FLTSEN_FAULT1 0x00000002 //< Fault1 Sense +#define PWM_X_FLTSEN_FAULT0 0x00000001 //< Fault0 Sense + +/** + * Defines for the bit fields in the PWM_O_X_FLTSTAT0 register. + */ +#define PWM_X_FLTSTAT0_FAULT3 0x00000008 //< Fault Input 3 +#define PWM_X_FLTSTAT0_FAULT2 0x00000004 //< Fault Input 2 +#define PWM_X_FLTSTAT0_FAULT1 0x00000002 //< Fault Input 1 +#define PWM_X_FLTSTAT0_FAULT0 0x00000001 //< Fault Input 0 + +/** + * Defines for the bit fields in the PWM_O_X_FLTSTAT1 register. + */ +#define PWM_X_FLTSTAT1_DCMP7 0x00000080 //< Digital Comparator 7 Trigger +#define PWM_X_FLTSTAT1_DCMP6 0x00000040 //< Digital Comparator 6 Trigger +#define PWM_X_FLTSTAT1_DCMP5 0x00000020 //< Digital Comparator 5 Trigger +#define PWM_X_FLTSTAT1_DCMP4 0x00000010 //< Digital Comparator 4 Trigger +#define PWM_X_FLTSTAT1_DCMP3 0x00000008 //< Digital Comparator 3 Trigger +#define PWM_X_FLTSTAT1_DCMP2 0x00000004 //< Digital Comparator 2 Trigger +#define PWM_X_FLTSTAT1_DCMP1 0x00000002 //< Digital Comparator 1 Trigger +#define PWM_X_FLTSTAT1_DCMP0 0x00000001 //< Digital Comparator 0 Trigger + +/** + * Defines for the PWM Generator standard offsets. + */ +#define PWM_O_X_CTL (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< Gen Control Reg +#define PWM_O_X_INTEN (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< Gen Int/Trig Enable Reg +#define PWM_O_X_RIS (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< Gen Raw Int Status Reg +#define PWM_O_X_ISC (*((reg32_t *)(PWMC_BASE + 0x0000000C))) //< Gen Int Status Reg +#define PWM_O_X_LOAD (*((reg32_t *)(PWMC_BASE + 0x00000010))) //< Gen Load Reg +#define PWM_O_X_COUNT (*((reg32_t *)(PWMC_BASE + 0x00000014))) //< Gen Counter Reg +#define PWM_O_X_CMPA (*((reg32_t *)(PWMC_BASE + 0x00000018))) //< Gen Compare A Reg +#define PWM_O_X_CMPB (*((reg32_t *)(PWMC_BASE + 0x0000001C))) //< Gen Compare B Reg +#define PWM_O_X_GENA (*((reg32_t *)(PWMC_BASE + 0x00000020))) //< Gen Generator A Ctrl Reg +#define PWM_O_X_GENB (*((reg32_t *)(PWMC_BASE + 0x00000024))) //< Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL (*((reg32_t *)(PWMC_BASE + 0x00000028))) //< Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE (*((reg32_t *)(PWMC_BASE + 0x0000002C))) //< Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL (*((reg32_t *)(PWMC_BASE + 0x00000030))) //< Gen DB Falling Edge Delay Reg +#define PWM_O_X_FLTSRC0 (*((reg32_t *)(PWMC_BASE + 0x00000034))) //< Fault pin, comparator condition +#define PWM_O_X_FLTSRC1 (*((reg32_t *)(PWMC_BASE + 0x00000038))) //< Digital comparator condition +#define PWM_O_X_MINFLTPER (*((reg32_t *)(PWMC_BASE + 0x0000003C))) //< Fault minimum period extension +#define PWM_GEN_0_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000040))) //< PWM0 base +#define PWM_GEN_1_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000080))) //< PWM1 base +#define PWM_GEN_2_OFFSET (*((reg32_t *)(PWMC_BASE + 0x000000C0))) //< PWM2 base +#define PWM_GEN_3_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000100))) //< PWM3 base + +/** + * Defines for the PWM Generator extended offsets. + */ +#define PWM_O_X_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000000))) //< Fault logic sense +#define PWM_O_X_FLTSTAT0 (*((reg32_t *)(PWMC_BASE + 0x00000004))) //< Pin and comparator status +#define PWM_O_X_FLTSTAT1 (*((reg32_t *)(PWMC_BASE + 0x00000008))) //< Digital comparator status +#define PWM_EXT_0_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000800))) //< PWM0 extended base +#define PWM_EXT_1_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000880))) //< PWM1 extended base +#define PWM_EXT_2_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000900))) //< PWM2 extended base +#define PWM_EXT_3_OFFSET (*((reg32_t *)(PWMC_BASE + 0x00000980))) //< PWM3 extended base + +#endif /* LM3S_PWM_H */ diff --git a/bertos/cpu/cortex-m3/io/stm32_adc.h b/bertos/cpu/cortex-m3/io/stm32_adc.h index a3d4d2ed..d81843ee 100644 --- a/bertos/cpu/cortex-m3/io/stm32_adc.h +++ b/bertos/cpu/cortex-m3/io/stm32_adc.h @@ -132,89 +132,89 @@ #define ADC_FLAG_STRT ((uint8_t)0X10) -/* ADC ADON mask */ -#define CR2_ADON_SET ((uint32_t)0x00000001) -#define CR2_ADON_RESET ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CR2_DMA_SET ((uint16_t)0x0100) -#define CR2_DMA_RESET ((uint16_t)0xFEFF) - -/* ADC RSTCAL mask */ -#define CR2_RSTCAL_SET ((uint16_t)0x0008) - -/* ADC CAL mask */ -#define CR2_CAL_SET ((uint16_t)0x0004) - -/* ADC SWSTRT mask */ -#define CR2_SWSTRT_SET ((uint32_t)0x00400000) - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CR1_DISCEN_SET ((uint32_t)0x00000800) -#define CR1_DISCEN_RESET ((uint32_t)0xFFFFF7FF) - -/* ADC EXTTRIG mask */ -#define CR2_EXTTRIG_SET ((uint32_t)0x00100000) -#define CR2_EXTTRIG_RESET ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CR2_EXTTRIG_SWSTRT_SET ((uint32_t)0x00500000) -#define CR2_EXTTRIG_SWSTRT_RESET ((uint32_t)0xFFAFFFFF) - -/* ADC JAUTO mask */ -#define CR1_JAUTO_SET ((uint32_t)0x00000400) -#define CR1_JAUTO_RESET ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CR1_JDISCEN_SET ((uint32_t)0x00001000) -#define CR1_JDISCEN_RESET ((uint32_t)0xFFFFEFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_RESET ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CR2_JEXTTRIG_SET ((uint32_t)0x00008000) -#define CR2_JEXTTRIG_RESET ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTRT mask */ -#define CR2_JSWSTRT_SET ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CR2_JEXTTRIG_JSWSTRT_SET ((uint32_t)0x00208000) -#define CR2_JEXTTRIG_JSWSTRT_RESET ((uint32_t)0xFFDF7FFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) - -/* ADC SQx mask */ -#define SQR3_SQ_MASK ((uint8_t)0x1F) -#define SQR2_SQ_MASK ((uint8_t)0x1F) +/* ADC ADON mask */ +#define CR2_ADON_SET ((uint32_t)0x00000001) +#define CR2_ADON_RESET ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_SET ((uint16_t)0x0100) +#define CR2_DMA_RESET ((uint16_t)0xFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_SET ((uint16_t)0x0008) + +/* ADC CAL mask */ +#define CR2_CAL_SET ((uint16_t)0x0004) + +/* ADC SWSTRT mask */ +#define CR2_SWSTRT_SET ((uint32_t)0x00400000) + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_SET ((uint32_t)0x00000800) +#define CR1_DISCEN_RESET ((uint32_t)0xFFFFF7FF) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_SET ((uint32_t)0x00100000) +#define CR2_EXTTRIG_RESET ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTRT_SET ((uint32_t)0x00500000) +#define CR2_EXTTRIG_SWSTRT_RESET ((uint32_t)0xFFAFFFFF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_SET ((uint32_t)0x00000400) +#define CR1_JAUTO_RESET ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_SET ((uint32_t)0x00001000) +#define CR1_JDISCEN_RESET ((uint32_t)0xFFFFEFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_RESET ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_SET ((uint32_t)0x00008000) +#define CR2_JEXTTRIG_RESET ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTRT mask */ +#define CR2_JSWSTRT_SET ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTRT_SET ((uint32_t)0x00208000) +#define CR2_JEXTTRIG_JSWSTRT_RESET ((uint32_t)0xFFDF7FFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) + +/* ADC SQx mask */ +#define SQR3_SQ_MASK ((uint8_t)0x1F) +#define SQR2_SQ_MASK ((uint8_t)0x1F) #define SQR1_SQ_MASK ((uint8_t)0x1F) #define SQR1_SQ_LEN_MASK 0xF -#define SQR1_SQ_LEN_SHIFT 20 - -/* ADC JSQx mask */ -#define JSQR_JSQ_SET ((uint8_t)0x1F) - -/* ADC JL mask */ -#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_SET ((uint8_t)0x07) -#define SMPR2_SMP_SET ((uint8_t)0x07) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF) - -/* ADC TSPD mask */ -#define CR2_TSVREFE_SET ((uint32_t)0x00800000) -#define CR2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF) - -/* ADC JDRx registers= offset */ -#define JDR_OFFSET ((uint8_t)0x28) +#define SQR1_SQ_LEN_SHIFT 20 + +/* ADC JSQx mask */ +#define JSQR_JSQ_SET ((uint8_t)0x1F) + +/* ADC JL mask */ +#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_SET ((uint8_t)0x07) +#define SMPR2_SMP_SET ((uint8_t)0x07) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF) + +/* ADC TSPD mask */ +#define CR2_TSVREFE_SET ((uint32_t)0x00800000) +#define CR2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF) + +/* ADC JDRx registers= offset */ +#define JDR_OFFSET ((uint8_t)0x28) /* ADC CR1 register */ #define CR1_EOCIE 5 @@ -268,10 +268,10 @@ #define SMPR2_CH2 6 #define SMPR2_CH1 3 #define SMPR2_CH0 0 - -/* ADC registers Masks */ -#define CR1_ADC_CLEAR_MASK ((uint32_t)0xFFF0FEFF) -#define CR2_ADC_CLEAR_MASK ((uint32_t)0xFFF1F7FD) + +/* ADC registers Masks */ +#define CR1_ADC_CLEAR_MASK ((uint32_t)0xFFF0FEFF) +#define CR2_ADC_CLEAR_MASK ((uint32_t)0xFFF1F7FD) #define SQR1_CLEAR_MASK ((uint32_t)0xFF0FFFFF) @@ -282,7 +282,7 @@ #define ADC_TEMP_CONST 25000 #define ADC_TEMP_CH 16 #define ADC_VREFINT_CH 17 - + struct stm32_adc { reg32_t SR; diff --git a/bertos/hw/hw_ntc.c b/bertos/hw/hw_ntc.c index d279dbe2..2509239d 100644 --- a/bertos/hw/hw_ntc.c +++ b/bertos/hw/hw_ntc.c @@ -1,45 +1,45 @@ -/** - * \file - * - * - * \brief NTC hardware-specific definition - * - * \author Lorenzo Berni - * - */ - -#include -#include "hw/ntc_map.h" - -const res_t NTC_RSER[NTC_CNT]; -const res_t NTC_RPAR[NTC_CNT]; -const amp_t NTC_AMP[NTC_CNT]; -const NtcHwInfo* NTC_INFO[NTC_CNT]; +/** + * \file + * + * + * \brief NTC hardware-specific definition + * + * \author Lorenzo Berni + * + */ + +#include +#include "hw/ntc_map.h" + +const res_t NTC_RSER[NTC_CNT]; +const res_t NTC_RPAR[NTC_CNT]; +const amp_t NTC_AMP[NTC_CNT]; +const NtcHwInfo* NTC_INFO[NTC_CNT]; diff --git a/bertos/kern/kfile.c b/bertos/kern/kfile.c index e8691163..5bafb52b 100644 --- a/bertos/kern/kfile.c +++ b/bertos/kern/kfile.c @@ -1,5 +1,4 @@ // notest: all #warning "This file is deprecated, use the new io/kfile.c" -#error analc #include diff --git a/bertos/kern/kfile.h b/bertos/kern/kfile.h index 24e07dd5..806d19ea 100644 --- a/bertos/kern/kfile.h +++ b/bertos/kern/kfile.h @@ -1,3 +1,2 @@ #warning "This file is deprecated, include the new " -#error anal #include diff --git a/boards/lpc-p2378/hw/hw_ntc.c b/boards/lpc-p2378/hw/hw_ntc.c index d279dbe2..2509239d 100644 --- a/boards/lpc-p2378/hw/hw_ntc.c +++ b/boards/lpc-p2378/hw/hw_ntc.c @@ -1,45 +1,45 @@ -/** - * \file - * - * - * \brief NTC hardware-specific definition - * - * \author Lorenzo Berni - * - */ - -#include -#include "hw/ntc_map.h" - -const res_t NTC_RSER[NTC_CNT]; -const res_t NTC_RPAR[NTC_CNT]; -const amp_t NTC_AMP[NTC_CNT]; -const NtcHwInfo* NTC_INFO[NTC_CNT]; +/** + * \file + * + * + * \brief NTC hardware-specific definition + * + * \author Lorenzo Berni + * + */ + +#include +#include "hw/ntc_map.h" + +const res_t NTC_RSER[NTC_CNT]; +const res_t NTC_RPAR[NTC_CNT]; +const amp_t NTC_AMP[NTC_CNT]; +const NtcHwInfo* NTC_INFO[NTC_CNT]; diff --git a/boards/stm32-p103/hw/hw_ntc.c b/boards/stm32-p103/hw/hw_ntc.c index d279dbe2..2509239d 100644 --- a/boards/stm32-p103/hw/hw_ntc.c +++ b/boards/stm32-p103/hw/hw_ntc.c @@ -1,45 +1,45 @@ -/** - * \file - * - * - * \brief NTC hardware-specific definition - * - * \author Lorenzo Berni - * - */ - -#include -#include "hw/ntc_map.h" - -const res_t NTC_RSER[NTC_CNT]; -const res_t NTC_RPAR[NTC_CNT]; -const amp_t NTC_AMP[NTC_CNT]; -const NtcHwInfo* NTC_INFO[NTC_CNT]; +/** + * \file + * + * + * \brief NTC hardware-specific definition + * + * \author Lorenzo Berni + * + */ + +#include +#include "hw/ntc_map.h" + +const res_t NTC_RSER[NTC_CNT]; +const res_t NTC_RPAR[NTC_CNT]; +const amp_t NTC_AMP[NTC_CNT]; +const NtcHwInfo* NTC_INFO[NTC_CNT]; diff --git a/wizard/LoadException.py b/wizard/LoadException.py index 99b30c9f..588dcc48 100644 --- a/wizard/LoadException.py +++ b/wizard/LoadException.py @@ -1,42 +1,42 @@ -#!/usr/bin/env python -# encoding: utf-8 -# -# This file is part of BeRTOS. -# -# Bertos is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# -# As a special exception, you may use this file as part of a free software -# library without restriction. Specifically, if other files instantiate -# templates or use macros or inline functions from this file, or you compile -# this file and link it with other files to produce an executable, this -# file does not by itself cause the resulting executable to be covered by -# the GNU General Public License. This exception does not however -# invalidate any other reasons why the executable file might be covered by -# the GNU General Public License. -# -# Copyright 2008 Develer S.r.l. (http://www.develer.com/) -# -# $Id: DefineException.py 2645 2009-04-23 09:28:13Z duplo $ -# -# Author: Lorenzo Berni -# - -class ToolchainException(Exception): - def __init__(self, partial_project): - self.partial_project = partial_project - -class VersionException(Exception): - def __init__(self, partial_project): - self.partial_project = partial_project +#!/usr/bin/env python +# encoding: utf-8 +# +# This file is part of BeRTOS. +# +# Bertos is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# As a special exception, you may use this file as part of a free software +# library without restriction. Specifically, if other files instantiate +# templates or use macros or inline functions from this file, or you compile +# this file and link it with other files to produce an executable, this +# file does not by itself cause the resulting executable to be covered by +# the GNU General Public License. This exception does not however +# invalidate any other reasons why the executable file might be covered by +# the GNU General Public License. +# +# Copyright 2008 Develer S.r.l. (http://www.develer.com/) +# +# $Id: DefineException.py 2645 2009-04-23 09:28:13Z duplo $ +# +# Author: Lorenzo Berni +# + +class ToolchainException(Exception): + def __init__(self, partial_project): + self.partial_project = partial_project + +class VersionException(Exception): + def __init__(self, partial_project): + self.partial_project = partial_project diff --git a/wizard/exception_handler.py b/wizard/exception_handler.py index 9e54fa69..561d8e16 100644 --- a/wizard/exception_handler.py +++ b/wizard/exception_handler.py @@ -1,69 +1,69 @@ -#!/usr/bin/env python -# encoding: utf-8 -# -# This file is part of BeRTOS. -# -# Bertos is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# -# As a special exception, you may use this file as part of a free software -# library without restriction. Specifically, if other files instantiate -# templates or use macros or inline functions from this file, or you compile -# this file and link it with other files to produce an executable, this -# file does not by itself cause the resulting executable to be covered by -# the GNU General Public License. This exception does not however -# invalidate any other reasons why the executable file might be covered by -# the GNU General Public License. -# -# Copyright 2008 Develer S.r.l. (http://www.develer.com/) -# -# $Id: const.py 2907 2009-09-08 14:02:04Z duplo $ -# -# Author: Lorenzo Berni -# - -import sys -import os -import traceback - -from PyQt4.QtCore import * -from PyQt4.QtGui import * - -def _excepthook(exc_type, exc_value, exc_traceback): - project_dir = QApplication.instance().project.info("PROJECT_PATH") - if not project_dir: - project_dir = os.getcwd() - file_name = os.path.join(project_dir, "wizard_error.log") - if os.path.exists(file_name): - content = open(file_name, "r").read() - else: - content = "" - if not os.path.exists(os.path.dirname(file_name)): - os.makedirs(os.path.dirname(file_name)) - f = open(file_name, "w") - message = "\n".join(traceback.format_exception(exc_type, exc_value, exc_traceback)) - f.write(message) - f.write(">"*80 + "\n") - f.write(content) - f.close() - print>>sys.stderr, message - QMessageBox.critical( - None, - "Exception occurred", - "An exception is occurred. Please attach the '%s' file to the support request." %os.path.abspath(file_name), - ) - QApplication.instance().quit() - -sys.excepthook = _excepthook - +#!/usr/bin/env python +# encoding: utf-8 +# +# This file is part of BeRTOS. +# +# Bertos is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# As a special exception, you may use this file as part of a free software +# library without restriction. Specifically, if other files instantiate +# templates or use macros or inline functions from this file, or you compile +# this file and link it with other files to produce an executable, this +# file does not by itself cause the resulting executable to be covered by +# the GNU General Public License. This exception does not however +# invalidate any other reasons why the executable file might be covered by +# the GNU General Public License. +# +# Copyright 2008 Develer S.r.l. (http://www.develer.com/) +# +# $Id: const.py 2907 2009-09-08 14:02:04Z duplo $ +# +# Author: Lorenzo Berni +# + +import sys +import os +import traceback + +from PyQt4.QtCore import * +from PyQt4.QtGui import * + +def _excepthook(exc_type, exc_value, exc_traceback): + project_dir = QApplication.instance().project.info("PROJECT_PATH") + if not project_dir: + project_dir = os.getcwd() + file_name = os.path.join(project_dir, "wizard_error.log") + if os.path.exists(file_name): + content = open(file_name, "r").read() + else: + content = "" + if not os.path.exists(os.path.dirname(file_name)): + os.makedirs(os.path.dirname(file_name)) + f = open(file_name, "w") + message = "\n".join(traceback.format_exception(exc_type, exc_value, exc_traceback)) + f.write(message) + f.write(">"*80 + "\n") + f.write(content) + f.close() + print>>sys.stderr, message + QMessageBox.critical( + None, + "Exception occurred", + "An exception is occurred. Please attach the '%s' file to the support request." %os.path.abspath(file_name), + ) + QApplication.instance().quit() + +sys.excepthook = _excepthook + diff --git a/wizard/winreg_importer.py b/wizard/winreg_importer.py index b7981cc4..f1eed56a 100644 --- a/wizard/winreg_importer.py +++ b/wizard/winreg_importer.py @@ -1,87 +1,87 @@ -#!/usr/bin/env python -# encoding: utf-8 -# -# This file is part of BeRTOS. -# -# Bertos is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# -# As a special exception, you may use this file as part of a free software -# library without restriction. Specifically, if other files instantiate -# templates or use macros or inline functions from this file, or you compile -# this file and link it with other files to produce an executable, this -# file does not by itself cause the resulting executable to be covered by -# the GNU General Public License. This exception does not however -# invalidate any other reasons why the executable file might be covered by -# the GNU General Public License. -# -# Copyright 2008 Develer S.r.l. (http://www.develer.com/) -# -# $Id: qvariant_converter.py 2506 2009-04-15 08:29:07Z duplo $ -# -# Author: Lorenzo Berni -# - -from _winreg import * - -# Open the registry keys. When the keys don't exist it do nothing -try: - DIR_KEY = OpenKey(HKEY_LOCAL_MACHINE, "SOFTWARE\Develer\BeRTOS SDK\BeRTOS Dirs") -except WindowsError: - DIR_KEY = None - -try: - TOOLCHAIN_KEY = OpenKey(HKEY_LOCAL_MACHINE, "SOFTWARE\Develer\BeRTOS SDK\Toolchain Executables") -except WindowsError: - TOOLCHAIN_KEY = None - -try: - CLI_KEY = OpenKey(HKEY_LOCAL_MACHINE, "SOFTWARE\Develer\BeRTOS SDK\Ide Command Lines") -except WindowsError: - CLI_KEY = None - -def getBertosDirs(): - """ - Returns the path of the BeRTOS versions installed by the BeRTOS SDK installer. - """ - return getFromRegistry(DIR_KEY).values() - -def getBertosToolchains(): - """ - Returns the path of the executables of the toolchains installed by the BeRTOS - SDK installer. - """ - return getFromRegistry(TOOLCHAIN_KEY).values() - -def getCommandLines(): - """ - Returns the command lines to launch in order to open the selected IDE. - """ - return getFromRegistry(CLI_KEY) - -def getFromRegistry(key): - """ - Returns the value of all the named values of the given key. - """ - index = 0 - items = {} - if key: - while True: - try: - item = EnumValue(key, index) - items[item[0]] = item[1] - index += 1 - except WindowsError: - break +#!/usr/bin/env python +# encoding: utf-8 +# +# This file is part of BeRTOS. +# +# Bertos is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# As a special exception, you may use this file as part of a free software +# library without restriction. Specifically, if other files instantiate +# templates or use macros or inline functions from this file, or you compile +# this file and link it with other files to produce an executable, this +# file does not by itself cause the resulting executable to be covered by +# the GNU General Public License. This exception does not however +# invalidate any other reasons why the executable file might be covered by +# the GNU General Public License. +# +# Copyright 2008 Develer S.r.l. (http://www.develer.com/) +# +# $Id: qvariant_converter.py 2506 2009-04-15 08:29:07Z duplo $ +# +# Author: Lorenzo Berni +# + +from _winreg import * + +# Open the registry keys. When the keys don't exist it do nothing +try: + DIR_KEY = OpenKey(HKEY_LOCAL_MACHINE, "SOFTWARE\Develer\BeRTOS SDK\BeRTOS Dirs") +except WindowsError: + DIR_KEY = None + +try: + TOOLCHAIN_KEY = OpenKey(HKEY_LOCAL_MACHINE, "SOFTWARE\Develer\BeRTOS SDK\Toolchain Executables") +except WindowsError: + TOOLCHAIN_KEY = None + +try: + CLI_KEY = OpenKey(HKEY_LOCAL_MACHINE, "SOFTWARE\Develer\BeRTOS SDK\Ide Command Lines") +except WindowsError: + CLI_KEY = None + +def getBertosDirs(): + """ + Returns the path of the BeRTOS versions installed by the BeRTOS SDK installer. + """ + return getFromRegistry(DIR_KEY).values() + +def getBertosToolchains(): + """ + Returns the path of the executables of the toolchains installed by the BeRTOS + SDK installer. + """ + return getFromRegistry(TOOLCHAIN_KEY).values() + +def getCommandLines(): + """ + Returns the command lines to launch in order to open the selected IDE. + """ + return getFromRegistry(CLI_KEY) + +def getFromRegistry(key): + """ + Returns the value of all the named values of the given key. + """ + index = 0 + items = {} + if key: + while True: + try: + item = EnumValue(key, index) + items[item[0]] = item[1] + index += 1 + except WindowsError: + break return items \ No newline at end of file