From 214a3703cc92b423088cf27c4fc637e288d38e17 Mon Sep 17 00:00:00 2001 From: batt Date: Thu, 23 Oct 2008 17:05:54 +0000 Subject: [PATCH] Merged from external project: ********** r22536 | batt | 2008-10-23 19:00:53 +0200(gio, 23 ott 2008) | 1 line Reformat; set default SPI serial to SPI0. ********** git-svn-id: https://src.develer.com/svnoss/bertos/trunk@1898 38d2e660-2303-0410-9eaa-f027e97ec537 --- bertos/cfg/cfg_ser.h | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h index d1647006..8fc59489 100644 --- a/bertos/cfg/cfg_ser.h +++ b/bertos/cfg/cfg_ser.h @@ -35,7 +35,7 @@ * \version $Id$ * * \author Daniele Basile - */ + */ #ifndef CFG_SER_H #define CFG_SER_H @@ -46,55 +46,55 @@ * Edit these define for your project. */ /// Serial settings -#define CONFIG_SER_PORT 0 -#define CONFIG_SER_BAUDRATE 115200 +#define CONFIG_SER_PORT 0 +#define CONFIG_SER_BAUDRATE 115200 /// Spi settings -#define CONFIG_SPI_PORT 0 -#define CONFIG_SPI_BAUDRATE 5000000UL +#define CONFIG_SPI_PORT SER_SPI0 +#define CONFIG_SPI_BAUDRATE 5000000UL -/// [bytes] Size of the outbound FIFO buffer for port 0. +/// [bytes] Size of the outbound FIFO buffer for port 0. #define CONFIG_UART0_TXBUFSIZE 32 -/// [bytes] Size of the inbound FIFO buffer for port 0. +/// [bytes] Size of the inbound FIFO buffer for port 0. #define CONFIG_UART0_RXBUFSIZE 32 -/// [bytes] Size of the outbound FIFO buffer for port 1. +/// [bytes] Size of the outbound FIFO buffer for port 1. #define CONFIG_UART1_TXBUFSIZE 32 -/// [bytes] Size of the inbound FIFO buffer for port 1. +/// [bytes] Size of the inbound FIFO buffer for port 1. #define CONFIG_UART1_RXBUFSIZE 32 -/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only) +/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only) #define CONFIG_SPI_TXBUFSIZE 32 -/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only) +/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only) #define CONFIG_SPI_RXBUFSIZE 32 -/// [bytes] Size of the outbound FIFO buffer for SPI port 0. +/// [bytes] Size of the outbound FIFO buffer for SPI port 0. #define CONFIG_SPI0_TXBUFSIZE 32 -/// [bytes] Size of the inbound FIFO buffer for SPI port 0. +/// [bytes] Size of the inbound FIFO buffer for SPI port 0. #define CONFIG_SPI0_RXBUFSIZE 32 -/// [bytes] Size of the outbound FIFO buffer for SPI port 1. +/// [bytes] Size of the outbound FIFO buffer for SPI port 1. #define CONFIG_SPI1_TXBUFSIZE 32 -/// [bytes] Size of the inbound FIFO buffer for SPI port 1. +/// [bytes] Size of the inbound FIFO buffer for SPI port 1. #define CONFIG_SPI1_RXBUFSIZE 32 -/// SPI data order (AVR only). +/// SPI data order (AVR only). #define CONFIG_SPI_DATA_ORDER SER_MSB_FIRST -/// SPI clock division factor (AVR only). +/// SPI clock division factor (AVR only). #define CONFIG_SPI_CLOCK_DIV 16 -/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only). +/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only). #define CONFIG_SPI_CLOCK_POL 0 -/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only). +/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only). #define CONFIG_SPI_CLOCK_PHASE 0 /// Default transmit timeout (ms). Set to -1 to disable timeout support. @@ -103,7 +103,7 @@ /// Default receive timeout (ms). Set to -1 to disable timeout support. #define CONFIG_SER_RXTIMEOUT -1 -/// Use RTS/CTS handshake +/// Use RTS/CTS handshake #define CONFIG_SER_HWHANDSHAKE 0 /// Default baud rate (set to 0 to disable). @@ -112,7 +112,7 @@ /// Enable ser_gets() and ser_gets_echo(). #define CONFIG_SER_GETS 0 -/// Enable second serial port in emulator. +/// Enable second serial port in emulator. #define CONFIG_EMUL_UART1 0 /** -- 2.25.1