X-Git-Url: https://codewiz.org/gitweb?p=rmslog.git;a=blobdiff_plain;f=rmslog%2Fcfg%2Fcfg_ser.h;h=b2524ccbeb1818fe0bbee76935216b20f6d70f57;hp=b5ce58ae29950655e77416ec649b8ff30afd1c15;hb=953c42c0ea7e1c27793ba465db862e2fbc7ffdf9;hpb=fb32318668a726a7da4c9fe27a9770bf168af08d

diff --git a/rmslog/cfg/cfg_ser.h b/rmslog/cfg/cfg_ser.h
index b5ce58a..b2524cc 100644
--- a/rmslog/cfg/cfg_ser.h
+++ b/rmslog/cfg/cfg_ser.h
@@ -49,7 +49,7 @@
  * $WIZ$ type = "int"
  * $WIZ$ min = 2
  */
-#define CONFIG_UART0_TXBUFSIZE  32
+#define CONFIG_UART0_TXBUFSIZE  16
 
 /**
  * Size of the inbound FIFO buffer for port 0 [bytes].
@@ -58,62 +58,13 @@
  */
 #define CONFIG_UART0_RXBUFSIZE  512
 
-/**
- * Size of the outbound FIFO buffer for port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
- */
-#define CONFIG_UART1_TXBUFSIZE  32
-
-/**
- * Size of the inbound FIFO buffer for port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
- */
-#define CONFIG_UART1_RXBUFSIZE  32
-
-/**
- * Size of the outbound FIFO buffer for port 2 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2"
- */
-#define CONFIG_UART2_TXBUFSIZE  32
-
-/**
- * Size of the inbound FIFO buffer for port 2 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2"
- */
-#define CONFIG_UART2_RXBUFSIZE  32
-
-/**
- * Size of the outbound FIFO buffer for port 3 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lpc2"
- */
-#define CONFIG_UART3_TXBUFSIZE  32
-
-/**
- * Size of the inbound FIFO buffer for port 3 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lpc2"
- */
-#define CONFIG_UART3_RXBUFSIZE  32
-
-
 /**
  * Size of the outbound FIFO buffer for SPI port [bytes].
  * $WIZ$ type = "int"
  * $WIZ$ min = 2
  * $WIZ$ supports = "avr"
  */
-#define CONFIG_SPI_TXBUFSIZE    32
+#define CONFIG_SPI_TXBUFSIZE    0
 
 /**
  * Size of the inbound FIFO buffer for SPI port [bytes].
@@ -121,39 +72,7 @@
  * $WIZ$ min = 2
  * $WIZ$ supports = "avr"
  */
-#define CONFIG_SPI_RXBUFSIZE    32
-
-/**
- * Size of the outbound FIFO buffer for SPI port 0 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI0_TXBUFSIZE	32
-
-/**
- * Size of the inbound FIFO buffer for SPI port 0 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI0_RXBUFSIZE	32
-
-/**
- * Size of the outbound FIFO buffer for SPI port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI1_TXBUFSIZE	32
-
-/**
- * Size of the inbound FIFO buffer for SPI port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI1_RXBUFSIZE	32
+#define CONFIG_SPI_RXBUFSIZE    0
 
 /**
  * SPI data order.