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29 * Copyright 2003, 2004, 2005 Develer S.r.l. (http://www.develer.com/)
33 * \brief Driver for the AVR ATMega TWI (implementation)
35 * \author Stefano Fedrigo <aleph@develer.com>
36 * \author Bernie Innocenti <bernie@codewiz.org>
39 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
41 #include "cfg/cfg_i2c.h"
43 #define LOG_LEVEL I2C_LOG_LEVEL
44 #define LOG_FORMAT I2C_LOG_FORMAT
48 #include <cfg/debug.h>
49 #include <cfg/macros.h> // BV()
50 #include <cfg/module.h>
52 #include <cpu/detect.h>
54 #include <drv/timer.h>
57 #include <cpu/power.h>
59 #include <compat/twi.h>
62 /* Wait for TWINT flag set: bus is ready */
63 #define WAIT_TWI_READY do {} while (!(TWCR & BV(TWINT)))
66 * Send START condition on the bus.
68 * \return true on success, false otherwise.
70 static bool i2c_builtin_start(void)
72 TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
75 if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
78 LOG_ERR("!TW_(REP)START: %x\n", TWSR);
84 * Send START condition and select slave for write.
85 * \c id is the device id comprehensive of address left shifted by 1.
86 * The LSB of \c id is ignored and reset to 0 for write operation.
88 * \return true on success, false otherwise.
90 bool i2c_builtin_start_w(uint8_t id)
93 * Loop on the select write sequence: when the eeprom is busy
94 * writing previously sent data it will reply to the SLA_W
95 * control byte with a NACK. In this case, we must
96 * keep trying until the eeprom responds with an ACK.
98 ticks_t start = timer_clock();
99 while (i2c_builtin_start())
101 TWDR = id & ~I2C_READBIT;
102 TWCR = BV(TWINT) | BV(TWEN);
105 if (TW_STATUS == TW_MT_SLA_ACK)
107 else if (TW_STATUS != TW_MT_SLA_NACK)
109 LOG_ERR("!TW_MT_SLA_(N)ACK: %x\n", TWSR);
112 else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
114 LOG_ERR("Timeout on TWI_MT_START\n");
124 * Send START condition and select slave for read.
125 * \c id is the device id comprehensive of address left shifted by 1.
126 * The LSB of \c id is ignored and set to 1 for read operation.
128 * \return true on success, false otherwise.
130 bool i2c_builtin_start_r(uint8_t id)
132 if (i2c_builtin_start())
134 TWDR = id | I2C_READBIT;
135 TWCR = BV(TWINT) | BV(TWEN);
138 if (TW_STATUS == TW_MR_SLA_ACK)
141 LOG_ERR("!TW_MR_SLA_ACK: %x\n", TWSR);
149 * Send STOP condition.
151 void i2c_builtin_stop(void)
153 TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
158 * Put a single byte in master transmitter mode
159 * to the selected slave device through the TWI bus.
161 * \return true on success, false on error.
163 bool i2c_builtin_put(const uint8_t data)
166 TWCR = BV(TWINT) | BV(TWEN);
168 if (TW_STATUS != TW_MT_DATA_ACK)
170 LOG_ERR("!TW_MT_DATA_ACK: %x\n", TWSR);
177 * Get 1 byte from slave in master transmitter mode
178 * to the selected slave device through the TWI bus.
179 * If \a ack is true issue a ACK after getting the byte,
180 * otherwise a NACK is issued.
182 * \return the byte read if ok, EOF on errors.
184 int i2c_builtin_get(bool ack)
186 TWCR = BV(TWINT) | BV(TWEN) | (ack ? BV(TWEA) : 0);
191 if (TW_STATUS != TW_MR_DATA_ACK)
193 LOG_ERR("!TW_MR_DATA_ACK: %x\n", TWSR);
199 if (TW_STATUS != TW_MR_DATA_NACK)
201 LOG_ERR("!TW_MR_DATA_NACK: %x\n", TWSR);
206 /* avoid sign extension */
207 return (int)(uint8_t)TWDR;
214 * Initialize TWI module.
216 void i2c_builtin_init(void)
220 * This is pretty useless according to AVR's datasheet,
221 * but it helps us driving the TWI data lines on boards
222 * where the bus pull-up resistors are missing. This is
223 * probably due to some unwanted interaction between the
224 * port pin and the TWI lines.
226 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
227 PORTD |= BV(PD0) | BV(PD1);
228 DDRD |= BV(PD0) | BV(PD1);
229 #elif CPU_AVR_ATMEGA8
230 PORTC |= BV(PC4) | BV(PC5);
231 DDRC |= BV(PC4) | BV(PC5);
232 #elif CPU_AVR_ATMEGA32
233 PORTC |= BV(PC1) | BV(PC0);
234 DDRC |= BV(PC1) | BV(PC0);
236 #error Unsupported architecture
241 * F = CPU_FREQ / (16 + 2*TWBR * 4^TWPS)
243 #ifndef CONFIG_I2C_FREQ
244 #warning Using default value of 300000L for CONFIG_I2C_FREQ
245 #define CONFIG_I2C_FREQ 300000L /* ~300 kHz */
247 #define TWI_PRESC 1 /* 4 ^ TWPS */
249 TWBR = (CPU_FREQ / (2 * CONFIG_I2C_FREQ * TWI_PRESC)) - (8 / TWI_PRESC);
266 /* Wait for TWINT flag set: bus is ready */
267 #define WAIT_READY() \
269 while (!(TWCR & BV(TWINT))) \
274 * Send START condition on the bus.
276 INLINE bool i2c_hw_start(void)
278 TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
281 if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
288 * Send STOP condition.
290 INLINE void i2c_hw_stop(void)
292 TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
295 static void i2c_avr_start(I2c *i2c, uint16_t slave_addr)
298 * Loop on the select write sequence: when the eeprom is busy
299 * writing previously sent data it will reply to the SLA_W
300 * control byte with a NACK. In this case, we must
301 * keep trying until the slave responds with an ACK.
303 ticks_t start = timer_clock();
304 while (i2c_hw_start())
307 uint8_t sla_nack = 0;
308 if (I2C_TEST_START(i2c->flags) == I2C_START_W)
310 TWDR = slave_addr & ~I2C_READBIT;
311 sla_ack = TW_MT_SLA_ACK;
312 sla_nack = TW_MT_SLA_NACK;
316 TWDR = slave_addr | I2C_READBIT;
317 sla_ack = TW_MR_SLA_ACK;
318 sla_nack = TW_MR_SLA_NACK;
321 TWCR = BV(TWINT) | BV(TWEN);
324 if (TW_STATUS == sla_ack)
326 else if (TW_STATUS != sla_nack)
328 LOG_ERR("Start addr NACK[%x]\n", TWSR);
329 i2c->errors |= I2C_NO_ACK;
333 else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
335 LOG_ERR("Start timeout\n");
336 i2c->errors |= I2C_START_TIMEOUT;
342 LOG_ERR("I2c error\n");
343 i2c->errors |= I2C_ERR;
347 static void i2c_avr_putc(I2c *i2c, const uint8_t data)
351 TWCR = BV(TWINT) | BV(TWEN);
354 if (TW_STATUS != TW_MT_DATA_ACK)
356 LOG_ERR("Data nack[%x]\n", TWSR);
357 i2c->errors |= I2C_DATA_NACK;
361 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
365 static uint8_t i2c_avr_getc(I2c *i2c)
367 uint8_t data_flag = 0;
368 if (i2c->xfer_size == 1)
370 TWCR = BV(TWINT) | BV(TWEN);
371 data_flag = TW_MR_DATA_NACK;
375 TWCR = BV(TWINT) | BV(TWEN) | BV(TWEA);
376 data_flag = TW_MR_DATA_ACK;
381 if (TW_STATUS != TW_MR_DATA_ACK)
383 LOG_ERR("Data nack[%x]\n", TWSR);
384 i2c->errors |= I2C_DATA_NACK;
392 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
399 static const I2cVT i2c_avr_vt =
401 .start = i2c_avr_start,
402 .getc = i2c_avr_getc,
403 .putc = i2c_avr_putc,
404 .write = i2c_genericWrite,
405 .read = i2c_genericRead,
408 struct I2cHardware i2c_avr_hw[] =
415 * Initialize I2C module.
417 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
419 i2c->hw = &i2c_avr_hw[dev];
420 i2c->vt = &i2c_avr_vt;
424 * This is pretty useless according to AVR's datasheet,
425 * but it helps us driving the TWI data lines on boards
426 * where the bus pull-up resistors are missing. This is
427 * probably due to some unwanted interaction between the
428 * port pin and the TWI lines.
430 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
431 PORTD |= BV(PD0) | BV(PD1);
432 DDRD |= BV(PD0) | BV(PD1);
433 #elif CPU_AVR_ATMEGA8
434 PORTC |= BV(PC4) | BV(PC5);
435 DDRC |= BV(PC4) | BV(PC5);
436 #elif CPU_AVR_ATMEGA32
437 PORTC |= BV(PC1) | BV(PC0);
438 DDRC |= BV(PC1) | BV(PC0);
440 #error Unsupported architecture
445 * F = CPU_FREQ / (16 + 2*TWBR * 4^TWPS)
448 #define TWI_PRESC 1 /* 4 ^ TWPS */
450 TWBR = (CPU_FREQ / (2 * clock * TWI_PRESC)) - (8 / TWI_PRESC);