4 * This file is part of BeRTOS.
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Driver for the LM3S I2C (implementation)
37 #include "cfg/cfg_i2c.h"
39 #define LOG_LEVEL I2C_LOG_LEVEL
40 #define LOG_FORMAT I2C_LOG_FORMAT
44 #include <cfg/debug.h>
45 #include <cfg/macros.h> // BV()
46 #include <cfg/module.h>
48 #include <cpu/detect.h>
50 #include <cpu/types.h>
51 #include <cpu/power.h>
55 #include <drv/timer.h>
57 #include <drv/gpio_lm3s.h>
58 #include <drv/clock_lm3s.h>
71 #define WAIT_BUSY(base) \
73 while (HWREG(base + I2C_O_MCS) & I2C_MCS_BUSY ) \
79 * The start is not performed when we call the start function
80 * because the hardware should know the first data byte to send.
81 * Generally to perform a byte send we should write the slave address
82 * in slave address register and the first byte to send in data registry.
83 * After then we can perform the start write procedure, and send really
84 * the our data. To use common bertos i2c api the really start will be
85 * performed when the user "put" or "send" its data. These tricks are hide
86 * from the driver implementation.
88 static void i2c_lm3s_start(struct I2c *i2c, uint16_t slave_addr)
90 i2c->hw->first_xtranf = true;
92 if (I2C_TEST_START(i2c->flags) == I2C_START_W)
93 HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr & ~BV(0);
94 else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */
95 HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr | BV(0);
98 INLINE bool wait_addrAck(I2c *i2c, uint32_t mode_mask)
100 ticks_t start = timer_clock();
103 uint32_t status = HWREG(i2c->hw->base + I2C_O_MCS);
105 if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
108 if(status & I2C_MCS_ADRACK)
110 HWREG(i2c->hw->base + I2C_O_MCS) = mode_mask;
111 WAIT_BUSY(i2c->hw->base);
121 static void i2c_lm3s_putc(I2c *i2c, const uint8_t data)
123 HWREG(i2c->hw->base + I2C_O_MDR) = data;
125 if (i2c->hw->first_xtranf)
127 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
128 while( HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
130 if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
132 LOG_ERR("Start timeout\n");
133 i2c->errors |= I2C_START_TIMEOUT;
134 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
135 WAIT_BUSY(i2c->hw->base);
139 i2c->hw->first_xtranf = false;
143 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN;
144 WAIT_BUSY(i2c->hw->base);
147 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
149 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
150 WAIT_BUSY(i2c->hw->base);
154 static uint8_t i2c_lm3s_getc(I2c *i2c)
157 if (i2c->hw->first_xtranf)
160 if (i2c->xfer_size == 1)
161 start_mode = I2C_MCS_RUN | I2C_MCS_START;
163 start_mode = I2C_MCS_ACK | I2C_MCS_RUN | I2C_MCS_START;
165 HWREG(i2c->hw->base + I2C_O_MCS) = start_mode;
166 WAIT_BUSY(i2c->hw->base);
167 if (!wait_addrAck(i2c, start_mode))
169 LOG_ERR("Start timeout\n");
170 i2c->errors |= I2C_START_TIMEOUT;
171 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
172 WAIT_BUSY(i2c->hw->base);
176 data = HWREG(i2c->hw->base + I2C_O_MDR);
177 i2c->hw->first_xtranf = false;
181 if (i2c->xfer_size > 1)
182 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_ACK | I2C_MCS_RUN;
184 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN;
186 WAIT_BUSY(i2c->hw->base);
187 data = HWREG(i2c->hw->base + I2C_O_MDR);
190 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
192 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
193 WAIT_BUSY(i2c->hw->base);
200 static const I2cVT i2c_lm3s_vt =
202 .start = i2c_lm3s_start,
203 .getc = i2c_lm3s_getc,
204 .putc = i2c_lm3s_putc,
205 .write = i2c_genericWrite,
206 .read = i2c_genericRead,
209 struct I2cHardware i2c_lm3s_hw[] =
212 .base = I2C0_MASTER_BASE,
213 .sys_cntl = SYSCTL_RCGC1_I2C0,
214 .sys_gpio = SYSCTL_RCGC2_GPIOB,
215 .pin_mask = (GPIO_I2C0_SCL_PIN | GPIO_I2C0_SDA_PIN),
216 .gpio_base = GPIO_PORTB_BASE,
219 .base = I2C1_MASTER_BASE,
220 .sys_cntl = SYSCTL_RCGC1_I2C1,
221 .sys_gpio = SYSCTL_RCGC2_GPIOA,
222 .pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN),
223 .gpio_base = GPIO_PORTA_BASE,
228 * Initialize I2C module.
230 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
232 i2c->hw = &i2c_lm3s_hw[dev];
233 i2c->vt = &i2c_lm3s_vt;
235 /* Enable the peripheral clock */
236 SYSCTL_RCGC1_R |= i2c->hw->sys_cntl;
237 SYSCTL_RCGC2_R |= i2c->hw->sys_gpio;
239 /* Configure GPIO pins to work as I2C pins */
240 lm3s_gpioPinConfig(i2c->hw->gpio_base, i2c->hw->pin_mask,
241 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
243 * Note: to set correctly the i2c speed we shold before enable the i2c
244 * device and then set in master time period the correct value
247 /* Enable i2c device */
248 HWREG(i2c->hw->base + I2C_O_MCR) |= I2C_MCR_MFE;
251 * Compute the clock divider that achieves the fastest speed less than or
252 * equal to the desired speed. The numerator is biased to favor a larger
253 * clock divider so that the resulting clock is always less than or equal
254 * to the desired clock, never greater.
256 HWREG(i2c->hw->base + I2C_O_MTPR) = ((CPU_FREQ + (2 * 10 * clock) - 1) / (2 * 10 * clock)) - 1;