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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief AT91SAM3 GPIO hardware definitions.
40 * GPIO registers base addresses.
43 #define GPIO_PORTA_BASE 0x400E0E00
44 #define GPIO_PORTB_BASE 0x400E1000
45 #define GPIO_PORTC_BASE 0x400E1200
49 * GPIO register offsets.
52 #define GPIO_PER 0x00 //< PIO Enable Register
53 #define GPIO_PDR 0x04 //< PIO Disable Register
54 #define GPIO_PSR 0x08 //< PIO Status Register
55 #define GPIO_OER 0x10 //< Output Enable Register
56 #define GPIO_ODR 0x14 //< Output Disable Register
57 #define GPIO_OSR 0x18 //< Output Status Register
58 #define GPIO_IFER 0x20 //< Glitch Input Filter Enable Register
59 #define GPIO_IFDR 0x24 //< Glitch Input Filter Disable Register
60 #define GPIO_IFSR 0x28 //< Glitch Input Filter Status Register
61 #define GPIO_SODR 0x30 //< Set Output Data Register
62 #define GPIO_CODR 0x34 //< Clear Output Data Register
63 #define GPIO_ODSR 0x38 //< Output Data Status Register
64 #define GPIO_PDSR 0x3C //< Pin Data Status Register
65 #define GPIO_IER 0x40 //< Interrupt Enable Register
66 #define GPIO_IDR 0x44 //< Interrupt Disable Register
67 #define GPIO_IMR 0x48 //< Interrupt Mask Register
68 #define GPIO_ISR 0x4C //< Interrupt Status Register
69 #define GPIO_MDER 0x50 //< Multi-driver Enable Register
70 #define GPIO_MDDR 0x54 //< Multi-driver Disable Register
71 #define GPIO_MDSR 0x58 //< Multi-driver Status Register
72 #define GPIO_PUDR 0x60 //< Pull-up Disable Register
73 #define GPIO_PUER 0x64 //< Pull-up Enable Register
74 #define GPIO_PUSR 0x68 //< Pad Pull-up Status Register
75 #define GPIO_ABCDSR1 0x70 //< Peripheral Select Register 1
76 #define GPIO_ABCDSR2 0x74 //< Peripheral Select Register 2
77 #define GPIO_IFSCDR 0x80 //< Input Filter Slow Clock Disable Register
78 #define GPIO_IFSCER 0x84 //< Input Filter Slow Clock Enable Register
79 #define GPIO_IFSCSR 0x88 //< Input Filter Slow Clock Status Register
80 #define GPIO_SCDR 0x8C //< Slow Clock Divider Debouncing Register
81 #define GPIO_PPDDR 0x90 //< Pad Pull-down Disable Register
82 #define GPIO_PPDER 0x94 //< Pad Pull-down Enable Register
83 #define GPIO_PPDSR 0x98 //< Pad Pull-down Status Register
84 #define GPIO_OWER 0xA0 //< Output Write Enable
85 #define GPIO_OWDR 0xA4 //< Output Write Disable
86 #define GPIO_OWSR 0xA8 //< Output Write Status Register
87 #define GPIO_AIMER 0xB0 //< Additional Interrupt Modes Enable Register
88 #define GPIO_AIMDR 0xB4 //< Additional Interrupt Modes Disables Register
89 #define GPIO_AIMMR 0xB8 //< Additional Interrupt Modes Mask Register
90 #define GPIO_ESR 0xC0 //< Edge Select Register
91 #define GPIO_LSR 0xC4 //< Level Select Register
92 #define GPIO_ELSR 0xC8 //< Edge/Level Status Register
93 #define GPIO_FELLSR 0xD0 //< Falling Edge/Low Level Select Register
94 #define GPIO_REHLSR 0xD4 //< Rising Edge/ High Level Select Register
95 #define GPIO_FRLHSR 0xD8 //< Fall/Rise - Low/High Status Register
96 #define GPIO_LOCKSR 0xE0 //< Lock Status
97 #define GPIO_WPMR 0xE4 //< Write Protect Mode Register
98 #define GPIO_WPSR 0xE8 //< Write Protect Status Register
99 #define GPIO_SCHMITT 0x100 //< Schmitt Trigger Register
106 #ifdef CPU_CM3_AT91SAM3U
107 #define GPIO_UART0_RX_PIN BV(11)
108 #define GPIO_UART0_TX_PIN BV(12)
110 #define GPIO_UART0_RX_PIN BV(9)
111 #define GPIO_UART0_TX_PIN BV(10)
112 #define GPIO_UART1_RX_PIN BV(2)
113 #define GPIO_UART1_TX_PIN BV(3)
117 #endif /* SAM3_GPIO_H */