// \{
#define NIC_PHY_ADDR 0
-//Registry definition
+// Register bits definition
#define NIC_PHY_BMCR 0x00 // Basic mode control register.
#define NIC_PHY_BMCR_COLTEST 0x0080 // Collision test.
#define NIC_PHY_BMCR_FDUPLEX 0x0100 // Full duplex mode.
#define NIC_PHY_BMSR_ANEGCAPABLE 0x0008 // Able to do auto-negotiation
#define NIC_PHY_BMSR_LINKSTAT 0x0004 // Link status.
+#define NIC_PHY_ANLPAR_10_HDX BV(5) // 10BASE-T half duplex
+#define NIC_PHY_ANLPAR_10_FDX BV(6) // 10BASE-T full duplex
+#define NIC_PHY_ANLPAR_TX_HDX BV(7) // 100BASE-TX half duplex
+#define NIC_PHY_ANLPAR_TX_FDX BV(8) // 100BASE-TX full duplex
+
#define NIC_PHY_ID1 0x02 // PHY identifier register 1.
#define NIC_PHY_ID2 0x03 // PHY identifier register 2.
#define NIC_PHY_ANAR 0x04 // Auto negotiation advertisement register.
* See schematics for AT91SAM7X-EK evalution board.
*/
// All pins in port B
-#define PHY_TXCLK_ISOLATE_BIT 0
#define PHY_REFCLK_XT2_BIT 0
#define PHY_TXEN_BIT 1
#define PHY_TXD0_BIT 2
* See schematics for SAM3X-EK evalution board.
*/
// Port B
-#define PHY_TXCLK_ISOLATE_BIT 0
#define PHY_REFCLK_XT2_BIT 0
#define PHY_TXEN_BIT 1
#define PHY_TXD0_BIT 2
#define PHY_TXD1_BIT 3
+#define PHY_RXDV_TESTMODE_BIT 4
#define PHY_RXD0_AD0_BIT 5
#define PHY_RXD1_AD1_BIT 6
#define PHY_RXER_RXD4_RPTR_BIT 7
#define PHY_MDC_BIT 8
#define PHY_MDIO_BIT 9
-// Port C
-#define PHY_RXDV_TESTMODE_BIT 10
// Port A
#define PHY_MDINTR_BIT 5
-// Port D -- FIXME: Only on which revision?
-#define PHY_PWRDN_BIT 18
#define PHY_MII_PINS_PORTB \
BV(PHY_REFCLK_XT2_BIT) \
| BV(PHY_MDC_BIT) \
| BV(PHY_MDIO_BIT)
-#define PHY_MII_PINS_PORTC \
- BV(PHY_RXDV_TESTMODE_BIT)
-
#endif /* CPU_ARM_AT91 */
// \}