4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2009,2010,2011 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief EMAC driver for AT91SAM family with Davicom 9161A phy, interface.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
37 * \author Stefano Fedrigo <aleph@develer.com>
43 // Settings and definition for DAVICOM 9161A
45 #define NIC_PHY_ADDR 0
47 // Register bits definition
48 #define NIC_PHY_BMCR 0x00 // Basic mode control register.
49 #define NIC_PHY_BMCR_COLTEST 0x0080 // Collision test.
50 #define NIC_PHY_BMCR_FDUPLEX 0x0100 // Full duplex mode.
51 #define NIC_PHY_BMCR_ANEGSTART 0x0200 // Restart auto negotiation.
52 #define NIC_PHY_BMCR_ISOLATE 0x0400 // Isolate from MII.
53 #define NIC_PHY_BMCR_PWRDN 0x0800 // Power-down.
54 #define NIC_PHY_BMCR_ANEGENA 0x1000 // Enable auto negotiation.
55 #define NIC_PHY_BMCR_100MBPS 0x2000 // Select 100 Mbps.
56 #define NIC_PHY_BMCR_LOOPBACK 0x4000 // Enable loopback mode.
57 #define NIC_PHY_BMCR_RESET 0x8000 // Software reset.
59 #define NIC_PHY_BMSR 0x01 // Basic mode status register.
60 #define NIC_PHY_BMSR_ANCOMPL 0x0020 // Auto negotiation complete.
61 #define NIC_PHY_BMSR_ANEGCAPABLE 0x0008 // Able to do auto-negotiation
62 #define NIC_PHY_BMSR_LINKSTAT 0x0004 // Link status.
64 #define NIC_PHY_ANLPAR_10_HDX BV(5) // 10BASE-T half duplex
65 #define NIC_PHY_ANLPAR_10_FDX BV(6) // 10BASE-T full duplex
66 #define NIC_PHY_ANLPAR_TX_HDX BV(7) // 100BASE-TX half duplex
67 #define NIC_PHY_ANLPAR_TX_FDX BV(8) // 100BASE-TX full duplex
69 #define NIC_PHY_ID1 0x02 // PHY identifier register 1.
70 #define NIC_PHY_ID2 0x03 // PHY identifier register 2.
71 #define NIC_PHY_ANAR 0x04 // Auto negotiation advertisement register.
72 #define NIC_PHY_ANLPAR 0x05 // Auto negotiation link partner availability register.
73 #define NIC_PHY_ANER 0x06 // Auto negotiation expansion register.
78 * Pin definition for DAVICOM 9161A.
79 * See schematics for AT91SAM7X-EK evalution board.
82 #define PHY_REFCLK_XT2_BIT 0
83 #define PHY_TXEN_BIT 1
84 #define PHY_TXD0_BIT 2
85 #define PHY_TXD1_BIT 3
86 #define PHY_CRS_AD4_BIT 4
87 #define PHY_RXD0_AD0_BIT 5
88 #define PHY_RXD1_AD1_BIT 6
89 #define PHY_RXER_RXD4_RPTR_BIT 7
91 #define PHY_MDIO_BIT 9
92 #define PHY_TXD2_BIT 10
93 #define PHY_TXD3_BIT 11
94 #define PHY_TXER_TXD4_BIT 12
95 #define PHY_RXD2_AD2_BIT 13
96 #define PHY_RXD3_AD3_BIT 14
97 #define PHY_RXDV_TESTMODE_BIT 15
98 #define PHY_COL_RMII_BIT 16
99 #define PHY_RXCLK_10BTSER_BIT 17
100 #define PHY_PWRDN_BIT 18
101 #define PHY_MDINTR_BIT 26
103 #define PHY_MII_PINS \
104 BV(PHY_REFCLK_XT2_BIT) \
108 | BV(PHY_CRS_AD4_BIT) \
109 | BV(PHY_RXD0_AD0_BIT) \
110 | BV(PHY_RXD1_AD1_BIT) \
111 | BV(PHY_RXER_RXD4_RPTR_BIT) \
116 | BV(PHY_TXER_TXD4_BIT) \
117 | BV(PHY_RXD2_AD2_BIT) \
118 | BV(PHY_RXD3_AD3_BIT) \
119 | BV(PHY_RXDV_TESTMODE_BIT) \
120 | BV(PHY_COL_RMII_BIT) \
121 | BV(PHY_RXCLK_10BTSER_BIT)
126 * Pin definition for DAVICOM 9161A.
127 * See schematics for SAM3X-EK evalution board.
130 #define PHY_REFCLK_XT2_BIT 0
131 #define PHY_TXEN_BIT 1
132 #define PHY_TXD0_BIT 2
133 #define PHY_TXD1_BIT 3
134 #define PHY_RXDV_TESTMODE_BIT 4
135 #define PHY_RXD0_AD0_BIT 5
136 #define PHY_RXD1_AD1_BIT 6
137 #define PHY_RXER_RXD4_RPTR_BIT 7
138 #define PHY_MDC_BIT 8
139 #define PHY_MDIO_BIT 9
141 #define PHY_MDINTR_BIT 5
143 #define PHY_MII_PINS_PORTB \
144 BV(PHY_REFCLK_XT2_BIT) \
148 | BV(PHY_RXD0_AD0_BIT) \
149 | BV(PHY_RXD1_AD1_BIT) \
150 | BV(PHY_RXER_RXD4_RPTR_BIT) \
154 #endif /* CPU_ARM_AT91 */
158 #define EMAC_TX_BUFSIZ 1518 //!!! Don't change this
159 #define EMAC_TX_BUFFERS 1 //!!! Don't change this
160 #define EMAC_TX_DESCRIPTORS EMAC_TX_BUFFERS
162 #define EMAC_RX_BUFFERS 32 //!!! Don't change this
163 #define EMAC_RX_BUFSIZ 128 //!!! Don't change this
164 #define EMAC_RX_DESCRIPTORS EMAC_RX_BUFFERS
166 // Flag to manage local tx buffer
167 #define TXS_USED 0x80000000 //Used buffer.
168 #define TXS_WRAP 0x40000000 //Last descriptor.
169 #define TXS_ERROR 0x20000000 //Retry limit exceeded.
170 #define TXS_UNDERRUN 0x10000000 //Transmit underrun.
171 #define TXS_NO_BUFFER 0x08000000 //Buffer exhausted.
172 #define TXS_NO_CRC 0x00010000 //CRC not appended.
173 #define TXS_LAST_BUFF 0x00008000 //Last buffer of frame.
174 #define TXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS.
176 // Flag to manage local rx buffer
177 #define RXBUF_OWNERSHIP 0x00000001
178 #define RXBUF_WRAP 0x00000002
180 #define BUF_ADDRMASK 0xFFFFFFFC
182 #define RXS_BROADCAST_ADDR 0x80000000 // Broadcast address detected.
183 #define RXS_MULTICAST_HASH 0x40000000 // Multicast hash match.
184 #define RXS_UNICAST_HASH 0x20000000 // Unicast hash match.
185 #define RXS_EXTERNAL_ADDR 0x10000000 // External address match.
186 #define RXS_SA1_ADDR 0x04000000 // Specific address register 1 match.
187 #define RXS_SA2_ADDR 0x02000000 // Specific address register 2 match.
188 #define RXS_SA3_ADDR 0x01000000 // Specific address register 3 match.
189 #define RXS_SA4_ADDR 0x00800000 // Specific address register 4 match.
190 #define RXS_TYPE_ID 0x00400000 // Type ID match.
191 #define RXS_VLAN_TAG 0x00200000 // VLAN tag detected.
192 #define RXS_PRIORITY_TAG 0x00100000 // Priority tag detected.
193 #define RXS_VLAN_PRIORITY 0x000E0000 // VLAN priority.
194 #define RXS_CFI_IND 0x00010000 // Concatenation format indicator.
195 #define RXS_EOF 0x00008000 // End of frame.
196 #define RXS_SOF 0x00004000 // Start of frame.
197 #define RXS_RBF_OFFSET 0x00003000 // Receive buffer offset mask.
198 #define RXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS.
200 #define EMAC_RSR_BITS (BV(EMAC_BNA) | BV(EMAC_REC) | BV(EMAC_OVR))
201 #define EMAC_TSR_BITS (BV(EMAC_UBR) | BV(EMAC_COL) | BV(EMAC_RLES) | \
202 BV(EMAC_BEX) | BV(EMAC_COMP) | BV(EMAC_UND))
204 typedef struct BufDescriptor
206 volatile uint32_t addr;
207 volatile uint32_t stat;
210 #endif /* ETH_SAM3_H */