* \brief ARM UART and SPI I/O driver
*
*
- * \version $Id: ser_amr.c 18280 2007-10-11 15:14:20Z asterix $
+ * \version $Id: ser_at91.c 20881 2008-03-04 14:07:02Z batt $
* \author Daniele Basile <asterix@develer.com>
*/
* \{
*/
-#ifndef SER_UART0_IRQ_INIT
- /**
- * Default IRQ INIT macro - invoked in uart0_init()
- *
- * - Disable all interrupt
- * - Register USART0 interrupt
- * - Enable USART0 clock.
- */
- #define SER_UART0_IRQ_INIT do { \
- US0_IDR = 0xFFFFFFFF; \
- /* Set the vector. */ \
- AIC_SVR(US0_ID) = uart0_irq_dispatcher; \
- /* Initialize to edge triggered with defined priority. */ \
- AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \
- /* Enable the USART IRQ */ \
- AIC_IECR = BV(US0_ID); \
- PMC_PCER = BV(US0_ID); \
- } while (0)
-#endif
-
#ifndef SER_UART0_BUS_TXINIT
/**
* Default TXINIT macro - invoked in uart0_init()
*
* - Disable GPIO on USART0 tx/rx pins
- * - Reset USART0
- * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
- * - Enable both the receiver and the transmitter
- * - Enable only the RX complete interrupt
*/
- #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256
+ #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128
#warning Check USART0 pins!
#endif
#define SER_UART0_BUS_TXINIT do { \
PIOA_PDR = BV(RXD0) | BV(TXD0); \
- US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \
- US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO; \
- US0_CR = BV(US_RXEN) | BV(US_TXEN); \
- US0_IER = BV(US_RXRDY); \
} while (0)
#endif
#ifndef SER_UART0_BUS_TXBEGIN
/**
* Invoked before starting a transmission
- *
- * - Enable both the receiver and the transmitter
- * - Enable both the RX complete and TX empty interrupts
*/
- #define SER_UART0_BUS_TXBEGIN do { \
- US0_CR = BV(US_RXEN) | BV(US_TXEN); \
- US0_IER = BV(US_TXRDY) | BV(US_RXRDY); \
- } while (0)
+ #define SER_UART0_BUS_TXBEGIN
#endif
#ifndef SER_UART0_BUS_TXCHAR
#ifndef SER_UART0_BUS_TXEND
/**
* Invoked as soon as the txfifo becomes empty
- *
- * - Keep both the receiver and the transmitter enabled
- * - Keep the RX complete interrupt enabled
- * - Disable the TX empty interrupts
*/
- #define SER_UART0_BUS_TXEND do { \
- US0_CR = BV(US_RXEN) | BV(US_TXEN); \
- US0_IER = BV(US_RXRDY); \
- US0_IDR = BV(US_TXRDY); \
- } while (0)
+ #define SER_UART0_BUS_TXEND
#endif
/* End USART0 macros */
-#ifndef SER_UART1_IRQ_INIT
- /** \sa SER_UART0_BUS_TXINIT */
- #define SER_UART1_IRQ_INIT do { \
- US1_IDR = 0xFFFFFFFF; \
- /* Set the vector. */ \
- AIC_SVR(US1_ID) = uart1_irq_dispatcher; \
- /* Initialize to edge triggered with defined priority. */ \
- AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \
- /* Enable the USART IRQ */ \
- AIC_IECR = BV(US1_ID); \
- PMC_PCER = BV(US1_ID); \
- } while (0)
-#endif
-
#ifndef SER_UART1_BUS_TXINIT
- /** \sa SER_UART1_BUS_TXINIT */
- #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256
+ /**
+ * Default TXINIT macro - invoked in uart1_init()
+ *
+ * - Disable GPIO on USART1 tx/rx pins
+ */
+ #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128
#warning Check USART1 pins!
#endif
#define SER_UART1_BUS_TXINIT do { \
PIOA_PDR = BV(RXD1) | BV(TXD1); \
- US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \
- US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO; \
- US1_CR = BV(US_RXEN) | BV(US_TXEN); \
- US1_IER = BV(US_RXRDY); \
} while (0)
+
#endif
#ifndef SER_UART1_BUS_TXBEGIN
- /** \sa SER_UART1_BUS_TXBEGIN */
- #define SER_UART1_BUS_TXBEGIN do { \
- US1_CR = BV(US_RXEN) | BV(US_TXEN); \
- US1_IER = BV(US_TXRDY) | BV(US_RXRDY); \
- } while (0)
+ /**
+ * Invoked before starting a transmission
+ */
+ #define SER_UART1_BUS_TXBEGIN
#endif
#ifndef SER_UART1_BUS_TXCHAR
- /** \sa SER_UART1_BUS_TXCHAR */
+ /**
+ * Invoked to send one character.
+ */
#define SER_UART1_BUS_TXCHAR(c) do { \
US1_THR = (c); \
} while (0)
#endif
#ifndef SER_UART1_BUS_TXEND
- /** \sa SER_UART1_BUS_TXEND */
- #define SER_UART1_BUS_TXEND do { \
- US1_CR = BV(US_RXEN) | BV(US_TXEN); \
- US1_IER = BV(US_RXRDY); \
- US1_IDR = BV(US_TXRDY); \
- } while (0)
+ /**
+ * Invoked as soon as the txfifo becomes empty
+ */
+ #define SER_UART1_BUS_TXEND
#endif
-#ifdef NOT_FOR_ARM_PORT_IT
/**
- * \name Overridable SPI hooks
- *
- * These can be redefined in hw.h to implement
- * special bus policies such as slave select pin handling, etc.
- *
- * \{
- */
-#ifndef SER_SPI_BUS_TXINIT
+* \name Overridable SPI hooks
+*
+* These can be redefined in hw.h to implement
+* special bus policies such as slave select pin handling, etc.
+*
+* \{
+*/
+
+#ifndef SER_SPI0_BUS_TXINIT
/**
- * Default TXINIT macro - invoked in spi_init()
- * The default is no action.
- */
- #define SER_SPI_BUS_TXINIT
+ * Default TXINIT macro - invoked in spi_init()
+ * The default is no action.
+ */
+ #define SER_SPI0_BUS_TXINIT
#endif
-#ifndef SER_SPI_BUS_TXCLOSE
+#ifndef SER_SPI0_BUS_TXCLOSE
/**
- * Invoked after the last character has been transmitted.
- * The default is no action.
- */
- #define SER_SPI_BUS_TXCLOSE
+ * Invoked after the last character has been transmitted.
+ * The default is no action.
+ */
+ #define SER_SPI0_BUS_TXCLOSE
#endif
-/*\}*/
+
+#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
+
+ #ifndef SER_SPI1_BUS_TXINIT
+ /**
+ * Default TXINIT macro - invoked in spi_init()
+ * The default is no action.
+ */
+ #define SER_SPI1_BUS_TXINIT
+ #endif
+
+ #ifndef SER_SPI1_BUS_TXCLOSE
+ /**
+ * Invoked after the last character has been transmitted.
+ * The default is no action.
+ */
+ #define SER_SPI1_BUS_TXCLOSE
+ #endif
#endif
+/*\}*/
+
/**
* \def CONFIG_SER_STROBE
static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
-#ifdef NOT_FOR_ARM_PORT_IT
-static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
-static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
+static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE];
+static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE];
+#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
+static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE];
+static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE];
#endif
/**
struct Serial *ser_uart0 = &ser_handles[SER_UART0];
struct Serial *ser_uart1 = &ser_handles[SER_UART1];
-#ifdef NOT_FOR_ARM_PORT_IT
-struct Serial *ser_spi = &ser_handles[SER_SPI];
+struct Serial *ser_spi0 = &ser_handles[SER_SPI0];
+#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
+struct Serial *ser_spi1 = &ser_handles[SER_SPI1];
#endif
static void uart0_irq_dispatcher(void);
static void uart1_irq_dispatcher(void);
+static void spi0_irq_handler(void);
+#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
+static void spi1_irq_handler(void);
+#endif
/*
* Callbacks for USART0
*/
UNUSED_ARG(struct SerialHardware *, _hw),
UNUSED_ARG(struct Serial *, ser))
{
- SER_UART0_IRQ_INIT;
+ US0_IDR = 0xFFFFFFFF;
+ /* Set the vector. */
+ AIC_SVR(US0_ID) = uart0_irq_dispatcher;
+ /* Initialize to edge triggered with defined priority. */
+ AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
+ PMC_PCER = BV(US0_ID);
+
+ /*
+ * - Reset USART0
+ * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
+ * - Enable both the receiver and the transmitter
+ * - Enable only the RX complete interrupt
+ */
+ US0_CR = BV(US_RSTRX) | BV(US_RSTTX);
+ US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
+ US0_CR = BV(US_RXEN) | BV(US_TXEN);
+ US0_IER = BV(US_RXRDY);
+
SER_UART0_BUS_TXINIT;
+
+ /* Enable the USART IRQ */
+ AIC_IECR = BV(US0_ID);
+
SER_STROBE_INIT;
}
if (!hw->sending)
{
hw->sending = true;
+ /*
+ * - Enable the transmitter
+ * - Enable TX empty interrupt
+ */
SER_UART0_BUS_TXBEGIN;
+ US0_IER = BV(US_TXEMPTY);
}
}
{
case SER_PARITY_NONE:
{
- /* Parity mode. */
+ /* Parity none. */
US0_MR |= US_PAR_NO;
break;
}
case SER_PARITY_EVEN:
{
- /* Even parity.*/
+ /* Even parity. */
US0_MR |= US_PAR_EVEN;
break;
}
case SER_PARITY_ODD:
{
- /* Odd parity.*/
+ /* Odd parity. */
US0_MR |= US_PAR_ODD;
break;
}
UNUSED_ARG(struct SerialHardware *, _hw),
UNUSED_ARG(struct Serial *, ser))
{
- SER_UART1_IRQ_INIT;
+ US1_IDR = 0xFFFFFFFF;
+ /* Set the vector. */
+ AIC_SVR(US1_ID) = uart1_irq_dispatcher;
+ /* Initialize to edge triggered with defined priority. */
+ AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
+ PMC_PCER = BV(US1_ID);
+
+ /*
+ * - Reset USART1
+ * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
+ * - Enable both the receiver and the transmitter
+ * - Enable only the RX complete interrupt
+ */
+ US1_CR = BV(US_RSTRX) | BV(US_RSTTX);
+ US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
+ US1_CR = BV(US_RXEN) | BV(US_TXEN);
+ US1_IER = BV(US_RXRDY);
+
SER_UART1_BUS_TXINIT;
+
+ /* Enable the USART IRQ */
+ AIC_IECR = BV(US1_ID);
+
SER_STROBE_INIT;
}
if (!hw->sending)
{
hw->sending = true;
+ /*
+ * - Enable the transmitter
+ * - Enable TX empty interrupt
+ */
SER_UART1_BUS_TXBEGIN;
+ US1_IER = BV(US_TXEMPTY);
}
}
{
case SER_PARITY_NONE:
{
- /* Parity mode. */
+ /* Parity none. */
US1_MR |= US_PAR_NO;
break;
}
case SER_PARITY_EVEN:
{
- /* Even parity.*/
+ /* Even parity. */
US1_MR |= US_PAR_EVEN;
break;
}
case SER_PARITY_ODD:
{
- /* Odd parity.*/
+ /* Odd parity. */
US1_MR |= US_PAR_ODD;
break;
}
}
/* SPI driver */
-#ifdef NOT_FOR_ARM_PORT_IT
-static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
+static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
{
+ /* Disable PIO on SPI pins */
+ PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
+
+ /* Reset device */
+ SPI0_CR = BV(SPI_SWRST);
+
/*
- * Set MOSI and SCK ports out, MISO in.
- *
- * The ATmega64/128 datasheet explicitly states that the input/output
- * state of the SPI pins is not significant, as when the SPI is
- * active the I/O port are overrided.
- * This is *blatantly FALSE*.
- *
- * Moreover, the MISO pin on the board_kc *must* be in high impedance
- * state even when the SPI is off, because the line is wired together
- * with the KBus serial RX, and the transmitter of the slave boards
- * would be unable to drive the line.
+ * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
+ * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
*/
- ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
+ SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
/*
- * If the SPI master mode is activated and the SS pin is in input and tied low,
- * the SPI hardware will automatically switch to slave mode!
- * For proper communication this pins should therefore be:
- * - as output
- * - as input but tied high forever!
- * This driver set the pin as output.
+ * Set SPI mode.
+ * At reset clock division factor is set to 0, that is
+ * *forbidden*. Set SPI clock to minimum to keep it valid.
*/
- #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
- ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
+ SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
- ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
- /* Enable SPI, IRQ on, Master */
- SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
+ /* Disable all irqs */
+ SPI0_IDR = 0xFFFFFFFF;
+ /* Set the vector. */
+ AIC_SVR(SPI0_ID) = spi0_irq_handler;
+ /* Initialize to edge triggered with defined priority. */
+ AIC_SMR(SPI0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
+ /* Enable the USART IRQ */
+ AIC_IECR = BV(SPI0_ID);
+ PMC_PCER = BV(SPI0_ID);
- /* Set data order */
- #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
- SPCR |= BV(DORD);
- #endif
+ /* Enable interrupt on tx buffer empty */
+ SPI0_IER = BV(SPI_TXEMPTY);
- /* Set SPI clock rate */
- #if CONFIG_SPI_CLOCK_DIV == 128
- SPCR |= (BV(SPR1) | BV(SPR0));
- #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
- SPCR |= BV(SPR1);
- #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
- SPCR |= BV(SPR0);
- #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
- // SPR0 & SDPR1 both at 0
- #else
- #error Unsupported SPI clock division factor.
- #endif
+ /* Enable SPI */
+ SPI0_CR = BV(SPI_SPIEN);
- /* Set SPI2X bit (spi double frequency) */
- #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
- || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
- SPSR &= ~BV(SPI2X);
- #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
- SPSR |= BV(SPI2X);
- #else
- #error Unsupported SPI clock division factor.
- #endif
- /* Set clock polarity */
- #if CONFIG_SPI_CLOCK_POL == 1
- SPCR |= BV(CPOL);
- #endif
+ SER_SPI0_BUS_TXINIT;
- /* Set clock phase */
- #if CONFIG_SPI_CLOCK_PHASE == 1
- SPCR |= BV(CPHA);
- #endif
- SER_SPI_BUS_TXINIT;
+ SER_STROBE_INIT;
+}
+
+static void spi0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
+{
+ /* Disable SPI */
+ SPI0_CR = BV(SPI_SPIDIS);
+
+ /* Disable all irqs */
+ SPI0_IDR = 0xFFFFFFFF;
+
+ SER_SPI0_BUS_TXCLOSE;
+
+ /* Enable PIO on SPI pins */
+ PIOA_PER = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
+}
+
+static void spi0_starttx(struct SerialHardware *_hw)
+{
+ struct ArmSerial *hw = (struct ArmSerial *)_hw;
+
+ cpuflags_t flags;
+ IRQ_SAVE_DISABLE(flags);
+
+ /* Send data only if the SPI is not already transmitting */
+ if (!hw->sending && !fifo_isempty(&ser_spi0->txfifo))
+ {
+ hw->sending = true;
+ SPI0_TDR = fifo_pop(&ser_spi0->txfifo);
+ }
+
+ IRQ_RESTORE(flags);
+}
+
+static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
+{
+ SPI0_CSR0 &= ~SPI_SCBR;
+
+ ASSERT((uint8_t)DIV_ROUND(CLOCK_FREQ, rate));
+ SPI0_CSR0 |= DIV_ROUND(CLOCK_FREQ, rate) << SPI_SCBR_SHIFT;
+}
+
+/* SPI driver */
+static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
+{
+ /* Disable PIO on SPI pins */
+ PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
+
+ /* Reset device */
+ SPI1_CR = BV(SPI_SWRST);
+
+/*
+ * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
+ * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
+ */
+ SPI1_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
+
+ /*
+ * Set SPI mode.
+ * At reset clock division factor is set to 0, that is
+ * *forbidden*. Set SPI clock to minimum to keep it valid.
+ */
+ SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
+
+ /* Disable all irqs */
+ SPI1_IDR = 0xFFFFFFFF;
+ /* Set the vector. */
+ AIC_SVR(SPI1_ID) = spi1_irq_handler;
+ /* Initialize to edge triggered with defined priority. */
+ AIC_SMR(SPI1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
+ /* Enable the USART IRQ */
+ AIC_IECR = BV(SPI1_ID);
+ PMC_PCER = BV(SPI1_ID);
+
+ /* Enable interrupt on tx buffer empty */
+ SPI1_IER = BV(SPI_TXEMPTY);
+
+ /* Enable SPI */
+ SPI1_CR = BV(SPI_SPIEN);
+
+
+ SER_SPI1_BUS_TXINIT;
SER_STROBE_INIT;
}
-static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
+static void spi1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
{
- SPCR = 0;
+ /* Disable SPI */
+ SPI1_CR = BV(SPI_SPIDIS);
+
+ /* Disable all irqs */
+ SPI1_IDR = 0xFFFFFFFF;
- SER_SPI_BUS_TXCLOSE;
+ SER_SPI1_BUS_TXCLOSE;
- /* Set all pins as inputs */
- ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
+ /* Enable PIO on SPI pins */
+ PIOA_PER = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
}
-static void spi_starttx(struct SerialHardware *_hw)
+static void spi1_starttx(struct SerialHardware *_hw)
{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
+ struct ArmSerial *hw = (struct ArmSerial *)_hw;
cpuflags_t flags;
IRQ_SAVE_DISABLE(flags);
/* Send data only if the SPI is not already transmitting */
- if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
+ if (!hw->sending && !fifo_isempty(&ser_spi1->txfifo))
{
hw->sending = true;
- SPDR = fifo_pop(&ser_spi->txfifo);
+ SPI1_TDR = fifo_pop(&ser_spi1->txfifo);
}
IRQ_RESTORE(flags);
}
-static void spi_setbaudrate(
- UNUSED_ARG(struct SerialHardware *, _hw),
- UNUSED_ARG(unsigned long, rate))
+static void spi1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
{
- // nop
+ SPI1_CSR0 &= ~SPI_SCBR;
+
+ ASSERT((uint8_t)DIV_ROUND(CLOCK_FREQ, rate));
+ SPI1_CSR0 |= DIV_ROUND(CLOCK_FREQ, rate) << SPI_SCBR_SHIFT;
}
static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
{
// nop
}
-#endif
static bool tx_sending(struct SerialHardware* _hw)
C99INIT(txSending, tx_sending),
};
-#ifdef NOT_FOR_ARM_PORT_IT
-static const struct SerialHardwareVT SPI_VT =
+static const struct SerialHardwareVT SPI0_VT =
+{
+ C99INIT(init, spi0_init),
+ C99INIT(cleanup, spi0_cleanup),
+ C99INIT(setBaudrate, spi0_setbaudrate),
+ C99INIT(setParity, spi_setparity),
+ C99INIT(txStart, spi0_starttx),
+ C99INIT(txSending, tx_sending),
+};
+#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128
+static const struct SerialHardwareVT SPI1_VT =
{
- C99INIT(init, spi_init),
- C99INIT(cleanup, spi_cleanup),
- C99INIT(setBaudrate, spi_setbaudrate),
+ C99INIT(init, spi1_init),
+ C99INIT(cleanup, spi1_cleanup),
+ C99INIT(setBaudrate, spi1_setbaudrate),
C99INIT(setParity, spi_setparity),
- C99INIT(txStart, spi_starttx),
+ C99INIT(txStart, spi1_starttx),
C99INIT(txSending, tx_sending),
};
#endif
},
C99INIT(sending, false),
},
-#ifdef NOT_FOR_ARM_PORT_IT
+
{
C99INIT(hw, /**/) {
- C99INIT(table, &SPI_VT),
- C99INIT(txbuffer, spi_txbuffer),
- C99INIT(rxbuffer, spi_rxbuffer),
- C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
- C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
+ C99INIT(table, &SPI0_VT),
+ C99INIT(txbuffer, spi0_txbuffer),
+ C99INIT(rxbuffer, spi0_rxbuffer),
+ C99INIT(txbuffer_size, sizeof(spi0_txbuffer)),
+ C99INIT(rxbuffer_size, sizeof(spi0_rxbuffer)),
+ },
+ C99INIT(sending, false),
+ },
+ #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128
+ {
+ C99INIT(hw, /**/) {
+ C99INIT(table, &SPI1_VT),
+ C99INIT(txbuffer, spi1_txbuffer),
+ C99INIT(rxbuffer, spi1_rxbuffer),
+ C99INIT(txbuffer_size, sizeof(spi1_txbuffer)),
+ C99INIT(rxbuffer_size, sizeof(spi1_rxbuffer)),
},
C99INIT(sending, false),
}
-#endif
+
+ #endif
};
struct SerialHardware *ser_hw_getdesc(int unit)
if (fifo_isempty(txfifo))
{
+ /*
+ * - Disable the TX empty interrupts
+ */
+ US0_IDR = BV(US_TXEMPTY);
SER_UART0_BUS_TXEND;
UARTDescs[SER_UART0].sending = false;
}
if (US0_CSR & BV(US_RXRDY))
uart0_irq_rx();
- if (US0_CSR & BV(US_TXRDY))
+ if (US0_CSR & BV(US_TXEMPTY))
uart0_irq_tx();
/* Inform hw that we have served the IRQ */
if (fifo_isempty(txfifo))
{
+ /*
+ * - Disable the TX empty interrupts
+ */
+ US1_IDR = BV(US_TXEMPTY);
SER_UART1_BUS_TXEND;
UARTDescs[SER_UART1].sending = false;
}
if (US1_CSR & BV(US_RXRDY))
uart1_irq_rx();
- if (US1_CSR & BV(US_TXRDY))
+ if (US1_CSR & BV(US_TXEMPTY))
uart1_irq_tx();
/* Inform hw that we have served the IRQ */
AIC_EOICR = 0;
}
+
+/**
+ * SPI0 interrupt handler
+ */
+static void spi0_irq_handler(void) __attribute__ ((interrupt));
+static void spi0_irq_handler(void)
+{
+ SER_STROBE_ON;
+
+ char c = SPI0_RDR;
+ /* Read incoming byte. */
+ if (!fifo_isfull(&ser_spi0->rxfifo))
+ fifo_push(&ser_spi0->rxfifo, c);
+ /*
+ * FIXME
+ else
+ ser_spi0->status |= SERRF_RXFIFOOVERRUN;
+ */
+
+ /* Send */
+ if (!fifo_isempty(&ser_spi0->txfifo))
+ SPI0_TDR = fifo_pop(&ser_spi0->txfifo);
+ else
+ UARTDescs[SER_SPI0].sending = false;
+
+ /* Inform hw that we have served the IRQ */
+ AIC_EOICR = 0;
+ SER_STROBE_OFF;
+}
+
+
+#if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X128
+/**
+ * SPI1 interrupt handler
+ */
+static void spi1_irq_handler(void) __attribute__ ((interrupt));
+static void spi1_irq_handler(void)
+{
+ SER_STROBE_ON;
+
+ char c = SPI1_RDR;
+ /* Read incoming byte. */
+ if (!fifo_isfull(&ser_spi1->rxfifo))
+ fifo_push(&ser_spi1->rxfifo, c);
+ /*
+ * FIXME
+ else
+ ser_spi1->status |= SERRF_RXFIFOOVERRUN;
+ */
+
+ /* Send */
+ if (!fifo_isempty(&ser_spi1->txfifo))
+ SPI1_TDR = fifo_pop(&ser_spi1->txfifo);
+ else
+ UARTDescs[SER_SPI1].sending = false;
+
+ /* Inform hw that we have served the IRQ */
+ AIC_EOICR = 0;
+ SER_STROBE_OFF;
+}
+#endif
projects / bertos.git / commitdiff