#ifndef ETH_AT91_H
#define ETH_AT91_H
-// Settings and definition for PHY registers
-// \{
-
-//Registry definition
-#define NIC_PHY_BMCR 0x00 // Basic mode control register.
-#define NIC_PHY_BMCR_COLTEST 0x0080 // Collision test.
-#define NIC_PHY_BMCR_FDUPLEX 0x0100 // Full duplex mode.
-#define NIC_PHY_BMCR_ANEGSTART 0x0200 // Restart auto negotiation.
-#define NIC_PHY_BMCR_ISOLATE 0x0400 // Isolate from MII.
-#define NIC_PHY_BMCR_PWRDN 0x0800 // Power-down.
-#define NIC_PHY_BMCR_ANEGENA 0x1000 // Enable auto negotiation.
-#define NIC_PHY_BMCR_100MBPS 0x2000 // Select 100 Mbps.
-#define NIC_PHY_BMCR_LOOPBACK 0x4000 // Enable loopback mode.
-#define NIC_PHY_BMCR_RESET 0x8000 // Software reset.
-
-#define NIC_PHY_BMSR 0x01 // Basic mode status register.
-#define NIC_PHY_BMSR_ANCOMPL 0x0020 // Auto negotiation complete.
-#define NIC_PHY_BMSR_ANEGCAPABLE 0x0008 // Able to do auto-negotiation
-#define NIC_PHY_BMSR_LINKSTAT 0x0004 // Link status.
-
-#define NIC_PHY_ID1 0x02 // PHY identifier register 1.
-#define NIC_PHY_ID2 0x03 // PHY identifier register 2.
-#define NIC_PHY_ANAR 0x04 // Auto negotiation advertisement register.
-#define NIC_PHY_ANLPAR 0x05 // Auto negotiation link partner availability register.
-#define NIC_PHY_ANER 0x06 // Auto negotiation expansion register.
-
-/* Pin definition MII/RMII PHY interdace */
-#define PHY_TXCLK_BIT BV(0)
-#define PHY_TXEN_BIT BV(1)
-#define PHY_TXD0_BIT BV(2)
-#define PHY_TXD1_BIT BV(3)
-#define PHY_CRS_BIT BV(4)
-#define PHY_RXD0_BIT BV(5)
-#define PHY_RXD1_BIT BV(6)
-#define PHY_RXER_BIT BV(7)
-#define PHY_MDC_BIT BV(8)
-#define PHY_MDIO_BIT BV(9)
-#define PHY_TXD2_BIT BV(10)
-#define PHY_TXD3_BIT BV(11)
-#define PHY_TXER_BIT BV(12)
-#define PHY_RXD2_BIT BV(13)
-#define PHY_RXD3_BIT BV(14)
-#define PHY_RXDV_BIT BV(15)
-#define PHY_COL_BIT BV(16)
-#define PHY_RXCLK_BIT BV(17)
-
-#define PHY_MII_PINS \
- ( PHY_TXEN_BIT \
- | PHY_TXD0_BIT \
- | PHY_TXD1_BIT \
- | PHY_CRS_BIT \
- | PHY_RXD0_BIT \
- | PHY_RXD1_BIT \
- | PHY_RXER_BIT \
- | PHY_MDC_BIT \
- | PHY_MDIO_BIT \
- | PHY_TXD2_BIT \
- | PHY_TXD3_BIT \
- | PHY_TXER_BIT \
- | PHY_RXD2_BIT \
- | PHY_RXD3_BIT \
- | PHY_RXDV_BIT \
- | PHY_COL_BIT \
- | PHY_RXCLK_BIT)
-// \}
+#include <cpu/types.h>
#define EMAC_TX_BUFSIZ 1518 //!!! Don't change this
#define EMAC_TX_BUFFERS 1 //!!! Don't change this
#endif
/*\}*/
+
+/**
+ * Pin definition MII/RMII PHY interdace
+ */
+#if CPU_ARM_SAM7X
+ #define PHY_TXCLK_BIT BV(0)
+ #define PHY_TXEN_BIT BV(1)
+ #define PHY_TXD0_BIT BV(2)
+ #define PHY_TXD1_BIT BV(3)
+ #define PHY_CRS_BIT BV(4)
+ #define PHY_RXD0_BIT BV(5)
+ #define PHY_RXD1_BIT BV(6)
+ #define PHY_RXER_BIT BV(7)
+ #define PHY_MDC_BIT BV(8)
+ #define PHY_MDIO_BIT BV(9)
+ #define PHY_TXD2_BIT BV(10)
+ #define PHY_TXD3_BIT BV(11)
+ #define PHY_TXER_BIT BV(12)
+ #define PHY_RXD2_BIT BV(13)
+ #define PHY_RXD3_BIT BV(14)
+ #define PHY_RXDV_BIT BV(15)
+ #define PHY_COL_BIT BV(16)
+ #define PHY_RXCLK_BIT BV(17)
+
+#elif CPU_ARM_SAM7S_LARGE
+ /* No ethernet interface is present on this cpu */
+#else
+ #error No MII/RMII PHY pins interface was define for select CPU.
+#endif
+
+#define PHY_MII_PINS \
+ ( PHY_TXEN_BIT \
+ | PHY_TXD0_BIT \
+ | PHY_TXD1_BIT \
+ | PHY_CRS_BIT \
+ | PHY_RXD0_BIT \
+ | PHY_RXD1_BIT \
+ | PHY_RXER_BIT \
+ | PHY_MDC_BIT \
+ | PHY_MDIO_BIT \
+ | PHY_TXD2_BIT \
+ | PHY_TXD3_BIT \
+ | PHY_TXER_BIT \
+ | PHY_RXD2_BIT \
+ | PHY_RXD3_BIT \
+ | PHY_RXDV_BIT \
+ | PHY_COL_BIT \
+ | PHY_RXCLK_BIT)
+// \}
+
#endif /* AT91SAM7_H */
* \author Stefano Fedrigo <aleph@develer.com>
*/
+#include "eth_sam3.h"
#include "cfg/cfg_eth.h"
#define LOG_LEVEL ETH_LOG_LEVEL
#include <cfg/macros.h>
#include <cfg/compiler.h>
-// TODO: unify includes
-//#include <io/at91sam7.h>
-//#include <io/arm.h>
-//#include <io/include.h>
-#include <io/sam3.h>
+#include <io/cm3.h>
+
#include <drv/irq_cm3.h>
+#include <drv/timer.h>
+#include <drv/eth.h>
#include <cpu/power.h>
#include <cpu/types.h>
#include <cpu/irq.h>
-#include <drv/timer.h>
-#include <drv/eth.h>
-
#include <mware/event.h>
#include <string.h>
-#include "eth_sam3.h"
-
#define EMAC_RX_INTS (BV(EMAC_RCOMP) | BV(EMAC_ROVR) | BV(EMAC_RXUBR))
#define EMAC_TX_INTS (BV(EMAC_TCOMP) | BV(EMAC_TXUBR) | BV(EMAC_RLEX))
#ifndef ETH_SAM3_H
#define ETH_SAM3_H
-// Settings and definition for DAVICOM 9161A
-// \{
-#define NIC_PHY_ADDR 0
-
-// Register bits definition
-#define NIC_PHY_BMCR 0x00 // Basic mode control register.
-#define NIC_PHY_BMCR_COLTEST 0x0080 // Collision test.
-#define NIC_PHY_BMCR_FDUPLEX 0x0100 // Full duplex mode.
-#define NIC_PHY_BMCR_ANEGSTART 0x0200 // Restart auto negotiation.
-#define NIC_PHY_BMCR_ISOLATE 0x0400 // Isolate from MII.
-#define NIC_PHY_BMCR_PWRDN 0x0800 // Power-down.
-#define NIC_PHY_BMCR_ANEGENA 0x1000 // Enable auto negotiation.
-#define NIC_PHY_BMCR_100MBPS 0x2000 // Select 100 Mbps.
-#define NIC_PHY_BMCR_LOOPBACK 0x4000 // Enable loopback mode.
-#define NIC_PHY_BMCR_RESET 0x8000 // Software reset.
-
-#define NIC_PHY_BMSR 0x01 // Basic mode status register.
-#define NIC_PHY_BMSR_ANCOMPL 0x0020 // Auto negotiation complete.
-#define NIC_PHY_BMSR_ANEGCAPABLE 0x0008 // Able to do auto-negotiation
-#define NIC_PHY_BMSR_LINKSTAT 0x0004 // Link status.
-
-#define NIC_PHY_ANLPAR_10_HDX BV(5) // 10BASE-T half duplex
-#define NIC_PHY_ANLPAR_10_FDX BV(6) // 10BASE-T full duplex
-#define NIC_PHY_ANLPAR_TX_HDX BV(7) // 100BASE-TX half duplex
-#define NIC_PHY_ANLPAR_TX_FDX BV(8) // 100BASE-TX full duplex
-
-#define NIC_PHY_ID1 0x02 // PHY identifier register 1.
-#define NIC_PHY_ID2 0x03 // PHY identifier register 2.
-#define NIC_PHY_ANAR 0x04 // Auto negotiation advertisement register.
-#define NIC_PHY_ANLPAR 0x05 // Auto negotiation link partner availability register.
-#define NIC_PHY_ANER 0x06 // Auto negotiation expansion register.
-
-#if CPU_ARM_AT91
-
-/*
- * Pin definition for DAVICOM 9161A.
- * See schematics for AT91SAM7X-EK evalution board.
- */
-// All pins in port B
-#define PHY_REFCLK_XT2_BIT 0
-#define PHY_TXEN_BIT 1
-#define PHY_TXD0_BIT 2
-#define PHY_TXD1_BIT 3
-#define PHY_CRS_AD4_BIT 4
-#define PHY_RXD0_AD0_BIT 5
-#define PHY_RXD1_AD1_BIT 6
-#define PHY_RXER_RXD4_RPTR_BIT 7
-#define PHY_MDC_BIT 8
-#define PHY_MDIO_BIT 9
-#define PHY_TXD2_BIT 10
-#define PHY_TXD3_BIT 11
-#define PHY_TXER_TXD4_BIT 12
-#define PHY_RXD2_AD2_BIT 13
-#define PHY_RXD3_AD3_BIT 14
-#define PHY_RXDV_TESTMODE_BIT 15
-#define PHY_COL_RMII_BIT 16
-#define PHY_RXCLK_10BTSER_BIT 17
-#define PHY_PWRDN_BIT 18
-#define PHY_MDINTR_BIT 26
-
-#define PHY_MII_PINS \
- BV(PHY_REFCLK_XT2_BIT) \
- | BV(PHY_TXEN_BIT) \
- | BV(PHY_TXD0_BIT) \
- | BV(PHY_TXD1_BIT) \
- | BV(PHY_CRS_AD4_BIT) \
- | BV(PHY_RXD0_AD0_BIT) \
- | BV(PHY_RXD1_AD1_BIT) \
- | BV(PHY_RXER_RXD4_RPTR_BIT) \
- | BV(PHY_MDC_BIT) \
- | BV(PHY_MDIO_BIT) \
- | BV(PHY_TXD2_BIT) \
- | BV(PHY_TXD3_BIT) \
- | BV(PHY_TXER_TXD4_BIT) \
- | BV(PHY_RXD2_AD2_BIT) \
- | BV(PHY_RXD3_AD3_BIT) \
- | BV(PHY_RXDV_TESTMODE_BIT) \
- | BV(PHY_COL_RMII_BIT) \
- | BV(PHY_RXCLK_10BTSER_BIT)
-
-#else
-
-/*
- * Pin definition for DAVICOM 9161A.
- * See schematics for SAM3X-EK evalution board.
- */
-// Port B
-#define PHY_REFCLK_XT2_BIT 0
-#define PHY_TXEN_BIT 1
-#define PHY_TXD0_BIT 2
-#define PHY_TXD1_BIT 3
-#define PHY_RXDV_TESTMODE_BIT 4
-#define PHY_RXD0_AD0_BIT 5
-#define PHY_RXD1_AD1_BIT 6
-#define PHY_RXER_RXD4_RPTR_BIT 7
-#define PHY_MDC_BIT 8
-#define PHY_MDIO_BIT 9
-// Port A
-#define PHY_MDINTR_BIT 5
-
-#define PHY_MII_PINS_PORTB \
- BV(PHY_REFCLK_XT2_BIT) \
- | BV(PHY_TXEN_BIT) \
- | BV(PHY_TXD0_BIT) \
- | BV(PHY_TXD1_BIT) \
- | BV(PHY_RXD0_AD0_BIT) \
- | BV(PHY_RXD1_AD1_BIT) \
- | BV(PHY_RXER_RXD4_RPTR_BIT) \
- | BV(PHY_MDC_BIT) \
- | BV(PHY_MDIO_BIT)
-
-#endif /* CPU_ARM_AT91 */
-// \}
-
+#include <cpu/types.h>
#define EMAC_TX_BUFSIZ 1518 //!!! Don't change this
#define EMAC_TX_BUFFERS 1 //!!! Don't change this
#endif
-/*\}*/
+#if CPU_CM3_SAM3X8
+ // Port B
+ #define PHY_REFCLK_XT2_BIT 0
+ #define PHY_TXEN_BIT 1
+ #define PHY_TXD0_BIT 2
+ #define PHY_TXD1_BIT 3
+ #define PHY_RXDV_TESTMODE_BIT 4
+ #define PHY_RXD0_AD0_BIT 5
+ #define PHY_RXD1_AD1_BIT 6
+ #define PHY_RXER_RXD4_RPTR_BIT 7
+ #define PHY_MDC_BIT 8
+ #define PHY_MDIO_BIT 9
+ // Port A
+ #define PHY_MDINTR_BIT 5
+#elif (CPU_CM3_SAM3U || CPU_CM3_SAM3N)
+ /* No ethernet interface is present on this cpu */
+#else
+ #error No MII/RMII PHY pins interface was define for select CPU.
+#endif
+
+#define PHY_MII_PINS_PORTB \
+ BV(PHY_REFCLK_XT2_BIT) \
+ | BV(PHY_TXEN_BIT) \
+ | BV(PHY_TXD0_BIT) \
+ | BV(PHY_TXD1_BIT) \
+ | BV(PHY_RXD0_AD0_BIT) \
+ | BV(PHY_RXD1_AD1_BIT) \
+ | BV(PHY_RXER_RXD4_RPTR_BIT) \
+ | BV(PHY_MDC_BIT) \
+ | BV(PHY_MDIO_BIT)
+
+
#endif /* SAM3_H */
#include <cfg/cfg_eth.h>
+/*
+ * Common PHY settings
+ */
+
+/**
+ * Basic mode control settings.
+ *
+ *\{
+ */
+#define NIC_PHY_BMCR 0x00 ///< Basic mode control register address.
+
+#define NIC_PHY_BMCR_COLTEST BV(7) ///< Collision test.
+#define NIC_PHY_BMCR_FDUPLEX BV(8) ///< Full duplex mode.
+#define NIC_PHY_BMCR_ANEGSTART BV(9) ///< Restart auto negotiation.
+#define NIC_PHY_BMCR_ISOLATE BV(10) ///< Isolate from MII.
+#define NIC_PHY_BMCR_PWRDN BV(11) ///< Power-down.
+#define NIC_PHY_BMCR_ANEGENA BV(12) ///< Enable auto negotiation.
+#define NIC_PHY_BMCR_100MBPS BV(13) ///< Select 100 Mbps.
+#define NIC_PHY_BMCR_LOOPBACK BV(14) ///< Enable loopback mode.
+#define NIC_PHY_BMCR_RESET BV(15) ///< Software reset.
+/* \} */
+
+/**
+ * Basic mode status settings.
+ *
+ *\{
+ */
+#define NIC_PHY_BMSR 0x01 ///< Basic mode status register.
+
+#define NIC_PHY_BMSR_ANCOMPL BV(5) ///< Auto negotiation complete.
+#define NIC_PHY_BMSR_ANEGCAPABLE BV(3) ///< Able to do auto-negotiation
+#define NIC_PHY_BMSR_LINKSTAT BV(2) ///< Link status.
+/* \} */
+
+#define NIC_PHY_ID1 0x02 ///< PHY identifier register 1.
+#define NIC_PHY_ID2 0x03 ///< PHY identifier register 2.
+#define NIC_PHY_ANAR 0x04 ///< Auto negotiation advertisement register.
+#define NIC_PHY_ANLPAR 0x05 ///< Auto negotiation link partner availability register.
+
+/**
+ * Auto negotiation expansion settings.
+ *
+ *\{
+ */
+#define NIC_PHY_ANER 0x06 // Auto negotiation expansion register address.
+
+#define NIC_PHY_ANLPAR_10_HDX BV(5) ///< 10BASE-T half duplex
+#define NIC_PHY_ANLPAR_10_FDX BV(6) ///< 10BASE-T full duplex
+#define NIC_PHY_ANLPAR_TX_HDX BV(7) ///< 100BASE-TX half duplex
+#define NIC_PHY_ANLPAR_TX_FDX BV(8) ///< 100BASE-TX full duplex
+/* \} */
+
+
/**
* \name Supported PHY chip.
*
projects / bertos.git / commitdiff