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29 * Copyright 2009 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief EMAC driver for AT91SAM7X Family, interface.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
42 // Settings and definition for PHY registers
46 #define NIC_PHY_BMCR 0x00 // Basic mode control register.
47 #define NIC_PHY_BMCR_COLTEST 0x0080 // Collision test.
48 #define NIC_PHY_BMCR_FDUPLEX 0x0100 // Full duplex mode.
49 #define NIC_PHY_BMCR_ANEGSTART 0x0200 // Restart auto negotiation.
50 #define NIC_PHY_BMCR_ISOLATE 0x0400 // Isolate from MII.
51 #define NIC_PHY_BMCR_PWRDN 0x0800 // Power-down.
52 #define NIC_PHY_BMCR_ANEGENA 0x1000 // Enable auto negotiation.
53 #define NIC_PHY_BMCR_100MBPS 0x2000 // Select 100 Mbps.
54 #define NIC_PHY_BMCR_LOOPBACK 0x4000 // Enable loopback mode.
55 #define NIC_PHY_BMCR_RESET 0x8000 // Software reset.
57 #define NIC_PHY_BMSR 0x01 // Basic mode status register.
58 #define NIC_PHY_BMSR_ANCOMPL 0x0020 // Auto negotiation complete.
59 #define NIC_PHY_BMSR_ANEGCAPABLE 0x0008 // Able to do auto-negotiation
60 #define NIC_PHY_BMSR_LINKSTAT 0x0004 // Link status.
62 #define NIC_PHY_ID1 0x02 // PHY identifier register 1.
63 #define NIC_PHY_ID2 0x03 // PHY identifier register 2.
64 #define NIC_PHY_ANAR 0x04 // Auto negotiation advertisement register.
65 #define NIC_PHY_ANLPAR 0x05 // Auto negotiation link partner availability register.
66 #define NIC_PHY_ANER 0x06 // Auto negotiation expansion register.
68 /* Pin definition MII/RMII PHY interdace */
69 #define PHY_TXCLK_BIT BV(0)
70 #define PHY_TXEN_BIT BV(1)
71 #define PHY_TXD0_BIT BV(2)
72 #define PHY_TXD1_BIT BV(3)
73 #define PHY_CRS_BIT BV(4)
74 #define PHY_RXD0_BIT BV(5)
75 #define PHY_RXD1_BIT BV(6)
76 #define PHY_RXER_BIT BV(7)
77 #define PHY_MDC_BIT BV(8)
78 #define PHY_MDIO_BIT BV(9)
79 #define PHY_TXD2_BIT BV(10)
80 #define PHY_TXD3_BIT BV(11)
81 #define PHY_TXER_BIT BV(12)
82 #define PHY_RXD2_BIT BV(13)
83 #define PHY_RXD3_BIT BV(14)
84 #define PHY_RXDV_BIT BV(15)
85 #define PHY_COL_BIT BV(16)
86 #define PHY_RXCLK_BIT BV(17)
88 #define PHY_MII_PINS \
108 #define EMAC_TX_BUFSIZ 1518 //!!! Don't change this
109 #define EMAC_TX_BUFFERS 1 //!!! Don't change this
110 #define EMAC_TX_DESCRIPTORS EMAC_TX_BUFFERS
112 #define EMAC_RX_BUFFERS 32 //!!! Don't change this
113 #define EMAC_RX_BUFSIZ 128 //!!! Don't change this
114 #define EMAC_RX_DESCRIPTORS EMAC_RX_BUFFERS
116 // Flag to manage local tx buffer
117 #define TXS_USED 0x80000000 //Used buffer.
118 #define TXS_WRAP 0x40000000 //Last descriptor.
119 #define TXS_ERROR 0x20000000 //Retry limit exceeded.
120 #define TXS_UNDERRUN 0x10000000 //Transmit underrun.
121 #define TXS_NO_BUFFER 0x08000000 //Buffer exhausted.
122 #define TXS_NO_CRC 0x00010000 //CRC not appended.
123 #define TXS_LAST_BUFF 0x00008000 //Last buffer of frame.
124 #define TXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS.
126 // Flag to manage local rx buffer
127 #define RXBUF_OWNERSHIP 0x00000001
128 #define RXBUF_WRAP 0x00000002
130 #define BUF_ADDRMASK 0xFFFFFFFC
132 #define RXS_BROADCAST_ADDR 0x80000000 // Broadcast address detected.
133 #define RXS_MULTICAST_HASH 0x40000000 // Multicast hash match.
134 #define RXS_UNICAST_HASH 0x20000000 // Unicast hash match.
135 #define RXS_EXTERNAL_ADDR 0x10000000 // External address match.
136 #define RXS_SA1_ADDR 0x04000000 // Specific address register 1 match.
137 #define RXS_SA2_ADDR 0x02000000 // Specific address register 2 match.
138 #define RXS_SA3_ADDR 0x01000000 // Specific address register 3 match.
139 #define RXS_SA4_ADDR 0x00800000 // Specific address register 4 match.
140 #define RXS_TYPE_ID 0x00400000 // Type ID match.
141 #define RXS_VLAN_TAG 0x00200000 // VLAN tag detected.
142 #define RXS_PRIORITY_TAG 0x00100000 // Priority tag detected.
143 #define RXS_VLAN_PRIORITY 0x000E0000 // VLAN priority.
144 #define RXS_CFI_IND 0x00010000 // Concatenation format indicator.
145 #define RXS_EOF 0x00008000 // End of frame.
146 #define RXS_SOF 0x00004000 // Start of frame.
147 #define RXS_RBF_OFFSET 0x00003000 // Receive buffer offset mask.
148 #define RXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS.
150 #define EMAC_RSR_BITS (BV(EMAC_BNA) | BV(EMAC_REC) | BV(EMAC_OVR))
151 #define EMAC_TSR_BITS (BV(EMAC_UBR) | BV(EMAC_COL) | BV(EMAC_RLES) | \
152 BV(EMAC_BEX) | BV(EMAC_COMP) | BV(EMAC_UND))
154 typedef struct BufDescriptor
156 volatile uint32_t addr;
157 volatile uint32_t stat;
160 #endif /* ETH_AT91_H */