* Edit these define for your project.
*/
-/// [bytes] Size of the outbound FIFO buffer for port 0. $WIZ$ type = "int"
+/**
+ * Size of the outbound FIFO buffer for port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "2"
+ */
#define CONFIG_UART0_TXBUFSIZE 32
-/// [bytes] Size of the inbound FIFO buffer for port 0. $WIZ$ type = "int"
+/**
+ * Size of the inbound FIFO buffer for port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "2"
+ */
#define CONFIG_UART0_RXBUFSIZE 32
-/// [bytes] Size of the outbound FIFO buffer for port 1. $WIZ$ type = "int"
+/**
+ * Size of the outbound FIFO buffer for port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "2"
+ * $WIZ$ supports = "at91 and not atmega8 and not atmega168 and not atmega32"
+ */
#define CONFIG_UART1_TXBUFSIZE 32
-/// [bytes] Size of the inbound FIFO buffer for port 1. $WIZ$ type = "int"
+/**
+ * Size of the inbound FIFO buffer for port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "2"
+ * $WIZ$ supports = "at91 and not atmega8 and not atmega168 and not atmega32"
+ */
#define CONFIG_UART1_RXBUFSIZE 32
/**
* [bytes] Size of the outbound FIFO buffer for SPI port.
* $WIZ$ type = "int"
+ * $WIZ$ min = "2"
* $WIZ$ supports = "avr"
*/
#define CONFIG_SPI_TXBUFSIZE 32
/**
* [bytes] Size of the inbound FIFO buffer for SPI port.
* $WIZ$ type = "int"
+ * $WIZ$ min = "2"
* $WIZ$ supports = "avr"
*/
#define CONFIG_SPI_RXBUFSIZE 32
-/// [bytes] Size of the outbound FIFO buffer for SPI port 0. $WIZ$ type = "int"
+/**
+ * Size of the outbound FIFO buffer for SPI port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "2"
+ * $WIZ$ supports = "at91"
+ */
#define CONFIG_SPI0_TXBUFSIZE 32
-/// [bytes] Size of the inbound FIFO buffer for SPI port 0. $WIZ$ type = "int"
+/**
+ * Size of the inbound FIFO buffer for SPI port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "2"
+ * $WIZ$ supports = "at91"
+ */
#define CONFIG_SPI0_RXBUFSIZE 32
-/// [bytes] Size of the outbound FIFO buffer for SPI port 1. $WIZ$ type = "int"
+/**
+ * Size of the outbound FIFO buffer for SPI port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "2"
+ * $WIZ$ supports = "at91"
+ */
#define CONFIG_SPI1_TXBUFSIZE 32
-/// [bytes] Size of the inbound FIFO buffer for SPI port 1. $WIZ$ type = "int"
+/**
+ * Size of the inbound FIFO buffer for SPI port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "2"
+ * $WIZ$ supports = "at91"
+ */
#define CONFIG_SPI1_RXBUFSIZE 32
/**
*/
#define CONFIG_SPI_CLOCK_PHASE SPI_SAMPLE_ON_FIRST_EDGE
-/// Default transmit timeout (ms). Set to -1 to disable timeout support. $WIZ$ type = "int"
+/**
+ * Default transmit timeout (ms). Set to -1 to disable timeout support.
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "-1"
+ */
#define CONFIG_SER_TXTIMEOUT -1
-/// Default receive timeout (ms). Set to -1 to disable timeout support. $WIZ$ type = "int"
+/**
+ * Default receive timeout (ms). Set to -1 to disable timeout support.
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "-1"
+ */
#define CONFIG_SER_RXTIMEOUT -1
/// Use RTS/CTS handshake. $WIZ$ type = "boolean"
#define CONFIG_SER_HWHANDSHAKE 0
-/// Default baud rate (set to 0 to disable). $WIZ$ type = "boolean"
-#define CONFIG_SER_DEFBAUDRATE 0
-
-/// Enable ser_gets() and ser_gets_echo(). $WIZ$ type = "boolean"
-#define CONFIG_SER_GETS 0
-
-/// Enable second serial port in emulator. $WIZ$ type = "boolean"
-#define CONFIG_EMUL_UART1 0
+/**
+ * Default baud rate for all serial ports (set to 0 to disable).
+ * $WIZ$ type = "int"
+ * $WIZ$ min = "0"
+ */
+#define CONFIG_SER_DEFBAUDRATE 0UL
-/// For serial debug. $WIZ$ type = "boolean"
+/// Enable strobe pin for serial debug. $WIZ$ type = "boolean"
#define CONFIG_SER_STROBE 0
#endif /* CFG_SER_H */