4 * This file is part of BeRTOS.
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6 * Bertos is free software; you can redistribute it and/or modify
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7 * it under the terms of the GNU General Public License as published by
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8 * the Free Software Foundation; either version 2 of the License, or
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9 * (at your option) any later version.
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11 * This program is distributed in the hope that it will be useful,
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 * GNU General Public License for more details.
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16 * You should have received a copy of the GNU General Public License
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17 * along with this program; if not, write to the Free Software
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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20 * As a special exception, you may use this file as part of a free software
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21 * library without restriction. Specifically, if other files instantiate
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22 * templates or use macros or inline functions from this file, or you compile
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23 * this file and link it with other files to produce an executable, this
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24 * file does not by itself cause the resulting executable to be covered by
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25 * the GNU General Public License. This exception does not however
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26 * invalidate any other reasons why the executable file might be covered by
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27 * the GNU General Public License.
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
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33 * \author Francesco Sacchi <batt@develer.com>
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35 * LPC23xx I/O registers.
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41 #include <cfg/compiler.h>
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43 /* Vectored Interrupt Controller (VIC) */
\r
44 #define VIC_BASE_ADDR 0xFFFFF000
\r
45 #define VICIRQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x000))
\r
46 #define VICFIQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x004))
\r
47 #define VICRawIntr (*(reg32_t *)(VIC_BASE_ADDR + 0x008))
\r
48 #define VICIntSelect (*(reg32_t *)(VIC_BASE_ADDR + 0x00C))
\r
49 #define VICIntEnable (*(reg32_t *)(VIC_BASE_ADDR + 0x010))
\r
50 #define VICIntEnClr (*(reg32_t *)(VIC_BASE_ADDR + 0x014))
\r
51 #define VICSoftInt (*(reg32_t *)(VIC_BASE_ADDR + 0x018))
\r
52 #define VICSoftIntClr (*(reg32_t *)(VIC_BASE_ADDR + 0x01C))
\r
53 #define VICProtection (*(reg32_t *)(VIC_BASE_ADDR + 0x020))
\r
54 #define VICSWPrioMask (*(reg32_t *)(VIC_BASE_ADDR + 0x024))
\r
56 #define VICVectAddr0 (*(reg32_t *)(VIC_BASE_ADDR + 0x100))
\r
57 #define VICVectAddr1 (*(reg32_t *)(VIC_BASE_ADDR + 0x104))
\r
58 #define VICVectAddr2 (*(reg32_t *)(VIC_BASE_ADDR + 0x108))
\r
59 #define VICVectAddr3 (*(reg32_t *)(VIC_BASE_ADDR + 0x10C))
\r
60 #define VICVectAddr4 (*(reg32_t *)(VIC_BASE_ADDR + 0x110))
\r
61 #define VICVectAddr5 (*(reg32_t *)(VIC_BASE_ADDR + 0x114))
\r
62 #define VICVectAddr6 (*(reg32_t *)(VIC_BASE_ADDR + 0x118))
\r
63 #define VICVectAddr7 (*(reg32_t *)(VIC_BASE_ADDR + 0x11C))
\r
64 #define VICVectAddr8 (*(reg32_t *)(VIC_BASE_ADDR + 0x120))
\r
65 #define VICVectAddr9 (*(reg32_t *)(VIC_BASE_ADDR + 0x124))
\r
66 #define VICVectAddr10 (*(reg32_t *)(VIC_BASE_ADDR + 0x128))
\r
67 #define VICVectAddr11 (*(reg32_t *)(VIC_BASE_ADDR + 0x12C))
\r
68 #define VICVectAddr12 (*(reg32_t *)(VIC_BASE_ADDR + 0x130))
\r
69 #define VICVectAddr13 (*(reg32_t *)(VIC_BASE_ADDR + 0x134))
\r
70 #define VICVectAddr14 (*(reg32_t *)(VIC_BASE_ADDR + 0x138))
\r
71 #define VICVectAddr15 (*(reg32_t *)(VIC_BASE_ADDR + 0x13C))
\r
72 #define VICVectAddr16 (*(reg32_t *)(VIC_BASE_ADDR + 0x140))
\r
73 #define VICVectAddr17 (*(reg32_t *)(VIC_BASE_ADDR + 0x144))
\r
74 #define VICVectAddr18 (*(reg32_t *)(VIC_BASE_ADDR + 0x148))
\r
75 #define VICVectAddr19 (*(reg32_t *)(VIC_BASE_ADDR + 0x14C))
\r
76 #define VICVectAddr20 (*(reg32_t *)(VIC_BASE_ADDR + 0x150))
\r
77 #define VICVectAddr21 (*(reg32_t *)(VIC_BASE_ADDR + 0x154))
\r
78 #define VICVectAddr22 (*(reg32_t *)(VIC_BASE_ADDR + 0x158))
\r
79 #define VICVectAddr23 (*(reg32_t *)(VIC_BASE_ADDR + 0x15C))
\r
80 #define VICVectAddr24 (*(reg32_t *)(VIC_BASE_ADDR + 0x160))
\r
81 #define VICVectAddr25 (*(reg32_t *)(VIC_BASE_ADDR + 0x164))
\r
82 #define VICVectAddr26 (*(reg32_t *)(VIC_BASE_ADDR + 0x168))
\r
83 #define VICVectAddr27 (*(reg32_t *)(VIC_BASE_ADDR + 0x16C))
\r
84 #define VICVectAddr28 (*(reg32_t *)(VIC_BASE_ADDR + 0x170))
\r
85 #define VICVectAddr29 (*(reg32_t *)(VIC_BASE_ADDR + 0x174))
\r
86 #define VICVectAddr30 (*(reg32_t *)(VIC_BASE_ADDR + 0x178))
\r
87 #define VICVectAddr31 (*(reg32_t *)(VIC_BASE_ADDR + 0x17C))
\r
89 /* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,
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90 these registers are known as "VICVectPriority(x)". */
\r
91 #define VICVectCntl0 (*(reg32_t *)(VIC_BASE_ADDR + 0x200))
\r
92 #define VICVectCntl1 (*(reg32_t *)(VIC_BASE_ADDR + 0x204))
\r
93 #define VICVectCntl2 (*(reg32_t *)(VIC_BASE_ADDR + 0x208))
\r
94 #define VICVectCntl3 (*(reg32_t *)(VIC_BASE_ADDR + 0x20C))
\r
95 #define VICVectCntl4 (*(reg32_t *)(VIC_BASE_ADDR + 0x210))
\r
96 #define VICVectCntl5 (*(reg32_t *)(VIC_BASE_ADDR + 0x214))
\r
97 #define VICVectCntl6 (*(reg32_t *)(VIC_BASE_ADDR + 0x218))
\r
98 #define VICVectCntl7 (*(reg32_t *)(VIC_BASE_ADDR + 0x21C))
\r
99 #define VICVectCntl8 (*(reg32_t *)(VIC_BASE_ADDR + 0x220))
\r
100 #define VICVectCntl9 (*(reg32_t *)(VIC_BASE_ADDR + 0x224))
\r
101 #define VICVectCntl10 (*(reg32_t *)(VIC_BASE_ADDR + 0x228))
\r
102 #define VICVectCntl11 (*(reg32_t *)(VIC_BASE_ADDR + 0x22C))
\r
103 #define VICVectCntl12 (*(reg32_t *)(VIC_BASE_ADDR + 0x230))
\r
104 #define VICVectCntl13 (*(reg32_t *)(VIC_BASE_ADDR + 0x234))
\r
105 #define VICVectCntl14 (*(reg32_t *)(VIC_BASE_ADDR + 0x238))
\r
106 #define VICVectCntl15 (*(reg32_t *)(VIC_BASE_ADDR + 0x23C))
\r
107 #define VICVectCntl16 (*(reg32_t *)(VIC_BASE_ADDR + 0x240))
\r
108 #define VICVectCntl17 (*(reg32_t *)(VIC_BASE_ADDR + 0x244))
\r
109 #define VICVectCntl18 (*(reg32_t *)(VIC_BASE_ADDR + 0x248))
\r
110 #define VICVectCntl19 (*(reg32_t *)(VIC_BASE_ADDR + 0x24C))
\r
111 #define VICVectCntl20 (*(reg32_t *)(VIC_BASE_ADDR + 0x250))
\r
112 #define VICVectCntl21 (*(reg32_t *)(VIC_BASE_ADDR + 0x254))
\r
113 #define VICVectCntl22 (*(reg32_t *)(VIC_BASE_ADDR + 0x258))
\r
114 #define VICVectCntl23 (*(reg32_t *)(VIC_BASE_ADDR + 0x25C))
\r
115 #define VICVectCntl24 (*(reg32_t *)(VIC_BASE_ADDR + 0x260))
\r
116 #define VICVectCntl25 (*(reg32_t *)(VIC_BASE_ADDR + 0x264))
\r
117 #define VICVectCntl26 (*(reg32_t *)(VIC_BASE_ADDR + 0x268))
\r
118 #define VICVectCntl27 (*(reg32_t *)(VIC_BASE_ADDR + 0x26C))
\r
119 #define VICVectCntl28 (*(reg32_t *)(VIC_BASE_ADDR + 0x270))
\r
120 #define VICVectCntl29 (*(reg32_t *)(VIC_BASE_ADDR + 0x274))
\r
121 #define VICVectCntl30 (*(reg32_t *)(VIC_BASE_ADDR + 0x278))
\r
122 #define VICVectCntl31 (*(reg32_t *)(VIC_BASE_ADDR + 0x27C))
\r
124 #define VICVectAddr (*(reg32_t *)(VIC_BASE_ADDR + 0xF00))
\r
127 /* Pin Connect Block */
\r
128 #define PINSEL_BASE_ADDR 0xE002C000
\r
129 #define PINSEL0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x00))
\r
130 #define PINSEL1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x04))
\r
131 #define PINSEL2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x08))
\r
132 #define PINSEL3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x0C))
\r
133 #define PINSEL4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x10))
\r
134 #define PINSEL5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x14))
\r
135 #define PINSEL6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x18))
\r
136 #define PINSEL7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x1C))
\r
137 #define PINSEL8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x20))
\r
138 #define PINSEL9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x24))
\r
139 #define PINSEL10 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x28))
\r
141 #define PINMODE0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x40))
\r
142 #define PINMODE1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x44))
\r
143 #define PINMODE2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x48))
\r
144 #define PINMODE3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x4C))
\r
145 #define PINMODE4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x50))
\r
146 #define PINMODE5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x54))
\r
147 #define PINMODE6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x58))
\r
148 #define PINMODE7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x5C))
\r
149 #define PINMODE8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x60))
\r
150 #define PINMODE9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x64))
\r
152 /* General Purpose Input/Output (GPIO) */
\r
153 #define GPIO_BASE_ADDR 0xE0028000
\r
154 #define IOPIN0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x00))
\r
155 #define IOSET0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x04))
\r
156 #define IODIR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x08))
\r
157 #define IOCLR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x0C))
\r
158 #define IOPIN1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x10))
\r
159 #define IOSET1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x14))
\r
160 #define IODIR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x18))
\r
161 #define IOCLR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x1C))
\r
163 /* GPIO Interrupt Registers */
\r
164 #define IO0_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x90))
\r
165 #define IO0_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x94))
\r
166 #define IO0_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x84))
\r
167 #define IO0_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x88))
\r
168 #define IO0_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0x8C))
\r
170 #define IO2_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xB0))
\r
171 #define IO2_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xB4))
\r
172 #define IO2_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xA4))
\r
173 #define IO2_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xA8))
\r
174 #define IO2_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0xAC))
\r
176 #define IO_INT_STAT (*(reg32_t *)(GPIO_BASE_ADDR + 0x80))
\r
178 #define PARTCFG_BASE_ADDR 0x3FFF8000
\r
179 #define PARTCFG (*(reg32_t *)(PARTCFG_BASE_ADDR + 0x00))
\r
181 /* Fast I/O setup */
\r
182 #define FIO_BASE_ADDR 0x3FFFC000
\r
183 #define FIO0DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x00))
\r
184 #define FIO0MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x10))
\r
185 #define FIO0PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x14))
\r
186 #define FIO0SET (*(reg32_t *)(FIO_BASE_ADDR + 0x18))
\r
187 #define FIO0CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x1C))
\r
189 #define FIO1DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x20))
\r
190 #define FIO1MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x30))
\r
191 #define FIO1PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x34))
\r
192 #define FIO1SET (*(reg32_t *)(FIO_BASE_ADDR + 0x38))
\r
193 #define FIO1CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x3C))
\r
195 #define FIO2DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x40))
\r
196 #define FIO2MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x50))
\r
197 #define FIO2PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x54))
\r
198 #define FIO2SET (*(reg32_t *)(FIO_BASE_ADDR + 0x58))
\r
199 #define FIO2CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x5C))
\r
201 #define FIO3DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x60))
\r
202 #define FIO3MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x70))
\r
203 #define FIO3PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x74))
\r
204 #define FIO3SET (*(reg32_t *)(FIO_BASE_ADDR + 0x78))
\r
205 #define FIO3CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x7C))
\r
207 #define FIO4DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x80))
\r
208 #define FIO4MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x90))
\r
209 #define FIO4PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x94))
\r
210 #define FIO4SET (*(reg32_t *)(FIO_BASE_ADDR + 0x98))
\r
211 #define FIO4CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x9C))
\r
213 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
\r
214 #define FIO0DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x00))
\r
215 #define FIO1DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x20))
\r
216 #define FIO2DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x40))
\r
217 #define FIO3DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x60))
\r
218 #define FIO4DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x80))
\r
220 #define FIO0DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x01))
\r
221 #define FIO1DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21))
\r
222 #define FIO2DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x41))
\r
223 #define FIO3DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x61))
\r
224 #define FIO4DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x81))
\r
226 #define FIO0DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x02))
\r
227 #define FIO1DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x22))
\r
228 #define FIO2DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x42))
\r
229 #define FIO3DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x62))
\r
230 #define FIO4DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x82))
\r
232 #define FIO0DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x03))
\r
233 #define FIO1DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x23))
\r
234 #define FIO2DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x43))
\r
235 #define FIO3DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x63))
\r
236 #define FIO4DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x83))
\r
238 #define FIO0DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x00))
\r
239 #define FIO1DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x20))
\r
240 #define FIO2DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x40))
\r
241 #define FIO3DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x60))
\r
242 #define FIO4DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x80))
\r
244 #define FIO0DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x02))
\r
245 #define FIO1DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x22))
\r
246 #define FIO2DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x42))
\r
247 #define FIO3DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x62))
\r
248 #define FIO4DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x82))
\r
250 #define FIO0MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x10))
\r
251 #define FIO1MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x30))
\r
252 #define FIO2MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x50))
\r
253 #define FIO3MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x70))
\r
254 #define FIO4MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x90))
\r
256 #define FIO0MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x11))
\r
257 #define FIO1MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21))
\r
258 #define FIO2MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x51))
\r
259 #define FIO3MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x71))
\r
260 #define FIO4MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x91))
\r
262 #define FIO0MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x12))
\r
263 #define FIO1MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x32))
\r
264 #define FIO2MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x52))
\r
265 #define FIO3MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x72))
\r
266 #define FIO4MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x92))
\r
268 #define FIO0MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x13))
\r
269 #define FIO1MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x33))
\r
270 #define FIO2MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x53))
\r
271 #define FIO3MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x73))
\r
272 #define FIO4MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x93))
\r
274 #define FIO0MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x10))
\r
275 #define FIO1MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x30))
\r
276 #define FIO2MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x50))
\r
277 #define FIO3MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x70))
\r
278 #define FIO4MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x90))
\r
280 #define FIO0MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x12))
\r
281 #define FIO1MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x32))
\r
282 #define FIO2MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x52))
\r
283 #define FIO3MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x72))
\r
284 #define FIO4MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x92))
\r
286 #define FIO0PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x14))
\r
287 #define FIO1PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x34))
\r
288 #define FIO2PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x54))
\r
289 #define FIO3PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x74))
\r
290 #define FIO4PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x94))
\r
292 #define FIO0PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x15))
\r
293 #define FIO1PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x25))
\r
294 #define FIO2PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x55))
\r
295 #define FIO3PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x75))
\r
296 #define FIO4PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x95))
\r
298 #define FIO0PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x16))
\r
299 #define FIO1PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x36))
\r
300 #define FIO2PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x56))
\r
301 #define FIO3PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x76))
\r
302 #define FIO4PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x96))
\r
304 #define FIO0PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x17))
\r
305 #define FIO1PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x37))
\r
306 #define FIO2PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x57))
\r
307 #define FIO3PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x77))
\r
308 #define FIO4PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x97))
\r
310 #define FIO0PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x14))
\r
311 #define FIO1PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x34))
\r
312 #define FIO2PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x54))
\r
313 #define FIO3PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x74))
\r
314 #define FIO4PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x94))
\r
316 #define FIO0PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x16))
\r
317 #define FIO1PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x36))
\r
318 #define FIO2PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x56))
\r
319 #define FIO3PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x76))
\r
320 #define FIO4PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x96))
\r
322 #define FIO0SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x18))
\r
323 #define FIO1SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x38))
\r
324 #define FIO2SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x58))
\r
325 #define FIO3SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x78))
\r
326 #define FIO4SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x98))
\r
328 #define FIO0SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x19))
\r
329 #define FIO1SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x29))
\r
330 #define FIO2SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x59))
\r
331 #define FIO3SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x79))
\r
332 #define FIO4SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x99))
\r
334 #define FIO0SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1A))
\r
335 #define FIO1SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3A))
\r
336 #define FIO2SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5A))
\r
337 #define FIO3SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7A))
\r
338 #define FIO4SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9A))
\r
340 #define FIO0SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1B))
\r
341 #define FIO1SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3B))
\r
342 #define FIO2SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5B))
\r
343 #define FIO3SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7B))
\r
344 #define FIO4SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9B))
\r
346 #define FIO0SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x18))
\r
347 #define FIO1SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x38))
\r
348 #define FIO2SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x58))
\r
349 #define FIO3SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x78))
\r
350 #define FIO4SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x98))
\r
352 #define FIO0SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x1A))
\r
353 #define FIO1SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x3A))
\r
354 #define FIO2SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x5A))
\r
355 #define FIO3SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x7A))
\r
356 #define FIO4SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x9A))
\r
358 #define FIO0CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x1C))
\r
359 #define FIO1CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x3C))
\r
360 #define FIO2CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x5C))
\r
361 #define FIO3CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x7C))
\r
362 #define FIO4CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x9C))
\r
364 #define FIO0CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x1D))
\r
365 #define FIO1CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x2D))
\r
366 #define FIO2CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x5D))
\r
367 #define FIO3CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x7D))
\r
368 #define FIO4CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x9D))
\r
370 #define FIO0CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1E))
\r
371 #define FIO1CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3E))
\r
372 #define FIO2CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5E))
\r
373 #define FIO3CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7E))
\r
374 #define FIO4CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9E))
\r
376 #define FIO0CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1F))
\r
377 #define FIO1CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3F))
\r
378 #define FIO2CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5F))
\r
379 #define FIO3CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7F))
\r
380 #define FIO4CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9F))
\r
382 #define FIO0CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x1C))
\r
383 #define FIO1CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x3C))
\r
384 #define FIO2CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x5C))
\r
385 #define FIO3CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x7C))
\r
386 #define FIO4CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x9C))
\r
388 #define FIO0CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x1E))
\r
389 #define FIO1CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x3E))
\r
390 #define FIO2CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x5E))
\r
391 #define FIO3CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x7E))
\r
392 #define FIO4CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x9E))
\r
395 /* System Control Block(SCB) modules include Memory Accelerator Module,
\r
396 Phase Locked Loop, VPB divider, Power Control, External Interrupt,
\r
397 Reset, and Code Security/Debugging */
\r
398 #define SCB_BASE_ADDR 0xE01FC000
\r
400 /* Memory Accelerator Module (MAM) */
\r
401 #define MAMCR (*(reg32_t *)(SCB_BASE_ADDR + 0x000))
\r
402 #define MAMTIM (*(reg32_t *)(SCB_BASE_ADDR + 0x004))
\r
403 #define MEMMAP (*(reg32_t *)(SCB_BASE_ADDR + 0x040))
\r
405 /* Phase Locked Loop (PLL) */
\r
406 #define PLLCON (*(reg32_t *)(SCB_BASE_ADDR + 0x080))
\r
407 #define PLLCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x084))
\r
408 #define PLLSTAT (*(reg32_t *)(SCB_BASE_ADDR + 0x088))
\r
409 #define PLLFEED (*(reg32_t *)(SCB_BASE_ADDR + 0x08C))
\r
411 /* Power Control */
\r
412 #define PCON (*(reg32_t *)(SCB_BASE_ADDR + 0x0C0))
\r
413 #define PCONP (*(reg32_t *)(SCB_BASE_ADDR + 0x0C4))
\r
415 /* Clock Divider */
\r
416 // #define APBDIV (*(reg32_t *)(SCB_BASE_ADDR + 0x100))
\r
417 #define CCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x104))
\r
418 #define USBCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x108))
\r
419 #define CLKSRCSEL (*(reg32_t *)(SCB_BASE_ADDR + 0x10C))
\r
420 #define PCLKSEL0 (*(reg32_t *)(SCB_BASE_ADDR + 0x1A8))
\r
421 #define PCLKSEL1 (*(reg32_t *)(SCB_BASE_ADDR + 0x1AC))
\r
423 /* External Interrupts */
\r
424 #define EXTINT (*(reg32_t *)(SCB_BASE_ADDR + 0x140))
\r
425 #define INTWAKE (*(reg32_t *)(SCB_BASE_ADDR + 0x144))
\r
426 #define EXTMODE (*(reg32_t *)(SCB_BASE_ADDR + 0x148))
\r
427 #define EXTPOLAR (*(reg32_t *)(SCB_BASE_ADDR + 0x14C))
\r
429 /* Reset, reset source identification */
\r
430 #define RSIR (*(reg32_t *)(SCB_BASE_ADDR + 0x180))
\r
432 /* RSID, code security protection */
\r
433 #define CSPR (*(reg32_t *)(SCB_BASE_ADDR + 0x184))
\r
435 /* AHB configuration */
\r
436 #define AHBCFG1 (*(reg32_t *)(SCB_BASE_ADDR + 0x188))
\r
437 #define AHBCFG2 (*(reg32_t *)(SCB_BASE_ADDR + 0x18C))
\r
439 /* System Controls and Status */
\r
440 #define SCS (*(reg32_t *)(SCB_BASE_ADDR + 0x1A0))
\r
442 /* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
\r
443 are for LPC24xx only. */
\r
444 #define STATIC_MEM0_BASE 0x80000000
\r
445 #define STATIC_MEM1_BASE 0x81000000
\r
446 #define STATIC_MEM2_BASE 0x82000000
\r
447 #define STATIC_MEM3_BASE 0x83000000
\r
449 #define DYNAMIC_MEM0_BASE 0xA0000000
\r
450 #define DYNAMIC_MEM1_BASE 0xB0000000
\r
451 #define DYNAMIC_MEM2_BASE 0xC0000000
\r
452 #define DYNAMIC_MEM3_BASE 0xD0000000
\r
454 /* External Memory Controller (EMC) */
\r
455 #define EMC_BASE_ADDR 0xFFE08000
\r
456 #define EMC_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x000))
\r
457 #define EMC_STAT (*(reg32_t *)(EMC_BASE_ADDR + 0x004))
\r
458 #define EMC_CONFIG (*(reg32_t *)(EMC_BASE_ADDR + 0x008))
\r
460 /* Dynamic RAM access registers */
\r
461 #define EMC_DYN_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x020))
\r
462 #define EMC_DYN_RFSH (*(reg32_t *)(EMC_BASE_ADDR + 0x024))
\r
463 #define EMC_DYN_RD_CFG (*(reg32_t *)(EMC_BASE_ADDR + 0x028))
\r
464 #define EMC_DYN_RP (*(reg32_t *)(EMC_BASE_ADDR + 0x030))
\r
465 #define EMC_DYN_RAS (*(reg32_t *)(EMC_BASE_ADDR + 0x034))
\r
466 #define EMC_DYN_SREX (*(reg32_t *)(EMC_BASE_ADDR + 0x038))
\r
467 #define EMC_DYN_APR (*(reg32_t *)(EMC_BASE_ADDR + 0x03C))
\r
468 #define EMC_DYN_DAL (*(reg32_t *)(EMC_BASE_ADDR + 0x040))
\r
469 #define EMC_DYN_WR (*(reg32_t *)(EMC_BASE_ADDR + 0x044))
\r
470 #define EMC_DYN_RC (*(reg32_t *)(EMC_BASE_ADDR + 0x048))
\r
471 #define EMC_DYN_RFC (*(reg32_t *)(EMC_BASE_ADDR + 0x04C))
\r
472 #define EMC_DYN_XSR (*(reg32_t *)(EMC_BASE_ADDR + 0x050))
\r
473 #define EMC_DYN_RRD (*(reg32_t *)(EMC_BASE_ADDR + 0x054))
\r
474 #define EMC_DYN_MRD (*(reg32_t *)(EMC_BASE_ADDR + 0x058))
\r
476 #define EMC_DYN_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x100))
\r
477 #define EMC_DYN_RASCAS0 (*(reg32_t *)(EMC_BASE_ADDR + 0x104))
\r
478 #define EMC_DYN_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x140))
\r
479 #define EMC_DYN_RASCAS1 (*(reg32_t *)(EMC_BASE_ADDR + 0x144))
\r
480 #define EMC_DYN_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x160))
\r
481 #define EMC_DYN_RASCAS2 (*(reg32_t *)(EMC_BASE_ADDR + 0x164))
\r
482 #define EMC_DYN_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x180))
\r
483 #define EMC_DYN_RASCAS3 (*(reg32_t *)(EMC_BASE_ADDR + 0x184))
\r
485 /* static RAM access registers */
\r
486 #define EMC_STA_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x200))
\r
487 #define EMC_STA_WAITWEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x204))
\r
488 #define EMC_STA_WAITOEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x208))
\r
489 #define EMC_STA_WAITRD0 (*(reg32_t *)(EMC_BASE_ADDR + 0x20C))
\r
490 #define EMC_STA_WAITPAGE0 (*(reg32_t *)(EMC_BASE_ADDR + 0x210))
\r
491 #define EMC_STA_WAITWR0 (*(reg32_t *)(EMC_BASE_ADDR + 0x214))
\r
492 #define EMC_STA_WAITTURN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x218))
\r
494 #define EMC_STA_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x220))
\r
495 #define EMC_STA_WAITWEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x224))
\r
496 #define EMC_STA_WAITOEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x228))
\r
497 #define EMC_STA_WAITRD1 (*(reg32_t *)(EMC_BASE_ADDR + 0x22C))
\r
498 #define EMC_STA_WAITPAGE1 (*(reg32_t *)(EMC_BASE_ADDR + 0x230))
\r
499 #define EMC_STA_WAITWR1 (*(reg32_t *)(EMC_BASE_ADDR + 0x234))
\r
500 #define EMC_STA_WAITTURN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x238))
\r
502 #define EMC_STA_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x240))
\r
503 #define EMC_STA_WAITWEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x244))
\r
504 #define EMC_STA_WAITOEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x248))
\r
505 #define EMC_STA_WAITRD2 (*(reg32_t *)(EMC_BASE_ADDR + 0x24C))
\r
506 #define EMC_STA_WAITPAGE2 (*(reg32_t *)(EMC_BASE_ADDR + 0x250))
\r
507 #define EMC_STA_WAITWR2 (*(reg32_t *)(EMC_BASE_ADDR + 0x254))
\r
508 #define EMC_STA_WAITTURN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x258))
\r
510 #define EMC_STA_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x260))
\r
511 #define EMC_STA_WAITWEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x264))
\r
512 #define EMC_STA_WAITOEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x268))
\r
513 #define EMC_STA_WAITRD3 (*(reg32_t *)(EMC_BASE_ADDR + 0x26C))
\r
514 #define EMC_STA_WAITPAGE3 (*(reg32_t *)(EMC_BASE_ADDR + 0x270))
\r
515 #define EMC_STA_WAITWR3 (*(reg32_t *)(EMC_BASE_ADDR + 0x274))
\r
516 #define EMC_STA_WAITTURN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x278))
\r
518 #define EMC_STA_EXT_WAIT (*(reg32_t *)(EMC_BASE_ADDR + 0x880))
\r
522 #define TMR0_BASE_ADDR 0xE0004000
\r
523 #define T0IR (*(reg32_t *)(TMR0_BASE_ADDR + 0x00))
\r
524 #define T0TCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x04))
\r
525 #define T0TC (*(reg32_t *)(TMR0_BASE_ADDR + 0x08))
\r
526 #define T0PR (*(reg32_t *)(TMR0_BASE_ADDR + 0x0C))
\r
527 #define T0PC (*(reg32_t *)(TMR0_BASE_ADDR + 0x10))
\r
528 #define T0MCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x14))
\r
529 #define T0MR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x18))
\r
530 #define T0MR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x1C))
\r
531 #define T0MR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x20))
\r
532 #define T0MR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x24))
\r
533 #define T0CCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x28))
\r
534 #define T0CR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x2C))
\r
535 #define T0CR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x30))
\r
536 #define T0CR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x34))
\r
537 #define T0CR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x38))
\r
538 #define T0EMR (*(reg32_t *)(TMR0_BASE_ADDR + 0x3C))
\r
539 #define T0CTCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x70))
\r
542 #define TMR1_BASE_ADDR 0xE0008000
\r
543 #define T1IR (*(reg32_t *)(TMR1_BASE_ADDR + 0x00))
\r
544 #define T1TCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x04))
\r
545 #define T1TC (*(reg32_t *)(TMR1_BASE_ADDR + 0x08))
\r
546 #define T1PR (*(reg32_t *)(TMR1_BASE_ADDR + 0x0C))
\r
547 #define T1PC (*(reg32_t *)(TMR1_BASE_ADDR + 0x10))
\r
548 #define T1MCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x14))
\r
549 #define T1MR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x18))
\r
550 #define T1MR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x1C))
\r
551 #define T1MR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x20))
\r
552 #define T1MR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x24))
\r
553 #define T1CCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x28))
\r
554 #define T1CR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x2C))
\r
555 #define T1CR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x30))
\r
556 #define T1CR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x34))
\r
557 #define T1CR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x38))
\r
558 #define T1EMR (*(reg32_t *)(TMR1_BASE_ADDR + 0x3C))
\r
559 #define T1CTCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x70))
\r
562 #define TMR2_BASE_ADDR 0xE0070000
\r
563 #define T2IR (*(reg32_t *)(TMR2_BASE_ADDR + 0x00))
\r
564 #define T2TCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x04))
\r
565 #define T2TC (*(reg32_t *)(TMR2_BASE_ADDR + 0x08))
\r
566 #define T2PR (*(reg32_t *)(TMR2_BASE_ADDR + 0x0C))
\r
567 #define T2PC (*(reg32_t *)(TMR2_BASE_ADDR + 0x10))
\r
568 #define T2MCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x14))
\r
569 #define T2MR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x18))
\r
570 #define T2MR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x1C))
\r
571 #define T2MR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x20))
\r
572 #define T2MR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x24))
\r
573 #define T2CCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x28))
\r
574 #define T2CR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x2C))
\r
575 #define T2CR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x30))
\r
576 #define T2CR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x34))
\r
577 #define T2CR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x38))
\r
578 #define T2EMR (*(reg32_t *)(TMR2_BASE_ADDR + 0x3C))
\r
579 #define T2CTCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x70))
\r
582 #define TMR3_BASE_ADDR 0xE0074000
\r
583 #define T3IR (*(reg32_t *)(TMR3_BASE_ADDR + 0x00))
\r
584 #define T3TCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x04))
\r
585 #define T3TC (*(reg32_t *)(TMR3_BASE_ADDR + 0x08))
\r
586 #define T3PR (*(reg32_t *)(TMR3_BASE_ADDR + 0x0C))
\r
587 #define T3PC (*(reg32_t *)(TMR3_BASE_ADDR + 0x10))
\r
588 #define T3MCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x14))
\r
589 #define T3MR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x18))
\r
590 #define T3MR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x1C))
\r
591 #define T3MR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x20))
\r
592 #define T3MR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x24))
\r
593 #define T3CCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x28))
\r
594 #define T3CR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x2C))
\r
595 #define T3CR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x30))
\r
596 #define T3CR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x34))
\r
597 #define T3CR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x38))
\r
598 #define T3EMR (*(reg32_t *)(TMR3_BASE_ADDR + 0x3C))
\r
599 #define T3CTCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x70))
\r
602 /* Pulse Width Modulator (PWM) */
\r
603 #define PWM0_BASE_ADDR 0xE0014000
\r
604 #define PWM0IR (*(reg32_t *)(PWM0_BASE_ADDR + 0x00))
\r
605 #define PWM0TCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x04))
\r
606 #define PWM0TC (*(reg32_t *)(PWM0_BASE_ADDR + 0x08))
\r
607 #define PWM0PR (*(reg32_t *)(PWM0_BASE_ADDR + 0x0C))
\r
608 #define PWM0PC (*(reg32_t *)(PWM0_BASE_ADDR + 0x10))
\r
609 #define PWM0MCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x14))
\r
610 #define PWM0MR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x18))
\r
611 #define PWM0MR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x1C))
\r
612 #define PWM0MR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x20))
\r
613 #define PWM0MR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x24))
\r
614 #define PWM0CCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x28))
\r
615 #define PWM0CR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x2C))
\r
616 #define PWM0CR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x30))
\r
617 #define PWM0CR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x34))
\r
618 #define PWM0CR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x38))
\r
619 #define PWM0EMR (*(reg32_t *)(PWM0_BASE_ADDR + 0x3C))
\r
620 #define PWM0MR4 (*(reg32_t *)(PWM0_BASE_ADDR + 0x40))
\r
621 #define PWM0MR5 (*(reg32_t *)(PWM0_BASE_ADDR + 0x44))
\r
622 #define PWM0MR6 (*(reg32_t *)(PWM0_BASE_ADDR + 0x48))
\r
623 #define PWM0PCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x4C))
\r
624 #define PWM0LER (*(reg32_t *)(PWM0_BASE_ADDR + 0x50))
\r
625 #define PWM0CTCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x70))
\r
627 #define PWM1_BASE_ADDR 0xE0018000
\r
628 #define PWM1IR (*(reg32_t *)(PWM1_BASE_ADDR + 0x00))
\r
629 #define PWM1TCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x04))
\r
630 #define PWM1TC (*(reg32_t *)(PWM1_BASE_ADDR + 0x08))
\r
631 #define PWM1PR (*(reg32_t *)(PWM1_BASE_ADDR + 0x0C))
\r
632 #define PWM1PC (*(reg32_t *)(PWM1_BASE_ADDR + 0x10))
\r
633 #define PWM1MCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x14))
\r
634 #define PWM1MR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x18))
\r
635 #define PWM1MR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x1C))
\r
636 #define PWM1MR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x20))
\r
637 #define PWM1MR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x24))
\r
638 #define PWM1CCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x28))
\r
639 #define PWM1CR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x2C))
\r
640 #define PWM1CR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x30))
\r
641 #define PWM1CR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x34))
\r
642 #define PWM1CR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x38))
\r
643 #define PWM1EMR (*(reg32_t *)(PWM1_BASE_ADDR + 0x3C))
\r
644 #define PWM1MR4 (*(reg32_t *)(PWM1_BASE_ADDR + 0x40))
\r
645 #define PWM1MR5 (*(reg32_t *)(PWM1_BASE_ADDR + 0x44))
\r
646 #define PWM1MR6 (*(reg32_t *)(PWM1_BASE_ADDR + 0x48))
\r
647 #define PWM1PCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x4C))
\r
648 #define PWM1LER (*(reg32_t *)(PWM1_BASE_ADDR + 0x50))
\r
649 #define PWM1CTCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x70))
\r
652 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
\r
653 #define UART0_BASE_ADDR 0xE000C000
\r
654 #define U0RBR (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
\r
655 #define U0THR (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
\r
656 #define U0DLL (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
\r
657 #define U0DLM (*(reg32_t *)(UART0_BASE_ADDR + 0x04))
\r
658 #define U0IER (*(reg32_t *)(UART0_BASE_ADDR + 0x04))
\r
659 #define U0IIR (*(reg32_t *)(UART0_BASE_ADDR + 0x08))
\r
660 #define U0FCR (*(reg32_t *)(UART0_BASE_ADDR + 0x08))
\r
661 #define U0LCR (*(reg32_t *)(UART0_BASE_ADDR + 0x0C))
\r
662 #define U0LSR (*(reg32_t *)(UART0_BASE_ADDR + 0x14))
\r
663 #define U0SCR (*(reg32_t *)(UART0_BASE_ADDR + 0x1C))
\r
664 #define U0ACR (*(reg32_t *)(UART0_BASE_ADDR + 0x20))
\r
665 #define U0ICR (*(reg32_t *)(UART0_BASE_ADDR + 0x24))
\r
666 #define U0FDR (*(reg32_t *)(UART0_BASE_ADDR + 0x28))
\r
667 #define U0TER (*(reg32_t *)(UART0_BASE_ADDR + 0x30))
\r
669 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
\r
670 #define UART1_BASE_ADDR 0xE0010000
\r
671 #define U1RBR (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
\r
672 #define U1THR (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
\r
673 #define U1DLL (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
\r
674 #define U1DLM (*(reg32_t *)(UART1_BASE_ADDR + 0x04))
\r
675 #define U1IER (*(reg32_t *)(UART1_BASE_ADDR + 0x04))
\r
676 #define U1IIR (*(reg32_t *)(UART1_BASE_ADDR + 0x08))
\r
677 #define U1FCR (*(reg32_t *)(UART1_BASE_ADDR + 0x08))
\r
678 #define U1LCR (*(reg32_t *)(UART1_BASE_ADDR + 0x0C))
\r
679 #define U1MCR (*(reg32_t *)(UART1_BASE_ADDR + 0x10))
\r
680 #define U1LSR (*(reg32_t *)(UART1_BASE_ADDR + 0x14))
\r
681 #define U1MSR (*(reg32_t *)(UART1_BASE_ADDR + 0x18))
\r
682 #define U1SCR (*(reg32_t *)(UART1_BASE_ADDR + 0x1C))
\r
683 #define U1ACR (*(reg32_t *)(UART1_BASE_ADDR + 0x20))
\r
684 #define U1FDR (*(reg32_t *)(UART1_BASE_ADDR + 0x28))
\r
685 #define U1TER (*(reg32_t *)(UART1_BASE_ADDR + 0x30))
\r
687 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
\r
688 #define UART2_BASE_ADDR 0xE0078000
\r
689 #define U2RBR (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
\r
690 #define U2THR (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
\r
691 #define U2DLL (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
\r
692 #define U2DLM (*(reg32_t *)(UART2_BASE_ADDR + 0x04))
\r
693 #define U2IER (*(reg32_t *)(UART2_BASE_ADDR + 0x04))
\r
694 #define U2IIR (*(reg32_t *)(UART2_BASE_ADDR + 0x08))
\r
695 #define U2FCR (*(reg32_t *)(UART2_BASE_ADDR + 0x08))
\r
696 #define U2LCR (*(reg32_t *)(UART2_BASE_ADDR + 0x0C))
\r
697 #define U2LSR (*(reg32_t *)(UART2_BASE_ADDR + 0x14))
\r
698 #define U2SCR (*(reg32_t *)(UART2_BASE_ADDR + 0x1C))
\r
699 #define U2ACR (*(reg32_t *)(UART2_BASE_ADDR + 0x20))
\r
700 #define U2ICR (*(reg32_t *)(UART2_BASE_ADDR + 0x24))
\r
701 #define U2FDR (*(reg32_t *)(UART2_BASE_ADDR + 0x28))
\r
702 #define U2TER (*(reg32_t *)(UART2_BASE_ADDR + 0x30))
\r
704 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
\r
705 #define UART3_BASE_ADDR 0xE007C000
\r
706 #define U3RBR (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
\r
707 #define U3THR (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
\r
708 #define U3DLL (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
\r
709 #define U3DLM (*(reg32_t *)(UART3_BASE_ADDR + 0x04))
\r
710 #define U3IER (*(reg32_t *)(UART3_BASE_ADDR + 0x04))
\r
711 #define U3IIR (*(reg32_t *)(UART3_BASE_ADDR + 0x08))
\r
712 #define U3FCR (*(reg32_t *)(UART3_BASE_ADDR + 0x08))
\r
713 #define U3LCR (*(reg32_t *)(UART3_BASE_ADDR + 0x0C))
\r
714 #define U3LSR (*(reg32_t *)(UART3_BASE_ADDR + 0x14))
\r
715 #define U3SCR (*(reg32_t *)(UART3_BASE_ADDR + 0x1C))
\r
716 #define U3ACR (*(reg32_t *)(UART3_BASE_ADDR + 0x20))
\r
717 #define U3ICR (*(reg32_t *)(UART3_BASE_ADDR + 0x24))
\r
718 #define U3FDR (*(reg32_t *)(UART3_BASE_ADDR + 0x28))
\r
719 #define U3TER (*(reg32_t *)(UART3_BASE_ADDR + 0x30))
\r
721 /* I2C Interface 0 */
\r
722 #define I2C0_BASE_ADDR 0xE001C000
\r
723 #define I20CONSET (*(reg32_t *)(I2C0_BASE_ADDR + 0x00))
\r
724 #define I20STAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x04))
\r
725 #define I20DAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x08))
\r
726 #define I20ADR (*(reg32_t *)(I2C0_BASE_ADDR + 0x0C))
\r
727 #define I20SCLH (*(reg32_t *)(I2C0_BASE_ADDR + 0x10))
\r
728 #define I20SCLL (*(reg32_t *)(I2C0_BASE_ADDR + 0x14))
\r
729 #define I20CONCLR (*(reg32_t *)(I2C0_BASE_ADDR + 0x18))
\r
731 /* I2C Interface 1 */
\r
732 #define I2C1_BASE_ADDR 0xE005C000
\r
733 #define I21CONSET (*(reg32_t *)(I2C1_BASE_ADDR + 0x00))
\r
734 #define I21STAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x04))
\r
735 #define I21DAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x08))
\r
736 #define I21ADR (*(reg32_t *)(I2C1_BASE_ADDR + 0x0C))
\r
737 #define I21SCLH (*(reg32_t *)(I2C1_BASE_ADDR + 0x10))
\r
738 #define I21SCLL (*(reg32_t *)(I2C1_BASE_ADDR + 0x14))
\r
739 #define I21CONCLR (*(reg32_t *)(I2C1_BASE_ADDR + 0x18))
\r
741 /* I2C Interface 2 */
\r
742 #define I2C2_BASE_ADDR 0xE0080000
\r
743 #define I22CONSET (*(reg32_t *)(I2C2_BASE_ADDR + 0x00))
\r
744 #define I22STAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x04))
\r
745 #define I22DAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x08))
\r
746 #define I22ADR (*(reg32_t *)(I2C2_BASE_ADDR + 0x0C))
\r
747 #define I22SCLH (*(reg32_t *)(I2C2_BASE_ADDR + 0x10))
\r
748 #define I22SCLL (*(reg32_t *)(I2C2_BASE_ADDR + 0x14))
\r
749 #define I22CONCLR (*(reg32_t *)(I2C2_BASE_ADDR + 0x18))
\r
751 /* SPI0 (Serial Peripheral Interface 0) */
\r
752 #define SPI0_BASE_ADDR 0xE0020000
\r
753 #define S0SPCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x00))
\r
754 #define S0SPSR (*(reg32_t *)(SPI0_BASE_ADDR + 0x04))
\r
755 #define S0SPDR (*(reg32_t *)(SPI0_BASE_ADDR + 0x08))
\r
756 #define S0SPCCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x0C))
\r
757 #define S0SPINT (*(reg32_t *)(SPI0_BASE_ADDR + 0x1C))
\r
759 /* SSP0 Controller */
\r
760 #define SSP0_BASE_ADDR 0xE0068000
\r
761 #define SSP0CR0 (*(reg32_t *)(SSP0_BASE_ADDR + 0x00))
\r
762 #define SSP0CR1 (*(reg32_t *)(SSP0_BASE_ADDR + 0x04))
\r
763 #define SSP0DR (*(reg32_t *)(SSP0_BASE_ADDR + 0x08))
\r
764 #define SSP0SR (*(reg32_t *)(SSP0_BASE_ADDR + 0x0C))
\r
765 #define SSP0CPSR (*(reg32_t *)(SSP0_BASE_ADDR + 0x10))
\r
766 #define SSP0IMSC (*(reg32_t *)(SSP0_BASE_ADDR + 0x14))
\r
767 #define SSP0RIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x18))
\r
768 #define SSP0MIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x1C))
\r
769 #define SSP0ICR (*(reg32_t *)(SSP0_BASE_ADDR + 0x20))
\r
770 #define SSP0DMACR (*(reg32_t *)(SSP0_BASE_ADDR + 0x24))
\r
772 /* SSP1 Controller */
\r
773 #define SSP1_BASE_ADDR 0xE0030000
\r
774 #define SSP1CR0 (*(reg32_t *)(SSP1_BASE_ADDR + 0x00))
\r
775 #define SSP1CR1 (*(reg32_t *)(SSP1_BASE_ADDR + 0x04))
\r
776 #define SSP1DR (*(reg32_t *)(SSP1_BASE_ADDR + 0x08))
\r
777 #define SSP1SR (*(reg32_t *)(SSP1_BASE_ADDR + 0x0C))
\r
778 #define SSP1CPSR (*(reg32_t *)(SSP1_BASE_ADDR + 0x10))
\r
779 #define SSP1IMSC (*(reg32_t *)(SSP1_BASE_ADDR + 0x14))
\r
780 #define SSP1RIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x18))
\r
781 #define SSP1MIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x1C))
\r
782 #define SSP1ICR (*(reg32_t *)(SSP1_BASE_ADDR + 0x20))
\r
783 #define SSP1DMACR (*(reg32_t *)(SSP1_BASE_ADDR + 0x24))
\r
786 /* Real Time Clock */
\r
787 #define RTC_BASE_ADDR 0xE0024000
\r
788 #define RTC_ILR (*(reg32_t *)(RTC_BASE_ADDR + 0x00))
\r
789 #define RTC_CTC (*(reg32_t *)(RTC_BASE_ADDR + 0x04))
\r
790 #define RTC_CCR (*(reg32_t *)(RTC_BASE_ADDR + 0x08))
\r
791 #define RTC_CIIR (*(reg32_t *)(RTC_BASE_ADDR + 0x0C))
\r
792 #define RTC_AMR (*(reg32_t *)(RTC_BASE_ADDR + 0x10))
\r
793 #define RTC_CTIME0 (*(reg32_t *)(RTC_BASE_ADDR + 0x14))
\r
794 #define RTC_CTIME1 (*(reg32_t *)(RTC_BASE_ADDR + 0x18))
\r
795 #define RTC_CTIME2 (*(reg32_t *)(RTC_BASE_ADDR + 0x1C))
\r
796 #define RTC_SEC (*(reg32_t *)(RTC_BASE_ADDR + 0x20))
\r
797 #define RTC_MIN (*(reg32_t *)(RTC_BASE_ADDR + 0x24))
\r
798 #define RTC_HOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x28))
\r
799 #define RTC_DOM (*(reg32_t *)(RTC_BASE_ADDR + 0x2C))
\r
800 #define RTC_DOW (*(reg32_t *)(RTC_BASE_ADDR + 0x30))
\r
801 #define RTC_DOY (*(reg32_t *)(RTC_BASE_ADDR + 0x34))
\r
802 #define RTC_MONTH (*(reg32_t *)(RTC_BASE_ADDR + 0x38))
\r
803 #define RTC_YEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x3C))
\r
804 #define RTC_CISS (*(reg32_t *)(RTC_BASE_ADDR + 0x40))
\r
805 #define RTC_ALSEC (*(reg32_t *)(RTC_BASE_ADDR + 0x60))
\r
806 #define RTC_ALMIN (*(reg32_t *)(RTC_BASE_ADDR + 0x64))
\r
807 #define RTC_ALHOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x68))
\r
808 #define RTC_ALDOM (*(reg32_t *)(RTC_BASE_ADDR + 0x6C))
\r
809 #define RTC_ALDOW (*(reg32_t *)(RTC_BASE_ADDR + 0x70))
\r
810 #define RTC_ALDOY (*(reg32_t *)(RTC_BASE_ADDR + 0x74))
\r
811 #define RTC_ALMON (*(reg32_t *)(RTC_BASE_ADDR + 0x78))
\r
812 #define RTC_ALYEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x7C))
\r
813 #define RTC_PREINT (*(reg32_t *)(RTC_BASE_ADDR + 0x80))
\r
814 #define RTC_PREFRAC (*(reg32_t *)(RTC_BASE_ADDR + 0x84))
\r
817 /* A/D Converter 0 (AD0) */
\r
818 #define AD0_BASE_ADDR 0xE0034000
\r
819 #define AD0CR (*(reg32_t *)(AD0_BASE_ADDR + 0x00))
\r
820 #define AD0GDR (*(reg32_t *)(AD0_BASE_ADDR + 0x04))
\r
821 #define AD0INTEN (*(reg32_t *)(AD0_BASE_ADDR + 0x0C))
\r
822 #define AD0DR0 (*(reg32_t *)(AD0_BASE_ADDR + 0x10))
\r
823 #define AD0DR1 (*(reg32_t *)(AD0_BASE_ADDR + 0x14))
\r
824 #define AD0DR2 (*(reg32_t *)(AD0_BASE_ADDR + 0x18))
\r
825 #define AD0DR3 (*(reg32_t *)(AD0_BASE_ADDR + 0x1C))
\r
826 #define AD0DR4 (*(reg32_t *)(AD0_BASE_ADDR + 0x20))
\r
827 #define AD0DR5 (*(reg32_t *)(AD0_BASE_ADDR + 0x24))
\r
828 #define AD0DR6 (*(reg32_t *)(AD0_BASE_ADDR + 0x28))
\r
829 #define AD0DR7 (*(reg32_t *)(AD0_BASE_ADDR + 0x2C))
\r
830 #define AD0STAT (*(reg32_t *)(AD0_BASE_ADDR + 0x30))
\r
833 /* D/A Converter */
\r
834 #define DAC_BASE_ADDR 0xE006C000
\r
835 #define DACR (*(reg32_t *)(DAC_BASE_ADDR + 0x00))
\r
839 #define WDG_BASE_ADDR 0xE0000000
\r
840 #define WDMOD (*(reg32_t *)(WDG_BASE_ADDR + 0x00))
\r
841 #define WDTC (*(reg32_t *)(WDG_BASE_ADDR + 0x04))
\r
842 #define WDFEED (*(reg32_t *)(WDG_BASE_ADDR + 0x08))
\r
843 #define WDTV (*(reg32_t *)(WDG_BASE_ADDR + 0x0C))
\r
844 #define WDCLKSEL (*(reg32_t *)(WDG_BASE_ADDR + 0x10))
\r
846 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
\r
847 #define CAN_ACCEPT_BASE_ADDR 0xE003C000
\r
848 #define CAN_AFMR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x00))
\r
849 #define CAN_SFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x04))
\r
850 #define CAN_SFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x08))
\r
851 #define CAN_EFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
\r
852 #define CAN_EFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x10))
\r
853 #define CAN_EOT (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x14))
\r
854 #define CAN_LUT_ERR_ADR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x18))
\r
855 #define CAN_LUT_ERR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
\r
857 #define CAN_CENTRAL_BASE_ADDR 0xE0040000
\r
858 #define CAN_TX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x00))
\r
859 #define CAN_RX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x04))
\r
860 #define CAN_MSR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x08))
\r
862 #define CAN1_BASE_ADDR 0xE0044000
\r
863 #define CAN1MOD (*(reg32_t *)(CAN1_BASE_ADDR + 0x00))
\r
864 #define CAN1CMR (*(reg32_t *)(CAN1_BASE_ADDR + 0x04))
\r
865 #define CAN1GSR (*(reg32_t *)(CAN1_BASE_ADDR + 0x08))
\r
866 #define CAN1ICR (*(reg32_t *)(CAN1_BASE_ADDR + 0x0C))
\r
867 #define CAN1IER (*(reg32_t *)(CAN1_BASE_ADDR + 0x10))
\r
868 #define CAN1BTR (*(reg32_t *)(CAN1_BASE_ADDR + 0x14))
\r
869 #define CAN1EWL (*(reg32_t *)(CAN1_BASE_ADDR + 0x18))
\r
870 #define CAN1SR (*(reg32_t *)(CAN1_BASE_ADDR + 0x1C))
\r
871 #define CAN1RFS (*(reg32_t *)(CAN1_BASE_ADDR + 0x20))
\r
872 #define CAN1RID (*(reg32_t *)(CAN1_BASE_ADDR + 0x24))
\r
873 #define CAN1RDA (*(reg32_t *)(CAN1_BASE_ADDR + 0x28))
\r
874 #define CAN1RDB (*(reg32_t *)(CAN1_BASE_ADDR + 0x2C))
\r
876 #define CAN1TFI1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x30))
\r
877 #define CAN1TID1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x34))
\r
878 #define CAN1TDA1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x38))
\r
879 #define CAN1TDB1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x3C))
\r
880 #define CAN1TFI2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x40))
\r
881 #define CAN1TID2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x44))
\r
882 #define CAN1TDA2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x48))
\r
883 #define CAN1TDB2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x4C))
\r
884 #define CAN1TFI3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x50))
\r
885 #define CAN1TID3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x54))
\r
886 #define CAN1TDA3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x58))
\r
887 #define CAN1TDB3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x5C))
\r
889 #define CAN2_BASE_ADDR 0xE0048000
\r
890 #define CAN2MOD (*(reg32_t *)(CAN2_BASE_ADDR + 0x00))
\r
891 #define CAN2CMR (*(reg32_t *)(CAN2_BASE_ADDR + 0x04))
\r
892 #define CAN2GSR (*(reg32_t *)(CAN2_BASE_ADDR + 0x08))
\r
893 #define CAN2ICR (*(reg32_t *)(CAN2_BASE_ADDR + 0x0C))
\r
894 #define CAN2IER (*(reg32_t *)(CAN2_BASE_ADDR + 0x10))
\r
895 #define CAN2BTR (*(reg32_t *)(CAN2_BASE_ADDR + 0x14))
\r
896 #define CAN2EWL (*(reg32_t *)(CAN2_BASE_ADDR + 0x18))
\r
897 #define CAN2SR (*(reg32_t *)(CAN2_BASE_ADDR + 0x1C))
\r
898 #define CAN2RFS (*(reg32_t *)(CAN2_BASE_ADDR + 0x20))
\r
899 #define CAN2RID (*(reg32_t *)(CAN2_BASE_ADDR + 0x24))
\r
900 #define CAN2RDA (*(reg32_t *)(CAN2_BASE_ADDR + 0x28))
\r
901 #define CAN2RDB (*(reg32_t *)(CAN2_BASE_ADDR + 0x2C))
\r
903 #define CAN2TFI1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x30))
\r
904 #define CAN2TID1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x34))
\r
905 #define CAN2TDA1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x38))
\r
906 #define CAN2TDB1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x3C))
\r
907 #define CAN2TFI2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x40))
\r
908 #define CAN2TID2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x44))
\r
909 #define CAN2TDA2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x48))
\r
910 #define CAN2TDB2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x4C))
\r
911 #define CAN2TFI3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x50))
\r
912 #define CAN2TID3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x54))
\r
913 #define CAN2TDA3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x58))
\r
914 #define CAN2TDB3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x5C))
\r
917 /* MultiMedia Card Interface(MCI) Controller */
\r
918 #define MCI_BASE_ADDR 0xE008C000
\r
919 #define MCI_POWER (*(reg32_t *)(MCI_BASE_ADDR + 0x00))
\r
920 #define MCI_CLOCK (*(reg32_t *)(MCI_BASE_ADDR + 0x04))
\r
921 #define MCI_ARGUMENT (*(reg32_t *)(MCI_BASE_ADDR + 0x08))
\r
922 #define MCI_COMMAND (*(reg32_t *)(MCI_BASE_ADDR + 0x0C))
\r
923 #define MCI_RESP_CMD (*(reg32_t *)(MCI_BASE_ADDR + 0x10))
\r
924 #define MCI_RESP0 (*(reg32_t *)(MCI_BASE_ADDR + 0x14))
\r
925 #define MCI_RESP1 (*(reg32_t *)(MCI_BASE_ADDR + 0x18))
\r
926 #define MCI_RESP2 (*(reg32_t *)(MCI_BASE_ADDR + 0x1C))
\r
927 #define MCI_RESP3 (*(reg32_t *)(MCI_BASE_ADDR + 0x20))
\r
928 #define MCI_DATA_TMR (*(reg32_t *)(MCI_BASE_ADDR + 0x24))
\r
929 #define MCI_DATA_LEN (*(reg32_t *)(MCI_BASE_ADDR + 0x28))
\r
930 #define MCI_DATA_CTRL (*(reg32_t *)(MCI_BASE_ADDR + 0x2C))
\r
931 #define MCI_DATA_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x30))
\r
932 #define MCI_STATUS (*(reg32_t *)(MCI_BASE_ADDR + 0x34))
\r
933 #define MCI_CLEAR (*(reg32_t *)(MCI_BASE_ADDR + 0x38))
\r
934 #define MCI_MASK0 (*(reg32_t *)(MCI_BASE_ADDR + 0x3C))
\r
935 #define MCI_MASK1 (*(reg32_t *)(MCI_BASE_ADDR + 0x40))
\r
936 #define MCI_FIFO_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x48))
\r
937 #define MCI_FIFO (*(reg32_t *)(MCI_BASE_ADDR + 0x80))
\r
940 /* I2S Interface Controller (I2S) */
\r
941 #define I2S_BASE_ADDR 0xE0088000
\r
942 #define I2S_DAO (*(reg32_t *)(I2S_BASE_ADDR + 0x00))
\r
943 #define I2S_DAI (*(reg32_t *)(I2S_BASE_ADDR + 0x04))
\r
944 #define I2S_TX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x08))
\r
945 #define I2S_RX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x0C))
\r
946 #define I2S_STATE (*(reg32_t *)(I2S_BASE_ADDR + 0x10))
\r
947 #define I2S_DMA1 (*(reg32_t *)(I2S_BASE_ADDR + 0x14))
\r
948 #define I2S_DMA2 (*(reg32_t *)(I2S_BASE_ADDR + 0x18))
\r
949 #define I2S_IRQ (*(reg32_t *)(I2S_BASE_ADDR + 0x1C))
\r
950 #define I2S_TXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x20))
\r
951 #define I2S_RXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x24))
\r
954 /* General-purpose DMA Controller */
\r
955 #define DMA_BASE_ADDR 0xFFE04000
\r
956 #define GPDMA_INT_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x000))
\r
957 #define GPDMA_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x004))
\r
958 #define GPDMA_INT_TCCLR (*(reg32_t *)(DMA_BASE_ADDR + 0x008))
\r
959 #define GPDMA_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x00C))
\r
960 #define GPDMA_INT_ERR_CLR (*(reg32_t *)(DMA_BASE_ADDR + 0x010))
\r
961 #define GPDMA_RAW_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x014))
\r
962 #define GPDMA_RAW_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x018))
\r
963 #define GPDMA_ENABLED_CHNS (*(reg32_t *)(DMA_BASE_ADDR + 0x01C))
\r
964 #define GPDMA_SOFT_BREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x020))
\r
965 #define GPDMA_SOFT_SREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x024))
\r
966 #define GPDMA_SOFT_LBREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x028))
\r
967 #define GPDMA_SOFT_LSREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x02C))
\r
968 #define GPDMA_CONFIG (*(reg32_t *)(DMA_BASE_ADDR + 0x030))
\r
969 #define GPDMA_SYNC (*(reg32_t *)(DMA_BASE_ADDR + 0x034))
\r
971 /* DMA channel 0 registers */
\r
972 #define GPDMA_CH0_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x100))
\r
973 #define GPDMA_CH0_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x104))
\r
974 #define GPDMA_CH0_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x108))
\r
975 #define GPDMA_CH0_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x10C))
\r
976 #define GPDMA_CH0_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x110))
\r
978 /* DMA channel 1 registers */
\r
979 #define GPDMA_CH1_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x120))
\r
980 #define GPDMA_CH1_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x124))
\r
981 #define GPDMA_CH1_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x128))
\r
982 #define GPDMA_CH1_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x12C))
\r
983 #define GPDMA_CH1_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x130))
\r
986 /* USB Controller */
\r
987 #define USB_INT_BASE_ADDR 0xE01FC1C0
\r
988 #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
\r
990 #define USB_INT_STAT (*(reg32_t *)(USB_INT_BASE_ADDR + 0x00))
\r
992 /* USB Device Interrupt Registers */
\r
993 #define DEV_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x00))
\r
994 #define DEV_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x04))
\r
995 #define DEV_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x08))
\r
996 #define DEV_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x0C))
\r
997 #define DEV_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x2C))
\r
999 /* USB Device Endpoint Interrupt Registers */
\r
1000 #define EP_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x30))
\r
1001 #define EP_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x34))
\r
1002 #define EP_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x38))
\r
1003 #define EP_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x3C))
\r
1004 #define EP_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x40))
\r
1006 /* USB Device Endpoint Realization Registers */
\r
1007 #define REALIZE_EP (*(reg32_t *)(USB_BASE_ADDR + 0x44))
\r
1008 #define EP_INDEX (*(reg32_t *)(USB_BASE_ADDR + 0x48))
\r
1009 #define MAXPACKET_SIZE (*(reg32_t *)(USB_BASE_ADDR + 0x4C))
\r
1011 /* USB Device Command Reagisters */
\r
1012 #define CMD_CODE (*(reg32_t *)(USB_BASE_ADDR + 0x10))
\r
1013 #define CMD_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x14))
\r
1015 /* USB Device Data Transfer Registers */
\r
1016 #define RX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x18))
\r
1017 #define TX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x1C))
\r
1018 #define RX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x20))
\r
1019 #define TX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x24))
\r
1020 #define USB_CTRL (*(reg32_t *)(USB_BASE_ADDR + 0x28))
\r
1022 /* USB Device DMA Registers */
\r
1023 #define DMA_REQ_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x50))
\r
1024 #define DMA_REQ_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x54))
\r
1025 #define DMA_REQ_SET (*(reg32_t *)(USB_BASE_ADDR + 0x58))
\r
1026 #define UDCA_HEAD (*(reg32_t *)(USB_BASE_ADDR + 0x80))
\r
1027 #define EP_DMA_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x84))
\r
1028 #define EP_DMA_EN (*(reg32_t *)(USB_BASE_ADDR + 0x88))
\r
1029 #define EP_DMA_DIS (*(reg32_t *)(USB_BASE_ADDR + 0x8C))
\r
1030 #define DMA_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x90))
\r
1031 #define DMA_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x94))
\r
1032 #define EOT_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xA0))
\r
1033 #define EOT_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xA4))
\r
1034 #define EOT_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xA8))
\r
1035 #define NDD_REQ_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xAC))
\r
1036 #define NDD_REQ_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xB0))
\r
1037 #define NDD_REQ_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xB4))
\r
1038 #define SYS_ERR_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xB8))
\r
1039 #define SYS_ERR_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xBC))
\r
1040 #define SYS_ERR_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xC0))
\r
1042 /* USB Host and OTG registers are for LPC24xx only */
\r
1043 /* USB Host Controller */
\r
1044 #define USBHC_BASE_ADDR 0xFFE0C000
\r
1045 #define HC_REVISION (*(reg32_t *)(USBHC_BASE_ADDR + 0x00))
\r
1046 #define HC_CONTROL (*(reg32_t *)(USBHC_BASE_ADDR + 0x04))
\r
1047 #define HC_CMD_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x08))
\r
1048 #define HC_INT_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x0C))
\r
1049 #define HC_INT_EN (*(reg32_t *)(USBHC_BASE_ADDR + 0x10))
\r
1050 #define HC_INT_DIS (*(reg32_t *)(USBHC_BASE_ADDR + 0x14))
\r
1051 #define HC_HCCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x18))
\r
1052 #define HC_PERIOD_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x1C))
\r
1053 #define HC_CTRL_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x20))
\r
1054 #define HC_CTRL_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x24))
\r
1055 #define HC_BULK_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x28))
\r
1056 #define HC_BULK_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x2C))
\r
1057 #define HC_DONE_HEAD (*(reg32_t *)(USBHC_BASE_ADDR + 0x30))
\r
1058 #define HC_FM_INTERVAL (*(reg32_t *)(USBHC_BASE_ADDR + 0x34))
\r
1059 #define HC_FM_REMAINING (*(reg32_t *)(USBHC_BASE_ADDR + 0x38))
\r
1060 #define HC_FM_NUMBER (*(reg32_t *)(USBHC_BASE_ADDR + 0x3C))
\r
1061 #define HC_PERIOD_START (*(reg32_t *)(USBHC_BASE_ADDR + 0x40))
\r
1062 #define HC_LS_THRHLD (*(reg32_t *)(USBHC_BASE_ADDR + 0x44))
\r
1063 #define HC_RH_DESCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x48))
\r
1064 #define HC_RH_DESCB (*(reg32_t *)(USBHC_BASE_ADDR + 0x4C))
\r
1065 #define HC_RH_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x50))
\r
1066 #define HC_RH_PORT_STAT1 (*(reg32_t *)(USBHC_BASE_ADDR + 0x54))
\r
1067 #define HC_RH_PORT_STAT2 (*(reg32_t *)(USBHC_BASE_ADDR + 0x58))
\r
1069 /* USB OTG Controller */
\r
1070 #define USBOTG_BASE_ADDR 0xFFE0C100
\r
1071 #define OTG_INT_STAT (*(reg32_t *)(USBOTG_BASE_ADDR + 0x00))
\r
1072 #define OTG_INT_EN (*(reg32_t *)(USBOTG_BASE_ADDR + 0x04))
\r
1073 #define OTG_INT_SET (*(reg32_t *)(USBOTG_BASE_ADDR + 0x08))
\r
1074 #define OTG_INT_CLR (*(reg32_t *)(USBOTG_BASE_ADDR + 0x0C))
\r
1075 /* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
\r
1076 #define OTG_STAT_CTRL (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10))
\r
1077 #define OTG_TIMER (*(reg32_t *)(USBOTG_BASE_ADDR + 0x14))
\r
1079 #define USBOTG_I2C_BASE_ADDR 0xFFE0C300
\r
1080 #define OTG_I2C_RX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00))
\r
1081 #define OTG_I2C_TX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00))
\r
1082 #define OTG_I2C_STS (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x04))
\r
1083 #define OTG_I2C_CTL (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x08))
\r
1084 #define OTG_I2C_CLKHI (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x0C))
\r
1085 #define OTG_I2C_CLKLO (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x10))
\r
1087 /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
\r
1088 OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
\r
1089 #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
\r
1090 #define OTG_CLK_CTRL (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04))
\r
1091 #define OTG_CLK_STAT (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08))
\r
1093 /* Note: below three register name convention is for LPC23xx USB device only, match
\r
1094 with the spec. update in USB Device Section. */
\r
1095 #define USBPortSel (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10))
\r
1096 #define USBClkCtrl (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04))
\r
1097 #define USBClkSt (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08))
\r
1099 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
\r
1100 #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
\r
1101 #define MAC_MAC1 (*(reg32_t *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
\r
1102 #define MAC_MAC2 (*(reg32_t *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
\r
1103 #define MAC_IPGT (*(reg32_t *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
\r
1104 #define MAC_IPGR (*(reg32_t *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
\r
1105 #define MAC_CLRT (*(reg32_t *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
\r
1106 #define MAC_MAXF (*(reg32_t *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
\r
1107 #define MAC_SUPP (*(reg32_t *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
\r
1108 #define MAC_TEST (*(reg32_t *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
\r
1109 #define MAC_MCFG (*(reg32_t *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
\r
1110 #define MAC_MCMD (*(reg32_t *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
\r
1111 #define MAC_MADR (*(reg32_t *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
\r
1112 #define MAC_MWTD (*(reg32_t *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
\r
1113 #define MAC_MRDD (*(reg32_t *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
\r
1114 #define MAC_MIND (*(reg32_t *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
\r
1116 #define MAC_SA0 (*(reg32_t *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
\r
1117 #define MAC_SA1 (*(reg32_t *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
\r
1118 #define MAC_SA2 (*(reg32_t *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
\r
1120 #define MAC_COMMAND (*(reg32_t *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
\r
1121 #define MAC_STATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
\r
1122 #define MAC_RXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
\r
1123 #define MAC_RXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
\r
1124 #define MAC_RXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
\r
1125 #define MAC_RXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
\r
1126 #define MAC_RXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
\r
1127 #define MAC_TXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
\r
1128 #define MAC_TXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
\r
1129 #define MAC_TXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
\r
1130 #define MAC_TXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
\r
1131 #define MAC_TXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
\r
1133 #define MAC_TSV0 (*(reg32_t *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
\r
1134 #define MAC_TSV1 (*(reg32_t *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
\r
1135 #define MAC_RSV (*(reg32_t *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
\r
1137 #define MAC_FLOWCONTROLCNT (*(reg32_t *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
\r
1138 #define MAC_FLOWCONTROLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
\r
1140 #define MAC_RXFILTERCTRL (*(reg32_t *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
\r
1141 #define MAC_RXFILTERWOLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
\r
1142 #define MAC_RXFILTERWOLCLR (*(reg32_t *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
\r
1144 #define MAC_HASHFILTERL (*(reg32_t *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
\r
1145 #define MAC_HASHFILTERH (*(reg32_t *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
\r
1147 #define MAC_INTSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
\r
1148 #define MAC_INTENABLE (*(reg32_t *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
\r
1149 #define MAC_INTCLEAR (*(reg32_t *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
\r
1150 #define MAC_INTSET (*(reg32_t *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
\r
1152 #define MAC_POWERDOWN (*(reg32_t *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
\r
1153 #define MAC_MODULEID (*(reg32_t *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
\r
1155 #endif /* LPC23XX_H */
\r
projects / bertos.git / blob