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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 Synchronous Serial Interface (SSI) driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include "cfg/compiler.h"
39 #include "cfg/debug.h"
41 #include <string.h> /* memset() */
45 /* SSI clocking informations (CPSDVSR + SCR) */
53 * Evaluate the SSI clock prescale (SSICPSR) and SSI serial clock rate (SCR).
55 INLINE struct SSIClock
56 lm3s_ssiPrescale(unsigned int bitrate)
60 for (ret.cpsdvsr = 2, ret.scr = CPU_FREQ / bitrate / ret.cpsdvsr - 1;
61 ret.scr > 255; ret.cpsdvsr += 2);
62 ASSERT(ret.cpsdvsr < 255);
68 * Initialize the SSI interface.
70 * Return 0 in case of success, a negative value otherwise.
72 int lm3s_ssiOpen(uint32_t addr, uint32_t frame, int mode,
73 int bitrate, uint32_t data_width)
75 struct SSIClock ssi_clock;
77 ASSERT(addr == SSI0_BASE || addr == SSI1_BASE);
78 /* Configure the SSI operating mode */
81 /* SSI Slave Mode Output Disable */
82 case SSI_MODE_SLAVE_OD:
83 HWREG(addr + SSI_O_CR1) = SSI_CR1_SOD;
87 HWREG(addr + SSI_O_CR1) = SSI_CR1_MS;
91 HWREG(addr + SSI_O_CR1) = 0;
97 /* Configure the peripheral clock and frame format */
98 ssi_clock = lm3s_ssiPrescale(bitrate);
99 HWREG(addr + SSI_O_CPSR) = ssi_clock.cpsdvsr;
100 HWREG(addr + SSI_O_CR0) =
101 (ssi_clock.scr << 8) |
103 (frame & SSI_CR0_FRF_M) |
105 /* Enable the SSI interface */
106 HWREG(addr + SSI_O_CR1) |= SSI_CR1_SSE;
112 * Write data to the SSI bus.
114 * Return the number of bytes written to the bus.
116 static size_t lm3s_ssiWrite(struct KFile *fd, const void *buf, size_t size)
118 LM3SSSI *fds = LM3SSSI_CAST(fd);
119 const char *p = (const char *)buf;
126 if (fds->flags & LM3S_SSI_NONBLOCK)
128 if (!lm3s_ssiWriteFrameNonBlocking(fds->addr,
133 lm3s_ssiWriteFrame(fds->addr, frame);
140 * Read data from the SSI bus.
142 * Return the number of bytes read from the bus.
144 static size_t lm3s_ssiRead(struct KFile *fd, void *buf, size_t size)
146 LM3SSSI *fds = LM3SSSI_CAST(fd);
148 uint8_t *p = (uint8_t *)buf;
154 if (fds->flags & LM3S_SSI_NONBLOCK)
156 if (!lm3s_ssiReadFrameNonBlocking(fds->addr, &frame))
160 lm3s_ssiReadFrame(fds->addr, &frame);
161 *p++ = (uint8_t)frame;
168 /* Wait for data in the TX FIFO being actually transmitted */
169 static int lm3s_ssiFlush(struct KFile *fd)
171 LM3SSSI *fds = LM3SSSI_CAST(fd);
173 while (!lm3s_ssiTxDone(fds->addr))
178 /* Disable the SSI interface */
179 static int lm3s_ssiClose(struct KFile *fd)
181 LM3SSSI *fds = LM3SSSI_CAST(fd);
184 HWREG(fds->addr + SSI_O_CR1) &= ~SSI_CR1_SSE;
189 * Initialize a LM3S SSI driver.
191 void lm3s_ssiInit(struct LM3SSSI *fds, uint32_t addr, uint32_t frame, int mode,
192 int bitrate, uint32_t data_width)
194 memset(fds, 0, sizeof(*fds));
195 DB(fds->fd._type = KFT_LM3SSSI);
197 /* TODO: only 8-bit frame size is supported */
198 ASSERT(data_width == 8);
200 fds->fd.write = lm3s_ssiWrite;
201 fds->fd.read = lm3s_ssiRead;
202 fds->fd.close = lm3s_ssiClose;
203 fds->fd.flush = lm3s_ssiFlush;
206 lm3s_ssiOpen(addr, frame, mode, bitrate, data_width);