bertos/cpu/cortex-m3/drv/hsmci_sam3.c

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  31  *
  32  * \brief HSMCI driver implementation.
  33  *
  34  * \author Daniele Basile <asterix@develer.com>
  35  */
  36
  37
  38 #include "hsmci_sam3.h"
  39 #include "hw/hw_sd.h"
  40
  41 #include <drv/timer.h>
  42 #include <drv/irq_cm3.h>
  43 #include <drv/dmac_sam3.h>
  44
  45 #include <mware/event.h>
  46
  47 #include <cpu/irq.h>
  48
  49 #include <io/cm3.h>
  50
  51
  52 #define HSMCI_CLK_DIV(RATE)     ((CPU_FREQ / (RATE << 1)) - 1)
  53
  54
  55 #define HSMCI_RESP_ERROR_MASK   (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
  56           | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
  57
  58 #define HSMCI_DATA_ERROR_MASK   (BV(HSMCI_SR_DCRCE) | BV(HSMCI_SR_DTOE))
  59
  60 #define HSMCI_READY_MASK     (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY))
  61 #define HSMCI_WAIT()\
  62         do { \
  63                 cpu_relax(); \
  64         } while (!(HSMCI_SR & BV(HSMCI_SR_CMDRDY)))
  65
  66
  67 #define HSMCI_WAIT_DATA_RDY()\
  68         do { \
  69                 cpu_relax(); \
  70         } while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY)))
  71
  72
  73 #define HSMCI_DMAC_CH    3
  74
  75
  76 void hsmci_readResp(uint32_t *resp, size_t len)
  77 {
  78         ASSERT(resp);
  79
  80         for (size_t i = 0; i < len ; i++)
  81                 resp[i] = HSMCI_RSPR;
  82 }
  83
  84 bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
  85 {
  86         HSMCI_WAIT();
  87
  88         HSMCI_ARGR = argument;
  89         HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT);
  90
  91         uint32_t status = HSMCI_SR;
  92         while (!(status & BV(HSMCI_SR_CMDRDY)))
  93         {
  94                 if (status & HSMCI_RESP_ERROR_MASK)
  95                         return status;
  96
  97                 cpu_relax();
  98
  99                 status = HSMCI_SR;
 100         }
 101
 102         return 0;
 103 }
 104
 105 #define HSMCI_WRITE_DMAC_CFG  (BV(DMAC_CFG_DST_H2SEL) | \
 106                                                            BV(DMAC_CFG_SOD) | \
 107                                                      ((0 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
 108                                                       (0 & DMAC_CFG_SRC_PER_MASK))
 109
 110 #define HSMCI_WRITE_DMAC_CTRLB  (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | \
 111                                                                 DMAC_CTRLB_FC_MEM2PER_DMA_FC | \
 112                                                                 DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING)
 113
 114 #define HSMCI_WRITE_DMAC_CTRLA  (DMAC_CTRLA_SRC_WIDTH_WORD | \
 115                                                                 DMAC_CTRLA_DST_WIDTH_WORD)
 116
 117 #define HSMCI_READ_DMAC_CFG  (BV(DMAC_CFG_SRC_H2SEL) | \
 118                                                           BV(DMAC_CFG_SOD) | \
 119                                                         ((0 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
 120                                                          (0 & DMAC_CFG_SRC_PER_MASK))
 121
 122 #define HSMCI_READ_DMAC_CTRLB  (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | \
 123                                                                 DMAC_CTRLB_FC_PER2MEM_DMA_FC | \
 124                                                                 DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED)
 125
 126 #define HSMCI_READ_DMAC_CTRLA  (DMAC_CTRLA_SRC_WIDTH_WORD | \
 127                                                                 DMAC_CTRLA_DST_WIDTH_WORD)
 128
 129
 130 void hsmci_write(const uint32_t *buf, size_t word_num, size_t blk_size)
 131 {
 132         HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
 133         HSMCI_BLKR = (blk_size << HSMCI_BLKR_BLKLEN_SHIFT) & ~0x30000;
 134
 135         dmac_setSources(HSMCI_DMAC_CH, (uint32_t)buf, (uint32_t)&HSMCI_TDR);
 136         dmac_configureDmac(HSMCI_DMAC_CH, word_num, HSMCI_WRITE_DMAC_CFG, HSMCI_WRITE_DMAC_CTRLA, HSMCI_WRITE_DMAC_CTRLB);
 137         dmac_start(HSMCI_DMAC_CH);
 138 }
 139
 140 void hsmci_read(uint32_t *buf, size_t word_num, size_t blk_size)
 141 {
 142         HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
 143         HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
 144
 145         dmac_setSources(HSMCI_DMAC_CH, (uint32_t)&HSMCI_RDR, (uint32_t)buf);
 146         dmac_configureDmac(HSMCI_DMAC_CH, word_num, HSMCI_READ_DMAC_CFG, HSMCI_READ_DMAC_CTRLA, HSMCI_READ_DMAC_CTRLB);
 147         dmac_start(HSMCI_DMAC_CH);
 148 }
 149
 150
 151 void hsmci_waitTransfer(void)
 152 {
 153         while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE)))
 154                 cpu_relax();
 155 }
 156
 157 void hsmci_setSpeed(uint32_t data_rate, int flag)
 158 {
 159         if (flag & HSMCI_HS_MODE)
 160                 HSMCI_CFG |= BV(HSMCI_CFG_HSMODE);
 161         else
 162                 HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE);
 163
 164         HSMCI_DTOR = 0xF8 | HSMCI_DTOR_DTOMUL_1;
 165         HSMCI_CSTOR = 0xF8 | HSMCI_CSTOR_CSTOMUL_1;
 166         HSMCI_MR = HSMCI_CLK_DIV(data_rate) | BV(HSMCI_MR_RDPROOF) | BV(HSMCI_MR_WRPROOF);
 167
 168         timer_delay(10);
 169 }
 170
 171 void hsmci_init(Hsmci *hsmci)
 172 {
 173         (void)hsmci;
 174
 175         SD_PIN_INIT();
 176
 177         pmc_periphEnable(HSMCI_ID);
 178         HSMCI_CR = BV(HSMCI_CR_SWRST);
 179         HSMCI_CR = BV(HSMCI_CR_PWSDIS) | BV(HSMCI_CR_MCIDIS);
 180         HSMCI_IDR = 0xFFFFFFFF;
 181
 182         HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576;
 183         HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576;
 184         HSMCI_MR = HSMCI_CLK_DIV(HSMCI_INIT_SPEED) | BV(HSMCI_MR_RDPROOF) | BV(HSMCI_MR_WRPROOF);
 185         HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL);
 186
 187         HSMCI_CR = BV(HSMCI_CR_MCIEN);
 188         HSMCI_DMA = 0;
 189
 190         dmac_enableCh(HSMCI_DMAC_CH, NULL);
 191 }