4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S debug support (implementation).
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/cfg_debug.h>
39 #include <cfg/macros.h> /* for BV() */
40 #include <drv/clock_lm3s.h> /* lm3s_busyWait() */
41 #include <drv/gpio_lm3s.h>
42 #include <drv/ser_lm3s.h>
43 #include "kdebug_lm3s.h"
45 #if CONFIG_KDEBUG_PORT == KDEBUG_PORT_DBGU
47 #if CONFIG_KDEBUG_PORT == 0
48 #define UART_BASE UART0_BASE
49 #define UART_GPIO_BASE GPIO_PORTA_BASE
50 #define UART_PINS (BV(1) | BV(0))
51 #define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOA
52 #elif CONFIG_KDEBUG_PORT == 1
53 #define UART_BASE UART1_BASE
54 #define UART_GPIO_BASE GPIO_PORTD_BASE
55 #define UART_PINS (BV(3) | BV(2))
56 #define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOD
57 #elif CONFIG_KDEBUG_PORT == 2
58 #define UART_BASE UART2_BASE
59 #define UART_GPIO_BASE GPIO_PORTG_BASE
60 #define UART_PINS (BV(1) | BV(0))
61 #define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOG
63 #error "UART port not supported in this board"
66 #define KDBG_WAIT_READY() while (!lm3s_uartReady(UART_BASE)) {}
67 #define KDBG_WAIT_TXDONE() while (!lm3s_uartTxDone(UART_BASE)) {}
69 #define KDBG_WRITE_CHAR(c) do { lm3s_uartPutCharNonBlocking(UART_BASE, c); } while(0)
71 /* Debug unit is used only for debug purposes so does not generate interrupts. */
72 #define KDBG_MASK_IRQ(old) do { (void)old; } while(0)
74 /* Debug unit is used only for debug purposes so does not generate interrupts. */
75 #define KDBG_RESTORE_IRQ(old) do { (void)old; } while(0)
77 typedef uint32_t kdbg_irqsave_t;
80 #error CONFIG_KDEBUG_PORT should be KDEBUG_PORT_DBGU
83 INLINE void uart_hw_config(void)
85 unsigned long div, baud = CONFIG_KDEBUG_BAUDRATE;
86 bool hi_speed = false;
88 if (baud * 16 > CPU_FREQ)
93 div = (CPU_FREQ * 8 / baud + 1) / 2;
95 lm3s_uartDisable(UART_BASE);
97 HWREG(UART_BASE + UART_O_CTL) |= UART_CTL_HSE;
99 HWREG(UART_BASE + UART_O_CTL) &= ~UART_CTL_HSE;
100 /* Set the baud rate */
101 HWREG(UART_BASE + UART_O_IBRD) = div / 64;
102 HWREG(UART_BASE + UART_O_FBRD) = div % 64;
103 /* Set word lenght and parity */
104 HWREG(UART_BASE + UART_O_LCRH) = UART_LCRH_WLEN_8;
105 lm3s_uartClear(UART_BASE);
106 lm3s_uartEnable(UART_BASE);
109 INLINE void kdbg_hw_init(void)
111 uint32_t reg_clock = 1 << CONFIG_KDEBUG_PORT;
113 /* Enable the peripheral clock */
114 SYSCTL_RCGC1_R |= reg_clock;
115 SYSCTL_RCGC2_R |= UART_REG_SYSCTL;
118 /* Configure GPIO pins to work as UART pins */
119 lm3s_gpioPinConfig(UART_GPIO_BASE, UART_PINS,
120 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
122 /* Low-level UART configuration */