bertos/cpu/cortex-m3/drv/nand_sam3.c

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  29  * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
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  32  *
  33  * \brief NAND driver hardware implementation for SAM3's static memory controller.
  34  *
  35  * \author Stefano Fedrigo <aleph@develer.com>
  36  */
  37
  38 #include <drv/nand.h>
  39 #include <cfg/log.h>
  40 #include <io/sam3.h>
  41 #include <drv/timer.h>
  42 #include <cpu/power.h> // cpu_relax()
  43
  44
  45 /*
  46  * PIO definitions.
  47  */
  48 #define NAND_PIN_CE        BV(6)
  49 #define NAND_PIN_RB        BV(2)
  50 #define NAND_PINS_PORTA    (NAND_PIN_CE | NAND_PIN_RB)
  51 #define NAND_PERIPH_PORTA  PIO_PERIPH_B
  52
  53 #define NAND_PIN_OE        BV(19)
  54 #define NAND_PIN_WE        BV(20)
  55 #define NAND_PIN_IO        0x0000FFFF
  56 #define NAND_PINS_PORTC    (NAND_PIN_OE | NAND_PIN_WE | NAND_PIN_IO)
  57 #define NAND_PERIPH_PORTC  PIO_PERIPH_A
  58
  59 #define NAND_PIN_CLE       BV(9)
  60 #define NAND_PIN_ALE       BV(8)
  61 #define NAND_PINS_PORTD    (NAND_PIN_CLE | NAND_PIN_ALE)
  62 #define NAND_PERIPH_PORTD  PIO_PERIPH_A
  63
  64
  65 /*
  66  * Wait for edge transition of READY/BUSY NAND
  67  * signal.
  68  * Return true for edge detection, false in case of timeout.
  69  */
  70 bool nand_waitReadyBusy(UNUSED_ARG(Nand *, chip), time_t timeout)
  71 {
  72         time_t start = timer_clock();
  73
  74         while (!(SMC_SR & SMC_SR_RB_EDGE0))
  75         {
  76                 cpu_relax();
  77                 if (timer_clock() - start > timeout)
  78                 {
  79                         LOG_INFO("nand: R/B timeout\n");
  80                         return false;
  81                 }
  82         }
  83
  84         return true;
  85 }
  86
  87
  88 /*
  89  * Wait for transfer to complete until timeout.
  90  * If transfer completes return true, false in case of timeout.
  91  */
  92 bool nand_waitTransferComplete(UNUSED_ARG(Nand *, chip), time_t timeout)
  93 {
  94         time_t start = timer_clock();
  95
  96         while (!(SMC_SR & SMC_SR_XFRDONE))
  97         {
  98                 cpu_relax();
  99                 if (timer_clock() - start > timeout)
 100                 {
 101                         LOG_INFO("nand: xfer complete timeout\n");
 102                         return false;
 103                 }
 104         }
 105
 106         return true;
 107 }
 108
 109
 110 /*
 111  * Send command to NAND and wait for completion.
 112  */
 113 void nand_sendCommand(Nand *chip,
 114                 uint32_t cmd1, uint32_t cmd2,
 115                 int num_cycles, uint32_t cycle0, uint32_t cycle1234)
 116 {
 117         reg32_t *cmd_addr;
 118         uint32_t cmd_val;
 119
 120         while (HWREG(NFC_CMD_BASE_ADDR + NFC_CMD_NFCCMD) & 0x8000000);
 121
 122         if (num_cycles == 5)
 123                 SMC_ADDR = cycle0;
 124
 125         cmd_val = NFC_CMD_NFCCMD
 126                 | ((chip->chip_select << NFC_CMD_CSID_SHIFT) & NFC_CMD_CSID_MASK)
 127                 | ((num_cycles << NFC_CMD_ACYCLE_SHIFT) & NFC_CMD_ACYCLE_MASK)
 128                 | cmd1 << 2
 129                 | cmd2 << 10;
 130
 131         // Check for commands transferring data
 132         if (cmd1 == NAND_CMD_WRITE_1 || cmd1 == NAND_CMD_READ_1 || cmd1 == NAND_CMD_READID)
 133                 cmd_val |= NFC_CMD_NFCEN;
 134
 135         // Check for commands writing data
 136         if (cmd1 == NAND_CMD_WRITE_1)
 137                 cmd_val |= NFC_CMD_NFCWR;
 138
 139         // Check for two command cycles
 140         if (cmd2)
 141                 cmd_val |= NFC_CMD_VCMD2;
 142
 143         cmd_addr = (reg32_t *)(NFC_CMD_BASE_ADDR + cmd_val);
 144         *cmd_addr = cycle1234;
 145
 146     while (!(SMC_SR & SMC_SR_CMDDONE));
 147 }
 148
 149
 150 /*
 151  * Get NAND chip status register.
 152  *
 153  * NOTE: this is global between different chip selects, so returns
 154  * the status register of the last used NAND chip.
 155  */
 156 uint8_t nand_getChipStatus(UNUSED_ARG(Nand *, chip))
 157 {
 158         return (uint8_t)HWREG(NFC_CMD_BASE_ADDR);
 159 }
 160
 161
 162 /*
 163  * Return pointer to buffer where data are read to or written from
 164  * by nand_sendCommand().
 165  */
 166 void *nand_dataBuffer(UNUSED_ARG(Nand *, chip))
 167 {
 168         return (void *)NFC_SRAM_BASE_ADDR;
 169 }
 170
 171
 172 /*
 173  * Extract ECC data from ECC_PRx registers.
 174  */
 175 bool nand_checkEcc(UNUSED_ARG(Nand *, chip))
 176 {
 177         uint32_t sr1 = SMC_ECC_SR1;
 178         if (sr1)
 179         {
 180                 LOG_INFO("ECC error, ECC_SR1=0x%lx\n", sr1);
 181                 return false;
 182         }
 183         else
 184                 return true;
 185 }
 186
 187
 188 /*
 189  * Compute ECC on data in a buffer.
 190  *
 191  * \param chip      nand context
 192  * \param buf       buffer containing data
 193  * \param size      size of data buffer
 194  * \param ecc       pointer to buffer where computed ECC is stored
 195  * \param ecc_size  max size for ecc buffer
 196  */
 197 void nand_computeEcc(UNUSED_ARG(Nand *, chip),
 198                 UNUSED_ARG(const void *, buf), UNUSED_ARG(size_t, size), uint32_t *ecc, size_t ecc_size)
 199 {
 200         size_t i;
 201         for (i = 0; i < ecc_size; i++)
 202                 ecc[i] = *((reg32_t *)(SMC_BASE + SMC_ECC_PR0_OFF) + i);
 203 }
 204
 205
 206 /*
 207  * Low-level hardware driver initialization.
 208  */
 209 void nand_hwInit(UNUSED_ARG(Nand *, chip))
 210 {
 211         // FIXME: Parameters specific for MT29F8G08AAD
 212
 213         // PIO init
 214         pmc_periphEnable(PIOA_ID);
 215         pmc_periphEnable(PIOC_ID);
 216         pmc_periphEnable(PIOD_ID);
 217
 218         PIO_PERIPH_SEL(PIOA_BASE, NAND_PINS_PORTA, NAND_PERIPH_PORTA);
 219         PIOA_PDR = NAND_PINS_PORTA;
 220         PIOA_PUER = NAND_PINS_PORTA;
 221
 222         PIO_PERIPH_SEL(PIOC_BASE, NAND_PINS_PORTC, NAND_PERIPH_PORTC);
 223         PIOC_PDR = NAND_PINS_PORTC;
 224         PIOC_PUER = NAND_PINS_PORTC;
 225
 226         PIO_PERIPH_SEL(PIOD_BASE, NAND_PINS_PORTD, NAND_PERIPH_PORTD);
 227         PIOD_PDR = NAND_PINS_PORTD;
 228         PIOD_PUER = NAND_PINS_PORTD;
 229
 230     pmc_periphEnable(SMC_SDRAMC_ID);
 231
 232         // SMC init
 233     SMC_SETUP0 = SMC_SETUP_NWE_SETUP(0)
 234                 | SMC_SETUP_NCS_WR_SETUP(0)
 235                 | SMC_SETUP_NRD_SETUP(0)
 236                 | SMC_SETUP_NCS_RD_SETUP(0);
 237
 238     SMC_PULSE0 = SMC_PULSE_NWE_PULSE(2)
 239                 | SMC_PULSE_NCS_WR_PULSE(3)
 240                 | SMC_PULSE_NRD_PULSE(2)
 241                 | SMC_PULSE_NCS_RD_PULSE(3);
 242
 243     SMC_CYCLE0 = SMC_CYCLE_NWE_CYCLE(3)
 244                 | SMC_CYCLE_NRD_CYCLE(3);
 245
 246     SMC_TIMINGS0 = SMC_TIMINGS_TCLR(1)
 247                 | SMC_TIMINGS_TADL(6)
 248                 | SMC_TIMINGS_TAR(4)
 249                 | SMC_TIMINGS_TRR(2)
 250                 | SMC_TIMINGS_TWB(9)
 251                 | SMC_TIMINGS_RBNSEL(7)
 252                 | SMC_TIMINGS_NFSEL;
 253
 254     SMC_MODE0 = SMC_MODE_READ_MODE
 255                 | SMC_MODE_WRITE_MODE;
 256
 257         SMC_CFG = SMC_CFG_PAGESIZE_PS2048_64
 258                 | SMC_CFG_EDGECTRL
 259                 | SMC_CFG_DTOMUL_X1048576
 260                 | SMC_CFG_DTOCYC(0xF)
 261                 | SMC_CFG_WSPARE
 262                 | SMC_CFG_RSPARE;
 263
 264         // Disable SMC interrupts, reset and enable NFC controller
 265         SMC_IDR = ~0;
 266         SMC_CTRL = 0;
 267         SMC_CTRL = SMC_CTRL_NFCEN;
 268
 269         // Enable ECC, 1 ECC per 256 bytes
 270         SMC_ECC_CTRL = SMC_ECC_CTRL_SWRST;
 271         SMC_ECC_MD = SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 | SMC_ECC_MD_TYPCORREC_C256B;
 272 }