4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Cortex-M3 architecture's entry point
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/debug.h>
41 extern size_t _etext, __data_start, __data_end,
42 __bss_start, __bss_end, __stack_irq_end;
44 extern int main(void);
46 /* Architecture's entry point */
47 static void _entry(void)
51 /* Copy the data segment initializers from flash to SRAM */
53 for (dst = &__data_start; dst < &__data_end ; )
56 /* Zero fill the bss segment */
57 for (dst = &__bss_start; dst < &__bss_end ; )
60 /* Initialize IRQ vector table in RAM */
63 /* Call the application's entry point */
67 static void nmi_isr(void)
72 static void fault_isr(void)
77 static void default_isr(void)
82 /* Startup vector table */
83 static void (* const irq_vectors[])(void) __attribute__ ((section(".vectors"))) = {
84 (void (*)(void))&__stack_irq_end, /* Initial stack pointer */
85 _entry, /* The reset handler */
86 nmi_isr, /* The NMI handler */
87 fault_isr, /* The hard fault handler */
88 default_isr, /* The MPU fault handler */
89 default_isr, /* The bus fault handler */
90 default_isr, /* The usage fault handler */
95 default_isr, /* SVCall handler */
96 default_isr, /* Debug monitor handler */
98 default_isr, /* The PendSV handler */
99 default_isr, /* The SysTick handler */
100 default_isr, /* GPIO Port A */
101 default_isr, /* GPIO Port B */
102 default_isr, /* GPIO Port C */
103 default_isr, /* GPIO Port D */
104 default_isr, /* GPIO Port E */
105 default_isr, /* UART0 Rx and Tx */
106 default_isr, /* UART1 Rx and Tx */
107 default_isr, /* SSI0 Rx and Tx */
108 default_isr, /* I2C0 Master and Slave */
109 default_isr, /* PWM Fault */
110 default_isr, /* PWM Generator 0 */
111 default_isr, /* PWM Generator 1 */
112 default_isr, /* PWM Generator 2 */
113 default_isr, /* Quadrature Encoder 0 */
114 default_isr, /* ADC Sequence 0 */
115 default_isr, /* ADC Sequence 1 */
116 default_isr, /* ADC Sequence 2 */
117 default_isr, /* ADC Sequence 3 */
118 default_isr, /* Watchdog timer */
119 default_isr, /* Timer 0 subtimer A */
120 default_isr, /* Timer 0 subtimer B */
121 default_isr, /* Timer 1 subtimer A */
122 default_isr, /* Timer 1 subtimer B */
123 default_isr, /* Timer 2 subtimer A */
124 default_isr, /* Timer 2 subtimer B */
125 default_isr, /* Analog Comparator 0 */
126 default_isr, /* Analog Comparator 1 */
127 default_isr, /* Analog Comparator 2 */
128 default_isr, /* System Control (PLL, OSC, BO) */
129 default_isr, /* FLASH Control */
130 default_isr, /* GPIO Port F */
131 default_isr, /* GPIO Port G */
132 default_isr, /* GPIO Port H */
133 default_isr, /* UART2 Rx and Tx */
134 default_isr, /* SSI1 Rx and Tx */
135 default_isr, /* Timer 3 subtimer A */
136 default_isr, /* Timer 3 subtimer B */
137 default_isr, /* I2C1 Master and Slave */
138 default_isr, /* Quadrature Encoder 1 */
139 default_isr, /* CAN0 */
140 default_isr, /* CAN1 */
141 default_isr, /* CAN2 */
142 default_isr, /* Ethernet */
143 default_isr /* Hibernate */