bertos/cpu/irq.h

   1 /**
   2  * \file
   3  * <!--
   4  * This file is part of BeRTOS.
   5  *
   6  * Bertos is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  *
  20  * As a special exception, you may use this file as part of a free software
  21  * library without restriction.  Specifically, if other files instantiate
  22  * templates or use macros or inline functions from this file, or you compile
  23  * this file and link it with other files to produce an executable, this
  24  * file does not by itself cause the resulting executable to be covered by
  25  * the GNU General Public License.  This exception does not however
  26  * invalidate any other reasons why the executable file might be covered by
  27  * the GNU General Public License.
  28  *
  29  * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
  30  * Copyright 2004 Giovanni Bajo
  31  *
  32  * -->
  33  *
  34  * \brief CPU-specific IRQ definitions.
  35  *
  36  * \author Giovanni Bajo <rasky@develer.com>
  37  * \author Bernie Innocenti <bernie@codewiz.org>
  38  * \author Stefano Fedrigo <aleph@develer.com>
  39  * \author Francesco Sacchi <batt@develer.com>
  40  */
  41 #ifndef CPU_IRQ_H
  42 #define CPU_IRQ_H
  43
  44 #include "detect.h"
  45 #include "types.h"
  46
  47 #include <cfg/compiler.h> /* for uintXX_t */
  48
  49 #if CPU_I196
  50         #define IRQ_DISABLE             disable_interrupt()
  51         #define IRQ_ENABLE              enable_interrupt()
  52 #elif CPU_X86
  53
  54         /* Get IRQ_* definitions from the hosting environment. */
  55         #include <cfg/os.h>
  56         #if OS_EMBEDDED
  57                 #define IRQ_DISABLE             FIXME
  58                 #define IRQ_ENABLE              FIXME
  59                 #define IRQ_SAVE_DISABLE(x)     FIXME
  60                 #define IRQ_RESTORE(x)          FIXME
  61         #endif /* OS_EMBEDDED */
  62
  63         #ifdef __GNUC__
  64                 #define BREAKPOINT  asm volatile ("int 3" ::)
  65         #endif
  66
  67 #elif CPU_ARM
  68
  69         #ifdef __IAR_SYSTEMS_ICC__
  70
  71                 #include <inarm.h>
  72
  73                 #if __CPU_MODE__ == 1 /* Thumb */
  74                         /* Use stubs */
  75                         extern cpuflags_t get_CPSR(void);
  76                         extern void set_CPSR(cpuflags_t flags);
  77                 #else
  78                         #define get_CPSR __get_CPSR
  79                         #define set_CPSR __set_CPSR
  80                 #endif
  81
  82                 #define IRQ_DISABLE __disable_interrupt()
  83                 #define IRQ_ENABLE  __enable_interrupt()
  84
  85                 #define IRQ_SAVE_DISABLE(x) \
  86                 do { \
  87                         (x) = get_CPSR(); \
  88                         __disable_interrupt(); \
  89                 } while (0)
  90
  91                 #define IRQ_RESTORE(x) \
  92                 do { \
  93                         set_CPSR(x); \
  94                 } while (0)
  95
  96                 #define IRQ_ENABLED() \
  97                         ((bool)(get_CPSR() & 0xb0))
  98
  99                 #define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
 100
 101         #else /* !__IAR_SYSTEMS_ICC__ */
 102
 103                 #define IRQ_DISABLE \
 104                 do { \
 105                         asm volatile ( \
 106                                 "mrs r0, cpsr\n\t" \
 107                                 "orr r0, r0, #0xc0\n\t" \
 108                                 "msr cpsr_c, r0" \
 109                                 ::: "r0" \
 110                         ); \
 111                 } while (0)
 112
 113                 #define IRQ_ENABLE \
 114                 do { \
 115                         asm volatile ( \
 116                                 "mrs r0, cpsr\n\t" \
 117                                 "bic r0, r0, #0xc0\n\t" \
 118                                 "msr cpsr_c, r0" \
 119                                 ::: "r0" \
 120                         ); \
 121                 } while (0)
 122
 123                 #define IRQ_SAVE_DISABLE(x) \
 124                 do { \
 125                         asm volatile ( \
 126                                 "mrs %0, cpsr\n\t" \
 127                                 "orr r0, %0, #0xc0\n\t" \
 128                                 "msr cpsr_c, r0" \
 129                                 : "=r" (x) \
 130                                 : /* no inputs */ \
 131                                 : "r0" \
 132                         ); \
 133                 } while (0)
 134
 135                 #define IRQ_RESTORE(x) \
 136                 do { \
 137                         asm volatile ( \
 138                                 "msr cpsr_c, %0" \
 139                                 : /* no outputs */ \
 140                                 : "r" (x) \
 141                         ); \
 142                 } while (0)
 143
 144                 #define CPU_READ_FLAGS() \
 145                 ({ \
 146                         cpuflags_t sreg; \
 147                         asm volatile ( \
 148                                 "mrs %0, cpsr\n\t" \
 149                                 : "=r" (sreg) \
 150                                 : /* no inputs */ \
 151                         ); \
 152                         sreg; \
 153                 })
 154
 155                 #define IRQ_ENABLED() ((CPU_READ_FLAGS() & 0xc0) != 0xc0)
 156
 157         #endif /* !__IAR_SYSTEMS_ICC_ */
 158
 159 #elif CPU_PPC
 160
 161         /* Get IRQ_* definitions from the hosting environment. */
 162         #include <cfg/os.h>
 163         #if OS_EMBEDDED
 164                 #define IRQ_DISABLE         FIXME
 165                 #define IRQ_ENABLE          FIXME
 166                 #define IRQ_SAVE_DISABLE(x) FIXME
 167                 #define IRQ_RESTORE(x)      FIXME
 168                 #define IRQ_ENABLED()       FIXME
 169         #endif /* OS_EMBEDDED */
 170
 171         #ifdef __GNUC__
 172                 #define BREAKPOINT  asm volatile ("twge 2,2" ::)
 173         #endif
 174
 175 #elif CPU_DSP56K
 176
 177         #define BREAKPOINT              asm(debug)
 178         #define IRQ_DISABLE             do { asm(bfset #0x0200,SR); asm(nop); } while (0)
 179         #define IRQ_ENABLE              do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
 180
 181         #define IRQ_SAVE_DISABLE(x)  \
 182                 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
 183         #define IRQ_RESTORE(x)  \
 184                 do { (void)x; asm(move x,SR); } while (0)
 185
 186         static inline bool irq_running(void)
 187         {
 188                 extern void *user_sp;
 189                 return !!user_sp;
 190         }
 191         #define IRQ_RUNNING() irq_running()
 192
 193         static inline bool irq_enabled(void)
 194         {
 195                 uint16_t x;
 196                 asm(move SR,x);
 197                 return !(x & 0x0200);
 198         }
 199         #define IRQ_ENABLED() irq_enabled()
 200
 201 #elif CPU_AVR
 202
 203         #define IRQ_DISABLE   asm volatile ("cli" ::)
 204         #define IRQ_ENABLE    asm volatile ("sei" ::)
 205
 206         #define IRQ_SAVE_DISABLE(x) \
 207         do { \
 208                 __asm__ __volatile__( \
 209                         "in %0,__SREG__\n\t" \
 210                         "cli" \
 211                         : "=r" (x) : /* no inputs */ : "cc" \
 212                 ); \
 213         } while (0)
 214
 215         #define IRQ_RESTORE(x) \
 216         do { \
 217                 __asm__ __volatile__( \
 218                         "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
 219                 ); \
 220         } while (0)
 221
 222         #define IRQ_ENABLED() \
 223         ({ \
 224                 uint8_t sreg; \
 225                 __asm__ __volatile__( \
 226                         "in %0,__SREG__\n\t" \
 227                         : "=r" (sreg)  /* no inputs & no clobbers */ \
 228                 ); \
 229                 (bool)(sreg & 0x80); \
 230         })
 231 #else
 232         #error No CPU_... defined.
 233 #endif
 234
 235 #ifndef IRQ_ENTRY
 236         #define IRQ_ENTRY() /* NOP */
 237 #endif
 238
 239 #ifndef IRQ_EXIT
 240         #define IRQ_EXIT() /* NOP */
 241 #endif
 242
 243 #ifdef IRQ_RUNNING
 244         /// Ensure callee is running within an interrupt
 245         #define ASSERT_IRQ_CONTEXT()  ASSERT(IRQ_RUNNING())
 246
 247         /// Ensure callee is not running within an interrupt
 248         #define ASSERT_USER_CONTEXT() ASSERT(!IRQ_RUNNING())
 249 #else
 250         #define ASSERT_USER_CONTEXT()  do {} while(0)
 251         #define ASSERT_IRQ_CONTEXT()   do {} while(0)
 252 #endif
 253
 254 #ifdef IRQ_ENABLED
 255         /// Ensure interrupts are enabled
 256         #define IRQ_ASSERT_ENABLED()  ASSERT(IRQ_ENABLED())
 257
 258         /// Ensure interrupts are not enabled
 259         #define IRQ_ASSERT_DISABLED() ASSERT(!IRQ_ENABLED())
 260 #else
 261         #define IRQ_ASSERT_ENABLED() do {} while(0)
 262         #define IRQ_ASSERT_DISABLED() do {} while(0)
 263 #endif
 264
 265 // OBSOLETE names
 266 #define ASSERT_IRQ_ENABLED()  IRQ_ASSERT_ENABLED()
 267 #define ASSERT_IRQ_DISABLED() IRQ_ASSERT_DISABLED()
 268
 269 /**
 270  * Execute \a CODE atomically with respect to interrupts.
 271  *
 272  * \see IRQ_SAVE_DISABLE IRQ_RESTORE
 273  */
 274 #define ATOMIC(CODE) \
 275         do { \
 276                 cpuflags_t __flags; \
 277                 IRQ_SAVE_DISABLE(__flags); \
 278                 CODE; \
 279                 IRQ_RESTORE(__flags); \
 280         } while (0)
 281
 282
 283 #ifndef BREAKPOINT
 284 #define BREAKPOINT /* nop */
 285 #endif
 286
 287
 288 #endif /* CPU_IRQ_H */