4 * This file is part of BeRTOS.
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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24 * file does not by itself cause the resulting executable to be covered by
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26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
33 * \brief AFSK1200 modem.
36 * \author Francesco Sacchi <asterix@develer.com>
42 #include "cfg/cfg_afsk.h"
43 #include "hw/hw_afsk.h"
45 #include <drv/timer.h>
47 #include <cfg/module.h>
49 #define LOG_LEVEL AFSK_LOG_LEVEL
50 #define LOG_FORMAT AFSK_LOG_FORMAT
53 #include <cpu/power.h>
55 #include <struct/fifobuf.h>
57 #include <string.h> /* memset */
62 #define PHASE_MAX (SAMPLEPERBIT * PHASE_BIT)
63 #define PHASE_THRES (PHASE_MAX / 2) // - PHASE_BIT / 2)
65 // Modulator constants
66 #define MARK_FREQ 1200
67 #define MARK_INC (uint16_t)(DIV_ROUND(SIN_LEN * (uint32_t)MARK_FREQ, CONFIG_AFSK_DAC_SAMPLERATE))
69 #define SPACE_FREQ 2200
70 #define SPACE_INC (uint16_t)(DIV_ROUND(SIN_LEN * (uint32_t)SPACE_FREQ, CONFIG_AFSK_DAC_SAMPLERATE))
72 //Ensure sample rate is a multiple of bit rate
73 STATIC_ASSERT(!(CONFIG_AFSK_DAC_SAMPLERATE % BITRATE));
75 #define DAC_SAMPLEPERBIT (CONFIG_AFSK_DAC_SAMPLERATE / BITRATE)
78 * Sine table for the first quarter of wave.
79 * The rest of the wave is computed from this first quarter.
80 * This table is used to generate the modulated data.
82 static const uint8_t PROGMEM sin_table[] =
84 128, 129, 131, 132, 134, 135, 137, 138, 140, 142, 143, 145, 146, 148, 149, 151,
85 152, 154, 155, 157, 158, 160, 162, 163, 165, 166, 167, 169, 170, 172, 173, 175,
86 176, 178, 179, 181, 182, 183, 185, 186, 188, 189, 190, 192, 193, 194, 196, 197,
87 198, 200, 201, 202, 203, 205, 206, 207, 208, 210, 211, 212, 213, 214, 215, 217,
88 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233,
89 234, 234, 235, 236, 237, 238, 238, 239, 240, 241, 241, 242, 243, 243, 244, 245,
90 245, 246, 246, 247, 248, 248, 249, 249, 250, 250, 250, 251, 251, 252, 252, 252,
91 253, 253, 253, 253, 254, 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255,
94 #define SIN_LEN 512 ///< Full wave length
96 STATIC_ASSERT(sizeof(sin_table) == SIN_LEN / 4);
100 * Given the index, this function computes the correct sine sample
101 * based only on the first quarter of wave.
103 INLINE uint8_t sin_sample(uint16_t idx)
105 ASSERT(idx < SIN_LEN);
106 uint16_t new_idx = idx % (SIN_LEN / 2);
107 new_idx = (new_idx >= (SIN_LEN / 4)) ? (SIN_LEN / 2 - new_idx - 1) : new_idx;
110 uint8_t data = pgm_read_char(&sin_table[new_idx]);
112 uint8_t data = sin_table[new_idx];
115 return (idx >= (SIN_LEN / 2)) ? (255 - data) : data;
119 #define BIT_DIFFER(bitline1, bitline2) (((bitline1) ^ (bitline2)) & 0x01)
120 #define EDGE_FOUND(bitline) BIT_DIFFER((bitline), (bitline) >> 1)
123 static void hdlc_parse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo)
125 hdlc->demod_bits <<= 1;
126 hdlc->demod_bits |= bit ? 1 : 0;
129 if (hdlc->demod_bits == HDLC_FLAG)
131 if (!fifo_isfull(fifo))
133 fifo_push(fifo, HDLC_FLAG);
134 hdlc->rxstart = true;
137 hdlc->rxstart = false;
145 if ((hdlc->demod_bits & HDLC_RESET) == HDLC_RESET)
147 hdlc->rxstart = false;
155 if ((hdlc->demod_bits & 0x3f) == 0x3e)
158 if (hdlc->demod_bits & 0x01)
159 hdlc->currchar |= 0x80;
161 if (++hdlc->bit_idx >= 8)
163 if ((hdlc->currchar == HDLC_FLAG
164 || hdlc->currchar == HDLC_RESET
165 || hdlc->currchar == AX25_ESC))
167 if (!fifo_isfull(fifo))
168 fifo_push(fifo, AX25_ESC);
170 hdlc->rxstart = false;
173 if (!fifo_isfull(fifo))
174 fifo_push(fifo, hdlc->currchar);
176 hdlc->rxstart = false;
183 hdlc->currchar >>= 1;
189 * This function has to be called by the ADC ISR when a sample of the configured
190 * channel is available.
191 * \param af Afsk context to operate one (\see Afsk).
192 * \param curr_sample current sample from the ADC.
194 void afsk_adc_isr(Afsk *af, int8_t curr_sample)
199 * Frequency discriminator and LP IIR filter.
200 * This filter is designed to work
201 * at the given sample rate and bit rate.
203 STATIC_ASSERT(SAMPLERATE == 9600);
204 STATIC_ASSERT(BITRATE == 1200);
207 * Frequency discrimination is achieved by simply multiplying
208 * the sample with a delayed sample of (samples per bit) / 2.
209 * Then the signal is lowpass filtered with a first order,
210 * 600 Hz filter. The filter implementation is selectable
211 * through the CONFIG_AFSK_FILTER config variable.
214 af->iir_x[0] = af->iir_x[1];
216 #if (CONFIG_AFSK_FILTER == AFSK_BUTTERWORTH)
217 af->iir_x[1] = ((int8_t)fifo_pop(&af->delay_fifo) * curr_sample) >> 2;
218 //af->iir_x[1] = ((int8_t)fifo_pop(&af->delay_fifo) * curr_sample) / 6.027339492;
219 #elif (CONFIG_AFSK_FILTER == AFSK_CHEBYSHEV)
220 af->iir_x[1] = ((int8_t)fifo_pop(&af->delay_fifo) * curr_sample) >> 2;
221 //af->iir_x[1] = ((int8_t)fifo_pop(&af->delay_fifo) * curr_sample) / 3.558147322;
223 #error Filter type not found!
226 af->iir_y[0] = af->iir_y[1];
228 #if CONFIG_AFSK_FILTER == AFSK_BUTTERWORTH
230 * This strange sum + shift is an optimization for af->iir_y[0] * 0.668.
231 * iir * 0.668 ~= (iir * 21) / 32 =
232 * = (iir * 16) / 32 + (iir * 4) / 32 + iir / 32 =
233 * = iir / 2 + iir / 8 + iir / 32 =
234 * = iir >> 1 + iir >> 3 + iir >> 5
236 af->iir_y[1] = af->iir_x[0] + af->iir_x[1] + (af->iir_y[0] >> 1) + (af->iir_y[0] >> 3) + (af->iir_y[0] >> 5);
237 //af->iir_y[1] = af->iir_x[0] + af->iir_x[1] + af->iir_y[0] * 0.6681786379;
238 #elif CONFIG_AFSK_FILTER == AFSK_CHEBYSHEV
240 * This should be (af->iir_y[0] * 0.438) but
241 * (af->iir_y[0] >> 1) is a faster approximation :-)
243 af->iir_y[1] = af->iir_x[0] + af->iir_x[1] + (af->iir_y[0] >> 1);
244 //af->iir_y[1] = af->iir_x[0] + af->iir_x[1] + af->iir_y[0] * 0.4379097269;
247 /* Save this sampled bit in a delay line */
248 af->sampled_bits <<= 1;
249 af->sampled_bits |= (af->iir_y[1] > 0) ? 1 : 0;
251 /* Store current ADC sample in the af->delay_fifo */
252 fifo_push(&af->delay_fifo, curr_sample);
254 /* If there is an edge, adjust phase sampling */
255 if (EDGE_FOUND(af->sampled_bits))
257 if (af->curr_phase < PHASE_THRES)
258 af->curr_phase += PHASE_INC;
260 af->curr_phase -= PHASE_INC;
262 af->curr_phase += PHASE_BIT;
265 if (af->curr_phase >= PHASE_MAX)
267 af->curr_phase %= PHASE_MAX;
269 /* Shift 1 position in the shift register of the found bits */
270 af->found_bits <<= 1;
273 * Determine bit value by reading the last 3 sampled bits.
274 * If the number of ones is two or greater, the bit value is a 1,
276 * This algorithm presumes that there are 8 samples per bit.
278 STATIC_ASSERT(SAMPLEPERBIT == 8);
279 uint8_t bits = af->sampled_bits & 0x07;
280 if (bits == 0x07 // 111, 3 bits set to 1
281 || bits == 0x06 // 110, 2 bits
282 || bits == 0x05 // 101, 2 bits
283 || bits == 0x03 // 011, 2 bits
288 * NRZI coding: if 2 consecutive bits have the same value
289 * a 1 is received, otherwise it's a 0.
291 hdlc_parse(&af->hdlc, !EDGE_FOUND(af->found_bits), &af->rx_fifo);
298 static void afsk_txStart(Afsk *af)
302 af->phase_inc = MARK_INC;
306 af->preamble_len = DIV_ROUND(CONFIG_AFSK_PREAMBLE_LEN * BITRATE, 8000);
307 AFSK_DAC_IRQ_START(af->dac_ch);
309 ATOMIC(af->trailer_len = DIV_ROUND(CONFIG_AFSK_TRAILER_LEN * BITRATE, 8000));
312 #define BIT_STUFF_LEN 5
314 #define SWITCH_TONE(inc) (((inc) == MARK_INC) ? SPACE_INC : MARK_INC)
318 * This function has to be called by the DAC ISR when a sample of the configured
319 * channel has been converted out.
321 * \param af Afsk context to operate one (\see Afsk).
323 * \note The next DAC output sample is supplied by the Afsk driver through calling
324 * the AFSK_DAC_SET() callback.
326 void afsk_dac_isr(Afsk *af)
328 /* Check if we are at a start of a sample cycle */
329 if (af->sample_count == 0)
333 /* We have just finished transimitting a char, get a new one. */
334 if (fifo_isempty(&af->tx_fifo) && af->trailer_len == 0)
336 AFSK_DAC_IRQ_STOP(af->dac_ch);
343 * If we have just finished sending an unstuffed byte,
344 * reset bitstuff counter.
349 af->bit_stuff = true;
352 * Handle preamble and trailer
354 if (af->preamble_len == 0)
356 if (fifo_isempty(&af->tx_fifo))
359 af->curr_out = HDLC_FLAG;
362 af->curr_out = fifo_pop(&af->tx_fifo);
367 af->curr_out = HDLC_FLAG;
370 /* Handle char escape */
371 if (af->curr_out == AX25_ESC)
373 if (fifo_isempty(&af->tx_fifo))
375 AFSK_DAC_IRQ_STOP(af->dac_ch);
380 af->curr_out = fifo_pop(&af->tx_fifo);
382 else if (af->curr_out == HDLC_FLAG || af->curr_out == HDLC_RESET)
383 /* If these chars are not escaped disable bit stuffing */
384 af->bit_stuff = false;
386 /* Start with LSB mask */
390 /* check for bit stuffing */
391 if (af->bit_stuff && af->stuff_cnt >= BIT_STUFF_LEN)
393 /* If there are more than 5 ones in a row insert a 0 */
396 af->phase_inc = SWITCH_TONE(af->phase_inc);
401 * NRZI: if we want to transmit a 1 the modulated frequency will stay
402 * unchanged; with a 0, there will be a change in the tone.
404 if (af->curr_out & af->tx_bit)
408 * - Stay on the previous tone
409 * - Increase bit stuff counter
417 * - Reset bit stuff counter
421 af->phase_inc = SWITCH_TONE(af->phase_inc);
424 /* Go to the next bit */
427 af->sample_count = DAC_SAMPLEPERBIT;
430 /* Get new sample and put it out on the DAC */
431 af->phase_acc += af->phase_inc;
432 af->phase_acc %= SIN_LEN;
434 AFSK_DAC_SET(af->dac_ch, sin_sample(af->phase_acc));
439 static size_t afsk_read(KFile *fd, void *_buf, size_t size)
441 Afsk *af = AFSK_CAST(fd);
442 uint8_t *buf = (uint8_t *)_buf;
444 #if CONFIG_AFSK_RXTIMEOUT == 0
445 while (size-- && !fifo_isempty_locked(&af->rx_fifo))
450 #if CONFIG_AFSK_RXTIMEOUT != -1
451 ticks_t start = timer_clock();
454 while (fifo_isempty_locked(&af->rx_fifo));
457 #if CONFIG_AFSK_RXTIMEOUT != -1
458 if (timer_clock() - start > ms_to_ticks(CONFIG_AFSK_RXTIMEOUT))
459 return buf - (uint8_t *)_buf;
463 *buf++ = fifo_pop_locked(&af->rx_fifo);
466 return buf - (uint8_t *)_buf;
469 static size_t afsk_write(KFile *fd, const void *_buf, size_t size)
471 Afsk *af = AFSK_CAST(fd);
472 const uint8_t *buf = (const uint8_t *)_buf;
476 while (fifo_isfull_locked(&af->tx_fifo))
479 fifo_push_locked(&af->tx_fifo, *buf++);
483 return buf - (const uint8_t *)_buf;
486 static int afsk_flush(KFile *fd)
488 Afsk *af = AFSK_CAST(fd);
496 * Initialize an AFSK1200 modem.
497 * \param af Afsk context to operate one (\see Afsk).
498 * \param adc_ch ADC channel used by the demodulator.
499 * \param dac_ch DAC channel used by the modulator.
501 void afsk_init(Afsk *af, int adc_ch, int dac_ch)
503 #if CONFIG_AFSK_RXTIMEOUT != -1
506 memset(af, 0, sizeof(*af));
510 fifo_init(&af->delay_fifo, (uint8_t *)af->delay_buf, sizeof(af->delay_buf));
511 fifo_init(&af->rx_fifo, af->rx_buf, sizeof(af->rx_buf));
513 /* Fill sample FIFO with 0 */
514 for (int i = 0; i < SAMPLEPERBIT / 2; i++)
515 fifo_push(&af->delay_fifo, 0);
517 fifo_init(&af->tx_fifo, af->tx_buf, sizeof(af->tx_buf));
519 AFSK_ADC_INIT(adc_ch, af);
520 AFSK_DAC_INIT(dac_ch, af);
522 LOG_INFO("MARK_INC %d, SPACE_INC %d\n", MARK_INC, SPACE_INC);
524 DB(af->fd._type = KFT_AFSK);
525 af->fd.write = afsk_write;
526 af->fd.read = afsk_read;
527 af->fd.flush = afsk_flush;
528 af->phase_inc = MARK_INC;