Sistema l'errore da me commesso in fase di conversione...
[bertos.git] / cfg / cpu.h
1 /**
2  * \file
3  * <!--
4  * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
5  * Copyright 2004 Giovanni Bajo
6  * This file is part of DevLib - See README.devlib for information.
7  * -->
8  *
9  * \brief CPU-specific definitions
10  *
11  * \author Giovanni Bajo <rasky@develer.com>
12  * \author Bernardo Innocenti <bernie@develer.com>
13  * \author Stefano Fedrigo <aleph@develer.com>
14  */
15 #ifndef DEVLIB_CPU_H
16 #define DEVLIB_CPU_H
17
18 #include <cfg/compiler.h> /* for uintXX_t */
19 #include <cfg/arch_config.h>  /* ARCH_EMUL */
20
21
22 /**
23  * \name Macros for determining CPU endianness.
24  * \{
25  */
26 #define CPU_BIG_ENDIAN    0x1234
27 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
28 /*\}*/
29
30 /** Macro to include cpu-specific versions of the headers. */
31 #define CPU_HEADER(module)          PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
32
33 /** Macro to include cpu-specific versions of implementation files. */
34 #define CPU_CSOURCE(module)         PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
35
36
37 #if CPU_I196
38
39         #define NOP                     nop_instruction()
40         #define IRQ_DISABLE             disable_interrupt()
41         #define IRQ_ENABLE              enable_interrupt()
42
43         typedef uint16_t cpuflags_t; // FIXME
44         typedef unsigned int cpustack_t;
45
46         #define CPU_REG_BITS            16
47         #define CPU_REGS_CNT            16
48         #define CPU_STACK_GROWS_UPWARD  0
49         #define CPU_SP_ON_EMPTY_SLOT    0
50         #define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
51         #define CPU_HARVARD             0
52
53 #elif CPU_X86
54
55         #define NOP                     asm volatile ("nop")
56
57         /* Get IRQ_* definitions from the hosting environment. */
58         #include <cfg/os.h>
59         #if OS_EMBEDDED
60                 #define IRQ_DISABLE             FIXME
61                 #define IRQ_ENABLE              FIXME
62                 #define IRQ_SAVE_DISABLE(x)     FIXME
63                 #define IRQ_RESTORE(x)          FIXME
64                 typedef uint32_t cpuflags_t; // FIXME
65         #endif /* OS_EMBEDDED */
66
67
68         #define CPU_REGS_CNT            7
69         #define CPU_SAVED_REGS_CNT      7
70         #define CPU_STACK_GROWS_UPWARD  0
71         #define CPU_SP_ON_EMPTY_SLOT    0
72         #define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
73         #define CPU_HARVARD             0
74
75         #if CPU_X86_64
76                 typedef uint64_t cpustack_t;
77                 #define CPU_REG_BITS    64
78
79                 #ifdef __WIN64__
80                         /* WIN64 is an IL32-P64 weirdo. */
81                         #define SIZEOF_LONG  4
82                 #endif
83         #else
84                 typedef uint32_t cpustack_t;
85                 #define CPU_REG_BITS    32
86         #endif
87
88 #elif CPU_ARM
89
90         typedef uint32_t cpuflags_t;
91         typedef uint32_t cpustack_t;
92
93         /* Register counts include SREG too */
94         #define CPU_REG_BITS           32
95         #define CPU_REGS_CNT           16
96         #define CPU_SAVED_REGS_CNT     FIXME
97         #define CPU_STACK_GROWS_UPWARD 0
98         #define CPU_SP_ON_EMPTY_SLOT   0
99         #define CPU_BYTE_ORDER         (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
100         #define CPU_HARVARD            0
101
102         #ifdef __IAR_SYSTEMS_ICC__
103
104                 #include <inarm.h>
105
106                 #if __CPU_MODE__ == 1 /* Thumb */
107                         /* Use stubs */
108                         extern cpuflags_t get_CPSR(void);
109                         extern void set_CPSR(cpuflags_t flags);
110                 #else
111                         #define get_CPSR __get_CPSR
112                         #define set_CPSR __set_CPSR
113                 #endif
114
115                 #define NOP         __no_operation()
116                 #define IRQ_DISABLE __disable_interrupt()
117                 #define IRQ_ENABLE  __enable_interrupt()
118
119                 #define IRQ_SAVE_DISABLE(x) \
120                 do { \
121                         (x) = get_CPSR(); \
122                         __disable_interrupt(); \
123                 } while (0)
124
125                 #define IRQ_RESTORE(x) \
126                 do { \
127                         set_CPSR(x); \
128                 } while (0)
129
130                 #define IRQ_GETSTATE() \
131                         ((bool)(get_CPSR() & 0xb0))
132
133                 #define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
134
135         #else /* !__IAR_SYSTEMS_ICC__ */
136
137                 #warning "IRQ_ macros need testing!"
138                 #warning "Test now or die :-)"
139
140                 #define NOP         asm volatile ("mov r0,r0" ::)
141
142                 #define IRQ_DISABLE \
143                 do { \
144                         asm volatile ( \
145                                 "mrs r0, cpsr\n\t" \
146                                 "orr r0, r0, #0xc0\n\t" \
147                                 "msr cpsr_c, r0" \
148                                 ::: "r0" \
149                         ); \
150                 } while (0)
151
152                 #define IRQ_ENABLE \
153                 do { \
154                         asm volatile ( \
155                                 "mrs r0, cpsr\n\t" \
156                                 "bic r0, r0, #0xc0\n\t" \
157                                 "msr cpsr_c, r0" \
158                                 ::: "r0" \
159                         ); \
160                 } while (0)
161
162                 #define IRQ_SAVE_DISABLE(x) \
163                 do { \
164                         asm volatile ( \
165                                 "mrs %0, cpsr\n\t" \
166                                 "orr r0, %0, #0xc0\n\t" \
167                                 "msr cpsr_c, r0" \
168                                 : "=r" (x) \
169                                 : /* no inputs */ \
170                                 : "r0" \
171                         ); \
172                 } while (0)
173
174                 #define IRQ_RESTORE(x) \
175                 do { \
176                         asm volatile ( \
177                                 "msr cpsr_c, %0" \
178                                 : /* no outputs */ \
179                                 : "r" (x) \
180                         ); \
181                 } while (0)
182
183                 #define IRQ_GETSTATE() \
184                 ({ \
185                         uint32_t sreg; \
186                         asm volatile ( \
187                                 "mrs %0, cpsr\n\t" \
188                                 : "=r" (sreg) \
189                                 : /* no inputs */ \
190                         ); \
191                         !((sreg & 0xc0) == 0xc0); \
192                 })
193
194         #endif /* !__IAR_SYSTEMS_ICC_ */
195
196 #elif CPU_PPC
197         #define NOP                 asm volatile ("nop" ::)
198
199         #define IRQ_DISABLE         FIXME
200         #define IRQ_ENABLE          FIXME
201         #define IRQ_SAVE_DISABLE(x) FIXME
202         #define IRQ_RESTORE(x)      FIXME
203         #define IRQ_GETSTATE()      FIXME
204
205         typedef uint32_t cpuflags_t; // FIXME
206         typedef uint32_t cpustack_t; // FIXME
207
208         /* Register counts include SREG too */
209         #define CPU_REG_BITS           (CPU_PPC32 ? 32 : 64)
210         #define CPU_REGS_CNT           FIXME
211         #define CPU_SAVED_REGS_CNT     FIXME
212         #define CPU_STACK_GROWS_UPWARD 0  //FIXME
213         #define CPU_SP_ON_EMPTY_SLOT   0  //FIXME
214         #define CPU_BYTE_ORDER         (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
215         #define CPU_HARVARD            0
216
217 #elif CPU_DSP56K
218
219         #define NOP                     asm(nop)
220         #define BREAKPOINT              asm(debug)
221         #define IRQ_DISABLE             do { asm(bfset #0x0200,SR); asm(nop); } while (0)
222         #define IRQ_ENABLE              do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
223
224         #define IRQ_SAVE_DISABLE(x)  \
225                 do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
226         #define IRQ_RESTORE(x)  \
227                 do { (void)x; asm(move x,SR); } while (0)
228
229         static inline bool irq_running(void)
230         {
231                 extern void *user_sp;
232                 return !!user_sp;
233         }
234         #define IRQ_RUNNING() irq_running()
235
236         static inline bool irq_getstate(void)
237         {
238                 uint16_t x;
239                 asm(move SR,x);
240                 return !(x & 0x0200);
241         }
242         #define IRQ_GETSTATE() irq_getstate()
243
244         typedef uint16_t cpuflags_t;
245         typedef unsigned int cpustack_t;
246
247         #define CPU_REG_BITS            16
248         #define CPU_REGS_CNT            FIXME
249         #define CPU_SAVED_REGS_CNT      8
250         #define CPU_STACK_GROWS_UPWARD  1
251         #define CPU_SP_ON_EMPTY_SLOT    0
252         #define CPU_BYTE_ORDER          CPU_BIG_ENDIAN
253         #define CPU_HARVARD             1
254
255         /* Memory is word-addessed in the DSP56K */
256         #define CPU_BITS_PER_CHAR  16
257         #define SIZEOF_SHORT        1
258         #define SIZEOF_INT          1
259         #define SIZEOF_LONG         2
260         #define SIZEOF_PTR          1
261
262 #elif CPU_AVR
263
264         #define NOP           asm volatile ("nop" ::)
265         #define IRQ_DISABLE   asm volatile ("cli" ::)
266         #define IRQ_ENABLE    asm volatile ("sei" ::)
267
268         #define IRQ_SAVE_DISABLE(x) \
269         do { \
270                 __asm__ __volatile__( \
271                         "in %0,__SREG__\n\t" \
272                         "cli" \
273                         : "=r" (x) : /* no inputs */ : "cc" \
274                 ); \
275         } while (0)
276
277         #define IRQ_RESTORE(x) \
278         do { \
279                 __asm__ __volatile__( \
280                         "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
281                 ); \
282         } while (0)
283
284         #define IRQ_GETSTATE() \
285         ({ \
286                 uint8_t sreg; \
287                 __asm__ __volatile__( \
288                         "in %0,__SREG__\n\t" \
289                         : "=r" (sreg)  /* no inputs & no clobbers */ \
290                 ); \
291                 (bool)(sreg & 0x80); \
292         })
293
294         typedef uint8_t cpuflags_t;
295         typedef uint8_t cpustack_t;
296
297         /* Register counts include SREG too */
298         #define CPU_REG_BITS            8
299         #define CPU_REGS_CNT           33
300         #define CPU_SAVED_REGS_CNT     19
301         #define CPU_STACK_GROWS_UPWARD  0
302         #define CPU_SP_ON_EMPTY_SLOT    1
303         #define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
304         #define CPU_HARVARD             1
305
306         /**
307          * Initialization value for registers in stack frame.
308          * The register index is not directly corrispondent to CPU
309          * register numbers. Index 0 is the SREG register: the initial
310          * value is all 0 but the interrupt bit (bit 7).
311          */
312         #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
313
314 #else
315         #error No CPU_... defined.
316 #endif
317
318 /**
319  * Execute \a CODE atomically with respect to interrupts.
320  *
321  * \see IRQ_SAVE_DISABLE IRQ_RESTORE
322  */
323 #define ATOMIC(CODE) \
324         do { \
325                 cpuflags_t __flags; \
326                 IRQ_SAVE_DISABLE(__flags); \
327                 CODE; \
328                 IRQ_RESTORE(__flags); \
329         } while (0)
330
331
332 /// Default for macro not defined in the right arch section
333 #ifndef CPU_REG_INIT_VALUE
334         #define CPU_REG_INIT_VALUE(reg)     0
335 #endif
336
337
338 #ifndef CPU_STACK_GROWS_UPWARD
339         #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
340 #endif
341
342 #ifndef CPU_SP_ON_EMPTY_SLOT
343         #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
344 #endif
345
346 /*
347  * Support stack handling peculiarities of a few CPUs.
348  *
349  * Most processors let their stack grow downward and
350  * keep SP pointing at the last pushed value.
351  */
352 #if !CPU_STACK_GROWS_UPWARD
353         #if !CPU_SP_ON_EMPTY_SLOT
354                 /* Most microprocessors (x86, m68k...) */
355                 #define CPU_PUSH_WORD(sp, data) \
356                         do { *--(sp) = (data); } while (0)
357                 #define CPU_POP_WORD(sp) \
358                         (*(sp)++)
359         #else
360                 /* AVR insanity */
361                 #define CPU_PUSH_WORD(sp, data) \
362                         do { *(sp)-- = (data); } while (0)
363                 #define CPU_POP_WORD(sp) \
364                         (*++(sp))
365         #endif
366
367 #else /* CPU_STACK_GROWS_UPWARD */
368
369         #if !CPU_SP_ON_EMPTY_SLOT
370                 /* DSP56K and other weirdos */
371                 #define CPU_PUSH_WORD(sp, data) \
372                         do { *++(sp) = (cpustack_t)(data); } while (0)
373                 #define CPU_POP_WORD(sp) \
374                         (*(sp)--)
375         #else
376                 #error I bet you cannot find a CPU like this
377         #endif
378 #endif
379
380
381 #if CPU_DSP56K
382         /*
383          * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
384          * RTS discards SR while returning (it does not restore it). So we push
385          * 0 to fake the same context.
386          */
387         #define CPU_PUSH_CALL_CONTEXT(sp, func) \
388                 do { \
389                         CPU_PUSH_WORD((sp), (func)); \
390                         CPU_PUSH_WORD((sp), 0x100); \
391                 } while (0);
392
393 #elif CPU_AVR
394         /*
395          * In AVR, the addresses are pushed into the stack as little-endian, while
396          * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
397          * no natural endianess).
398          */
399         #define CPU_PUSH_CALL_CONTEXT(sp, func) \
400                 do { \
401                         uint16_t funcaddr = (uint16_t)(func); \
402                         CPU_PUSH_WORD((sp), funcaddr); \
403                         CPU_PUSH_WORD((sp), funcaddr>>8); \
404                 } while (0)
405
406 #else
407         #define CPU_PUSH_CALL_CONTEXT(sp, func) \
408                 CPU_PUSH_WORD((sp), (cpustack_t)(func))
409 #endif
410
411
412 /**
413  * \name Default type sizes.
414  *
415  * These defaults are reasonable for most 16/32bit machines.
416  * Some of these macros may be overridden by CPU-specific code above.
417  *
418  * ANSI C requires that the following equations be true:
419  * \code
420  *   sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
421  *   sizeof(float) <= sizeof(double)
422  *   CPU_BITS_PER_CHAR  >= 8
423  *   CPU_BITS_PER_SHORT >= 8
424  *   CPU_BITS_PER_INT   >= 16
425  *   CPU_BITS_PER_LONG  >= 32
426  * \endcode
427  * \{
428  */
429 #ifndef SIZEOF_CHAR
430 #define SIZEOF_CHAR  1
431 #endif
432
433 #ifndef SIZEOF_SHORT
434 #define SIZEOF_SHORT  2
435 #endif
436
437 #ifndef SIZEOF_INT
438 #if CPU_REG_BITS < 32
439         #define SIZEOF_INT  2
440 #else
441         #define SIZEOF_INT  4
442 #endif
443 #endif /* !SIZEOF_INT */
444
445 #ifndef SIZEOF_LONG
446 #if CPU_REG_BITS > 32
447         #define SIZEOF_LONG  8
448 #else
449         #define SIZEOF_LONG  4
450 #endif
451 #endif
452
453 #ifndef SIZEOF_PTR
454 #if CPU_REG_BITS < 32
455         #define SIZEOF_PTR   2
456 #elif CPU_REG_BITS == 32
457         #define SIZEOF_PTR   4
458 #else /* CPU_REG_BITS > 32 */
459         #define SIZEOF_PTR   8
460 #endif
461 #endif
462
463 #ifndef CPU_BITS_PER_CHAR
464 #define CPU_BITS_PER_CHAR   (SIZEOF_CHAR * 8)
465 #endif
466
467 #ifndef CPU_BITS_PER_SHORT
468 #define CPU_BITS_PER_SHORT  (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
469 #endif
470
471 #ifndef CPU_BITS_PER_INT
472 #define CPU_BITS_PER_INT    (SIZEOF_INT * CPU_BITS_PER_CHAR)
473 #endif
474
475 #ifndef CPU_BITS_PER_LONG
476 #define CPU_BITS_PER_LONG   (SIZEOF_LONG * CPU_BITS_PER_CHAR)
477 #endif
478
479 #ifndef CPU_BITS_PER_PTR
480 #define CPU_BITS_PER_PTR    (SIZEOF_PTR * CPU_BITS_PER_CHAR)
481 #endif
482
483 #ifndef BREAKPOINT
484 #define BREAKPOINT /* nop */
485 #endif
486
487 /*\}*/
488
489 /* Sanity checks for the above definitions */
490 STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
491 STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
492 STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
493 STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
494 STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
495 STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
496 STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
497 STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
498 STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
499 STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
500 STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
501 #ifdef __HAS_INT64_T__
502 STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
503 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
504 #endif
505
506 /**
507  * \def CPU_IDLE
508  *
509  * \brief Invoked by the scheduler to stop the CPU when idle.
510  *
511  * This hook can be redefined to put the CPU in low-power mode, or to
512  * profile system load with an external strobe, or to save CPU cycles
513  * in hosted environments such as emulators.
514  */
515 #ifndef CPU_IDLE
516         #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
517                 /* This emulator hook should yield the CPU to the host.  */
518                 EXTERN_C_BEGIN
519                 void emul_idle(void);
520                 EXTERN_C_END
521                 #define CPU_IDLE emul_idle()
522         #else /* !ARCH_EMUL */
523                 #define CPU_IDLE do { /* nothing */ } while (0)
524         #endif /* !ARCH_EMUL */
525 #endif /* !CPU_IDLE */
526
527 #endif /* DEVLIB_CPU_H */