--- /dev/null
+/**\r
+ * \file\r
+ * <!--\r
+ * This file is part of BeRTOS.\r
+ *\r
+ * Bertos is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ *\r
+ * As a special exception, you may use this file as part of a free software\r
+ * library without restriction. Specifically, if other files instantiate\r
+ * templates or use macros or inline functions from this file, or you compile\r
+ * this file and link it with other files to produce an executable, this\r
+ * file does not by itself cause the resulting executable to be covered by\r
+ * the GNU General Public License. This exception does not however\r
+ * invalidate any other reasons why the executable file might be covered by\r
+ * the GNU General Public License.\r
+ *\r
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)\r
+ *\r
+ * -->\r
+ *\r
+ * \author Francesco Sacchi <batt@develer.com>\r
+ *\r
+ * LPC23xx I/O registers.\r
+ */\r
+\r
+#ifndef LPC23XX_H\r
+#define LPC23XX_H\r
+\r
+#include <cfg/compiler.h>\r
+\r
+/* Vectored Interrupt Controller (VIC) */\r
+#define VIC_BASE_ADDR 0xFFFFF000\r
+#define VICIRQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x000))\r
+#define VICFIQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x004))\r
+#define VICRawIntr (*(reg32_t *)(VIC_BASE_ADDR + 0x008))\r
+#define VICIntSelect (*(reg32_t *)(VIC_BASE_ADDR + 0x00C))\r
+#define VICIntEnable (*(reg32_t *)(VIC_BASE_ADDR + 0x010))\r
+#define VICIntEnClr (*(reg32_t *)(VIC_BASE_ADDR + 0x014))\r
+#define VICSoftInt (*(reg32_t *)(VIC_BASE_ADDR + 0x018))\r
+#define VICSoftIntClr (*(reg32_t *)(VIC_BASE_ADDR + 0x01C))\r
+#define VICProtection (*(reg32_t *)(VIC_BASE_ADDR + 0x020))\r
+#define VICSWPrioMask (*(reg32_t *)(VIC_BASE_ADDR + 0x024))\r
+\r
+#define VICVectAddr0 (*(reg32_t *)(VIC_BASE_ADDR + 0x100))\r
+#define VICVectAddr1 (*(reg32_t *)(VIC_BASE_ADDR + 0x104))\r
+#define VICVectAddr2 (*(reg32_t *)(VIC_BASE_ADDR + 0x108))\r
+#define VICVectAddr3 (*(reg32_t *)(VIC_BASE_ADDR + 0x10C))\r
+#define VICVectAddr4 (*(reg32_t *)(VIC_BASE_ADDR + 0x110))\r
+#define VICVectAddr5 (*(reg32_t *)(VIC_BASE_ADDR + 0x114))\r
+#define VICVectAddr6 (*(reg32_t *)(VIC_BASE_ADDR + 0x118))\r
+#define VICVectAddr7 (*(reg32_t *)(VIC_BASE_ADDR + 0x11C))\r
+#define VICVectAddr8 (*(reg32_t *)(VIC_BASE_ADDR + 0x120))\r
+#define VICVectAddr9 (*(reg32_t *)(VIC_BASE_ADDR + 0x124))\r
+#define VICVectAddr10 (*(reg32_t *)(VIC_BASE_ADDR + 0x128))\r
+#define VICVectAddr11 (*(reg32_t *)(VIC_BASE_ADDR + 0x12C))\r
+#define VICVectAddr12 (*(reg32_t *)(VIC_BASE_ADDR + 0x130))\r
+#define VICVectAddr13 (*(reg32_t *)(VIC_BASE_ADDR + 0x134))\r
+#define VICVectAddr14 (*(reg32_t *)(VIC_BASE_ADDR + 0x138))\r
+#define VICVectAddr15 (*(reg32_t *)(VIC_BASE_ADDR + 0x13C))\r
+#define VICVectAddr16 (*(reg32_t *)(VIC_BASE_ADDR + 0x140))\r
+#define VICVectAddr17 (*(reg32_t *)(VIC_BASE_ADDR + 0x144))\r
+#define VICVectAddr18 (*(reg32_t *)(VIC_BASE_ADDR + 0x148))\r
+#define VICVectAddr19 (*(reg32_t *)(VIC_BASE_ADDR + 0x14C))\r
+#define VICVectAddr20 (*(reg32_t *)(VIC_BASE_ADDR + 0x150))\r
+#define VICVectAddr21 (*(reg32_t *)(VIC_BASE_ADDR + 0x154))\r
+#define VICVectAddr22 (*(reg32_t *)(VIC_BASE_ADDR + 0x158))\r
+#define VICVectAddr23 (*(reg32_t *)(VIC_BASE_ADDR + 0x15C))\r
+#define VICVectAddr24 (*(reg32_t *)(VIC_BASE_ADDR + 0x160))\r
+#define VICVectAddr25 (*(reg32_t *)(VIC_BASE_ADDR + 0x164))\r
+#define VICVectAddr26 (*(reg32_t *)(VIC_BASE_ADDR + 0x168))\r
+#define VICVectAddr27 (*(reg32_t *)(VIC_BASE_ADDR + 0x16C))\r
+#define VICVectAddr28 (*(reg32_t *)(VIC_BASE_ADDR + 0x170))\r
+#define VICVectAddr29 (*(reg32_t *)(VIC_BASE_ADDR + 0x174))\r
+#define VICVectAddr30 (*(reg32_t *)(VIC_BASE_ADDR + 0x178))\r
+#define VICVectAddr31 (*(reg32_t *)(VIC_BASE_ADDR + 0x17C))\r
+\r
+/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,\r
+these registers are known as "VICVectPriority(x)". */\r
+#define VICVectCntl0 (*(reg32_t *)(VIC_BASE_ADDR + 0x200))\r
+#define VICVectCntl1 (*(reg32_t *)(VIC_BASE_ADDR + 0x204))\r
+#define VICVectCntl2 (*(reg32_t *)(VIC_BASE_ADDR + 0x208))\r
+#define VICVectCntl3 (*(reg32_t *)(VIC_BASE_ADDR + 0x20C))\r
+#define VICVectCntl4 (*(reg32_t *)(VIC_BASE_ADDR + 0x210))\r
+#define VICVectCntl5 (*(reg32_t *)(VIC_BASE_ADDR + 0x214))\r
+#define VICVectCntl6 (*(reg32_t *)(VIC_BASE_ADDR + 0x218))\r
+#define VICVectCntl7 (*(reg32_t *)(VIC_BASE_ADDR + 0x21C))\r
+#define VICVectCntl8 (*(reg32_t *)(VIC_BASE_ADDR + 0x220))\r
+#define VICVectCntl9 (*(reg32_t *)(VIC_BASE_ADDR + 0x224))\r
+#define VICVectCntl10 (*(reg32_t *)(VIC_BASE_ADDR + 0x228))\r
+#define VICVectCntl11 (*(reg32_t *)(VIC_BASE_ADDR + 0x22C))\r
+#define VICVectCntl12 (*(reg32_t *)(VIC_BASE_ADDR + 0x230))\r
+#define VICVectCntl13 (*(reg32_t *)(VIC_BASE_ADDR + 0x234))\r
+#define VICVectCntl14 (*(reg32_t *)(VIC_BASE_ADDR + 0x238))\r
+#define VICVectCntl15 (*(reg32_t *)(VIC_BASE_ADDR + 0x23C))\r
+#define VICVectCntl16 (*(reg32_t *)(VIC_BASE_ADDR + 0x240))\r
+#define VICVectCntl17 (*(reg32_t *)(VIC_BASE_ADDR + 0x244))\r
+#define VICVectCntl18 (*(reg32_t *)(VIC_BASE_ADDR + 0x248))\r
+#define VICVectCntl19 (*(reg32_t *)(VIC_BASE_ADDR + 0x24C))\r
+#define VICVectCntl20 (*(reg32_t *)(VIC_BASE_ADDR + 0x250))\r
+#define VICVectCntl21 (*(reg32_t *)(VIC_BASE_ADDR + 0x254))\r
+#define VICVectCntl22 (*(reg32_t *)(VIC_BASE_ADDR + 0x258))\r
+#define VICVectCntl23 (*(reg32_t *)(VIC_BASE_ADDR + 0x25C))\r
+#define VICVectCntl24 (*(reg32_t *)(VIC_BASE_ADDR + 0x260))\r
+#define VICVectCntl25 (*(reg32_t *)(VIC_BASE_ADDR + 0x264))\r
+#define VICVectCntl26 (*(reg32_t *)(VIC_BASE_ADDR + 0x268))\r
+#define VICVectCntl27 (*(reg32_t *)(VIC_BASE_ADDR + 0x26C))\r
+#define VICVectCntl28 (*(reg32_t *)(VIC_BASE_ADDR + 0x270))\r
+#define VICVectCntl29 (*(reg32_t *)(VIC_BASE_ADDR + 0x274))\r
+#define VICVectCntl30 (*(reg32_t *)(VIC_BASE_ADDR + 0x278))\r
+#define VICVectCntl31 (*(reg32_t *)(VIC_BASE_ADDR + 0x27C))\r
+\r
+#define VICVectAddr (*(reg32_t *)(VIC_BASE_ADDR + 0xF00))\r
+\r
+\r
+/* Pin Connect Block */\r
+#define PINSEL_BASE_ADDR 0xE002C000\r
+#define PINSEL0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x00))\r
+#define PINSEL1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x04))\r
+#define PINSEL2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x08))\r
+#define PINSEL3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x0C))\r
+#define PINSEL4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x10))\r
+#define PINSEL5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x14))\r
+#define PINSEL6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x18))\r
+#define PINSEL7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x1C))\r
+#define PINSEL8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x20))\r
+#define PINSEL9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x24))\r
+#define PINSEL10 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x28))\r
+\r
+#define PINMODE0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x40))\r
+#define PINMODE1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x44))\r
+#define PINMODE2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x48))\r
+#define PINMODE3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x4C))\r
+#define PINMODE4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x50))\r
+#define PINMODE5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x54))\r
+#define PINMODE6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x58))\r
+#define PINMODE7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x5C))\r
+#define PINMODE8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x60))\r
+#define PINMODE9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x64))\r
+\r
+/* General Purpose Input/Output (GPIO) */\r
+#define GPIO_BASE_ADDR 0xE0028000\r
+#define IOPIN0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x00))\r
+#define IOSET0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x04))\r
+#define IODIR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x08))\r
+#define IOCLR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x0C))\r
+#define IOPIN1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x10))\r
+#define IOSET1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x14))\r
+#define IODIR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x18))\r
+#define IOCLR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x1C))\r
+\r
+/* GPIO Interrupt Registers */\r
+#define IO0_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x90)) \r
+#define IO0_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x94))\r
+#define IO0_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x84))\r
+#define IO0_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x88))\r
+#define IO0_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0x8C))\r
+\r
+#define IO2_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xB0)) \r
+#define IO2_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xB4))\r
+#define IO2_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xA4))\r
+#define IO2_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xA8))\r
+#define IO2_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0xAC))\r
+\r
+#define IO_INT_STAT (*(reg32_t *)(GPIO_BASE_ADDR + 0x80))\r
+\r
+#define PARTCFG_BASE_ADDR 0x3FFF8000\r
+#define PARTCFG (*(reg32_t *)(PARTCFG_BASE_ADDR + 0x00)) \r
+\r
+/* Fast I/O setup */\r
+#define FIO_BASE_ADDR 0x3FFFC000\r
+#define FIO0DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x00)) \r
+#define FIO0MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x10))\r
+#define FIO0PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x14))\r
+#define FIO0SET (*(reg32_t *)(FIO_BASE_ADDR + 0x18))\r
+#define FIO0CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x1C))\r
+\r
+#define FIO1DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x20)) \r
+#define FIO1MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x30))\r
+#define FIO1PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x34))\r
+#define FIO1SET (*(reg32_t *)(FIO_BASE_ADDR + 0x38))\r
+#define FIO1CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x3C))\r
+\r
+#define FIO2DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x40)) \r
+#define FIO2MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x50))\r
+#define FIO2PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x54))\r
+#define FIO2SET (*(reg32_t *)(FIO_BASE_ADDR + 0x58))\r
+#define FIO2CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x5C))\r
+\r
+#define FIO3DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x60)) \r
+#define FIO3MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x70))\r
+#define FIO3PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x74))\r
+#define FIO3SET (*(reg32_t *)(FIO_BASE_ADDR + 0x78))\r
+#define FIO3CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x7C))\r
+\r
+#define FIO4DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x80)) \r
+#define FIO4MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x90))\r
+#define FIO4PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x94))\r
+#define FIO4SET (*(reg32_t *)(FIO_BASE_ADDR + 0x98))\r
+#define FIO4CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x9C))\r
+\r
+/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */\r
+#define FIO0DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x00)) \r
+#define FIO1DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x20)) \r
+#define FIO2DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x40)) \r
+#define FIO3DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x60)) \r
+#define FIO4DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x80)) \r
+\r
+#define FIO0DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x01)) \r
+#define FIO1DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21)) \r
+#define FIO2DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x41)) \r
+#define FIO3DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x61)) \r
+#define FIO4DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x81)) \r
+\r
+#define FIO0DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x02)) \r
+#define FIO1DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x22)) \r
+#define FIO2DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x42)) \r
+#define FIO3DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x62)) \r
+#define FIO4DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x82)) \r
+\r
+#define FIO0DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x03)) \r
+#define FIO1DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x23)) \r
+#define FIO2DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x43)) \r
+#define FIO3DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x63)) \r
+#define FIO4DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x83)) \r
+\r
+#define FIO0DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x00)) \r
+#define FIO1DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x20)) \r
+#define FIO2DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x40)) \r
+#define FIO3DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x60)) \r
+#define FIO4DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x80)) \r
+\r
+#define FIO0DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x02)) \r
+#define FIO1DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x22)) \r
+#define FIO2DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x42)) \r
+#define FIO3DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x62)) \r
+#define FIO4DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x82)) \r
+\r
+#define FIO0MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x10)) \r
+#define FIO1MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x30)) \r
+#define FIO2MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x50)) \r
+#define FIO3MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x70)) \r
+#define FIO4MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x90)) \r
+\r
+#define FIO0MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x11)) \r
+#define FIO1MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21)) \r
+#define FIO2MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x51)) \r
+#define FIO3MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x71)) \r
+#define FIO4MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x91)) \r
+\r
+#define FIO0MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x12)) \r
+#define FIO1MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x32)) \r
+#define FIO2MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x52)) \r
+#define FIO3MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x72)) \r
+#define FIO4MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x92)) \r
+\r
+#define FIO0MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x13)) \r
+#define FIO1MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x33)) \r
+#define FIO2MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x53)) \r
+#define FIO3MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x73)) \r
+#define FIO4MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x93)) \r
+\r
+#define FIO0MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x10)) \r
+#define FIO1MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x30)) \r
+#define FIO2MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x50)) \r
+#define FIO3MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x70)) \r
+#define FIO4MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x90)) \r
+\r
+#define FIO0MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x12)) \r
+#define FIO1MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x32)) \r
+#define FIO2MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x52)) \r
+#define FIO3MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x72)) \r
+#define FIO4MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x92)) \r
+\r
+#define FIO0PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x14)) \r
+#define FIO1PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x34)) \r
+#define FIO2PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x54)) \r
+#define FIO3PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x74)) \r
+#define FIO4PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x94)) \r
+\r
+#define FIO0PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x15)) \r
+#define FIO1PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x25)) \r
+#define FIO2PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x55)) \r
+#define FIO3PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x75)) \r
+#define FIO4PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x95)) \r
+\r
+#define FIO0PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x16)) \r
+#define FIO1PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x36)) \r
+#define FIO2PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x56)) \r
+#define FIO3PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x76)) \r
+#define FIO4PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x96)) \r
+\r
+#define FIO0PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x17)) \r
+#define FIO1PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x37)) \r
+#define FIO2PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x57)) \r
+#define FIO3PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x77)) \r
+#define FIO4PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x97)) \r
+\r
+#define FIO0PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x14)) \r
+#define FIO1PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x34)) \r
+#define FIO2PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x54)) \r
+#define FIO3PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x74)) \r
+#define FIO4PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x94)) \r
+\r
+#define FIO0PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x16)) \r
+#define FIO1PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x36)) \r
+#define FIO2PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x56)) \r
+#define FIO3PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x76)) \r
+#define FIO4PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x96)) \r
+\r
+#define FIO0SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x18)) \r
+#define FIO1SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x38)) \r
+#define FIO2SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x58)) \r
+#define FIO3SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x78)) \r
+#define FIO4SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x98)) \r
+\r
+#define FIO0SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x19)) \r
+#define FIO1SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x29)) \r
+#define FIO2SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x59)) \r
+#define FIO3SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x79)) \r
+#define FIO4SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x99)) \r
+\r
+#define FIO0SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1A)) \r
+#define FIO1SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3A)) \r
+#define FIO2SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5A)) \r
+#define FIO3SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7A)) \r
+#define FIO4SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9A)) \r
+\r
+#define FIO0SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1B)) \r
+#define FIO1SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3B)) \r
+#define FIO2SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5B)) \r
+#define FIO3SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7B)) \r
+#define FIO4SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9B)) \r
+\r
+#define FIO0SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x18)) \r
+#define FIO1SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x38)) \r
+#define FIO2SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x58)) \r
+#define FIO3SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x78)) \r
+#define FIO4SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x98)) \r
+\r
+#define FIO0SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x1A)) \r
+#define FIO1SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x3A)) \r
+#define FIO2SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x5A)) \r
+#define FIO3SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x7A)) \r
+#define FIO4SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x9A)) \r
+\r
+#define FIO0CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x1C)) \r
+#define FIO1CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x3C)) \r
+#define FIO2CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x5C)) \r
+#define FIO3CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x7C)) \r
+#define FIO4CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x9C)) \r
+\r
+#define FIO0CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x1D)) \r
+#define FIO1CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x2D)) \r
+#define FIO2CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x5D)) \r
+#define FIO3CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x7D)) \r
+#define FIO4CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x9D)) \r
+\r
+#define FIO0CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1E)) \r
+#define FIO1CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3E)) \r
+#define FIO2CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5E)) \r
+#define FIO3CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7E)) \r
+#define FIO4CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9E)) \r
+\r
+#define FIO0CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1F)) \r
+#define FIO1CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3F)) \r
+#define FIO2CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5F)) \r
+#define FIO3CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7F)) \r
+#define FIO4CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9F)) \r
+\r
+#define FIO0CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x1C)) \r
+#define FIO1CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x3C)) \r
+#define FIO2CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x5C)) \r
+#define FIO3CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x7C)) \r
+#define FIO4CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x9C)) \r
+\r
+#define FIO0CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x1E)) \r
+#define FIO1CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x3E)) \r
+#define FIO2CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x5E)) \r
+#define FIO3CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x7E)) \r
+#define FIO4CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x9E)) \r
+\r
+\r
+/* System Control Block(SCB) modules include Memory Accelerator Module,\r
+Phase Locked Loop, VPB divider, Power Control, External Interrupt, \r
+Reset, and Code Security/Debugging */\r
+#define SCB_BASE_ADDR 0xE01FC000\r
+\r
+/* Memory Accelerator Module (MAM) */\r
+#define MAMCR (*(reg32_t *)(SCB_BASE_ADDR + 0x000))\r
+#define MAMTIM (*(reg32_t *)(SCB_BASE_ADDR + 0x004))\r
+#define MEMMAP (*(reg32_t *)(SCB_BASE_ADDR + 0x040))\r
+\r
+/* Phase Locked Loop (PLL) */\r
+#define PLLCON (*(reg32_t *)(SCB_BASE_ADDR + 0x080))\r
+#define PLLCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x084))\r
+#define PLLSTAT (*(reg32_t *)(SCB_BASE_ADDR + 0x088))\r
+#define PLLFEED (*(reg32_t *)(SCB_BASE_ADDR + 0x08C))\r
+\r
+/* Power Control */\r
+#define PCON (*(reg32_t *)(SCB_BASE_ADDR + 0x0C0))\r
+#define PCONP (*(reg32_t *)(SCB_BASE_ADDR + 0x0C4))\r
+\r
+/* Clock Divider */\r
+// #define APBDIV (*(reg32_t *)(SCB_BASE_ADDR + 0x100))\r
+#define CCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x104))\r
+#define USBCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x108))\r
+#define CLKSRCSEL (*(reg32_t *)(SCB_BASE_ADDR + 0x10C))\r
+#define PCLKSEL0 (*(reg32_t *)(SCB_BASE_ADDR + 0x1A8))\r
+#define PCLKSEL1 (*(reg32_t *)(SCB_BASE_ADDR + 0x1AC))\r
+ \r
+/* External Interrupts */\r
+#define EXTINT (*(reg32_t *)(SCB_BASE_ADDR + 0x140))\r
+#define INTWAKE (*(reg32_t *)(SCB_BASE_ADDR + 0x144))\r
+#define EXTMODE (*(reg32_t *)(SCB_BASE_ADDR + 0x148))\r
+#define EXTPOLAR (*(reg32_t *)(SCB_BASE_ADDR + 0x14C))\r
+\r
+/* Reset, reset source identification */\r
+#define RSIR (*(reg32_t *)(SCB_BASE_ADDR + 0x180))\r
+\r
+/* RSID, code security protection */\r
+#define CSPR (*(reg32_t *)(SCB_BASE_ADDR + 0x184))\r
+\r
+/* AHB configuration */\r
+#define AHBCFG1 (*(reg32_t *)(SCB_BASE_ADDR + 0x188))\r
+#define AHBCFG2 (*(reg32_t *)(SCB_BASE_ADDR + 0x18C))\r
+\r
+/* System Controls and Status */\r
+#define SCS (*(reg32_t *)(SCB_BASE_ADDR + 0x1A0)) \r
+\r
+/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers \r
+are for LPC24xx only. */\r
+#define STATIC_MEM0_BASE 0x80000000\r
+#define STATIC_MEM1_BASE 0x81000000\r
+#define STATIC_MEM2_BASE 0x82000000\r
+#define STATIC_MEM3_BASE 0x83000000\r
+\r
+#define DYNAMIC_MEM0_BASE 0xA0000000\r
+#define DYNAMIC_MEM1_BASE 0xB0000000\r
+#define DYNAMIC_MEM2_BASE 0xC0000000\r
+#define DYNAMIC_MEM3_BASE 0xD0000000\r
+\r
+/* External Memory Controller (EMC) */\r
+#define EMC_BASE_ADDR 0xFFE08000\r
+#define EMC_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x000))\r
+#define EMC_STAT (*(reg32_t *)(EMC_BASE_ADDR + 0x004))\r
+#define EMC_CONFIG (*(reg32_t *)(EMC_BASE_ADDR + 0x008))\r
+\r
+/* Dynamic RAM access registers */\r
+#define EMC_DYN_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x020))\r
+#define EMC_DYN_RFSH (*(reg32_t *)(EMC_BASE_ADDR + 0x024))\r
+#define EMC_DYN_RD_CFG (*(reg32_t *)(EMC_BASE_ADDR + 0x028))\r
+#define EMC_DYN_RP (*(reg32_t *)(EMC_BASE_ADDR + 0x030))\r
+#define EMC_DYN_RAS (*(reg32_t *)(EMC_BASE_ADDR + 0x034))\r
+#define EMC_DYN_SREX (*(reg32_t *)(EMC_BASE_ADDR + 0x038))\r
+#define EMC_DYN_APR (*(reg32_t *)(EMC_BASE_ADDR + 0x03C))\r
+#define EMC_DYN_DAL (*(reg32_t *)(EMC_BASE_ADDR + 0x040))\r
+#define EMC_DYN_WR (*(reg32_t *)(EMC_BASE_ADDR + 0x044))\r
+#define EMC_DYN_RC (*(reg32_t *)(EMC_BASE_ADDR + 0x048))\r
+#define EMC_DYN_RFC (*(reg32_t *)(EMC_BASE_ADDR + 0x04C))\r
+#define EMC_DYN_XSR (*(reg32_t *)(EMC_BASE_ADDR + 0x050))\r
+#define EMC_DYN_RRD (*(reg32_t *)(EMC_BASE_ADDR + 0x054))\r
+#define EMC_DYN_MRD (*(reg32_t *)(EMC_BASE_ADDR + 0x058))\r
+\r
+#define EMC_DYN_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x100))\r
+#define EMC_DYN_RASCAS0 (*(reg32_t *)(EMC_BASE_ADDR + 0x104))\r
+#define EMC_DYN_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x140))\r
+#define EMC_DYN_RASCAS1 (*(reg32_t *)(EMC_BASE_ADDR + 0x144))\r
+#define EMC_DYN_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x160))\r
+#define EMC_DYN_RASCAS2 (*(reg32_t *)(EMC_BASE_ADDR + 0x164))\r
+#define EMC_DYN_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x180))\r
+#define EMC_DYN_RASCAS3 (*(reg32_t *)(EMC_BASE_ADDR + 0x184))\r
+\r
+/* static RAM access registers */\r
+#define EMC_STA_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x200))\r
+#define EMC_STA_WAITWEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x204))\r
+#define EMC_STA_WAITOEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x208))\r
+#define EMC_STA_WAITRD0 (*(reg32_t *)(EMC_BASE_ADDR + 0x20C))\r
+#define EMC_STA_WAITPAGE0 (*(reg32_t *)(EMC_BASE_ADDR + 0x210))\r
+#define EMC_STA_WAITWR0 (*(reg32_t *)(EMC_BASE_ADDR + 0x214))\r
+#define EMC_STA_WAITTURN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x218))\r
+\r
+#define EMC_STA_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x220))\r
+#define EMC_STA_WAITWEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x224))\r
+#define EMC_STA_WAITOEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x228))\r
+#define EMC_STA_WAITRD1 (*(reg32_t *)(EMC_BASE_ADDR + 0x22C))\r
+#define EMC_STA_WAITPAGE1 (*(reg32_t *)(EMC_BASE_ADDR + 0x230))\r
+#define EMC_STA_WAITWR1 (*(reg32_t *)(EMC_BASE_ADDR + 0x234))\r
+#define EMC_STA_WAITTURN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x238))\r
+\r
+#define EMC_STA_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x240))\r
+#define EMC_STA_WAITWEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x244))\r
+#define EMC_STA_WAITOEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x248))\r
+#define EMC_STA_WAITRD2 (*(reg32_t *)(EMC_BASE_ADDR + 0x24C))\r
+#define EMC_STA_WAITPAGE2 (*(reg32_t *)(EMC_BASE_ADDR + 0x250))\r
+#define EMC_STA_WAITWR2 (*(reg32_t *)(EMC_BASE_ADDR + 0x254))\r
+#define EMC_STA_WAITTURN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x258))\r
+\r
+#define EMC_STA_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x260))\r
+#define EMC_STA_WAITWEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x264))\r
+#define EMC_STA_WAITOEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x268))\r
+#define EMC_STA_WAITRD3 (*(reg32_t *)(EMC_BASE_ADDR + 0x26C))\r
+#define EMC_STA_WAITPAGE3 (*(reg32_t *)(EMC_BASE_ADDR + 0x270))\r
+#define EMC_STA_WAITWR3 (*(reg32_t *)(EMC_BASE_ADDR + 0x274))\r
+#define EMC_STA_WAITTURN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x278))\r
+\r
+#define EMC_STA_EXT_WAIT (*(reg32_t *)(EMC_BASE_ADDR + 0x880))\r
+\r
+ \r
+/* Timer 0 */\r
+#define TMR0_BASE_ADDR 0xE0004000\r
+#define T0IR (*(reg32_t *)(TMR0_BASE_ADDR + 0x00))\r
+#define T0TCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x04))\r
+#define T0TC (*(reg32_t *)(TMR0_BASE_ADDR + 0x08))\r
+#define T0PR (*(reg32_t *)(TMR0_BASE_ADDR + 0x0C))\r
+#define T0PC (*(reg32_t *)(TMR0_BASE_ADDR + 0x10))\r
+#define T0MCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x14))\r
+#define T0MR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x18))\r
+#define T0MR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x1C))\r
+#define T0MR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x20))\r
+#define T0MR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x24))\r
+#define T0CCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x28))\r
+#define T0CR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x2C))\r
+#define T0CR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x30))\r
+#define T0CR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x34))\r
+#define T0CR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x38))\r
+#define T0EMR (*(reg32_t *)(TMR0_BASE_ADDR + 0x3C))\r
+#define T0CTCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x70))\r
+\r
+/* Timer 1 */\r
+#define TMR1_BASE_ADDR 0xE0008000\r
+#define T1IR (*(reg32_t *)(TMR1_BASE_ADDR + 0x00))\r
+#define T1TCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x04))\r
+#define T1TC (*(reg32_t *)(TMR1_BASE_ADDR + 0x08))\r
+#define T1PR (*(reg32_t *)(TMR1_BASE_ADDR + 0x0C))\r
+#define T1PC (*(reg32_t *)(TMR1_BASE_ADDR + 0x10))\r
+#define T1MCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x14))\r
+#define T1MR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x18))\r
+#define T1MR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x1C))\r
+#define T1MR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x20))\r
+#define T1MR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x24))\r
+#define T1CCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x28))\r
+#define T1CR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x2C))\r
+#define T1CR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x30))\r
+#define T1CR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x34))\r
+#define T1CR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x38))\r
+#define T1EMR (*(reg32_t *)(TMR1_BASE_ADDR + 0x3C))\r
+#define T1CTCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x70))\r
+\r
+/* Timer 2 */\r
+#define TMR2_BASE_ADDR 0xE0070000\r
+#define T2IR (*(reg32_t *)(TMR2_BASE_ADDR + 0x00))\r
+#define T2TCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x04))\r
+#define T2TC (*(reg32_t *)(TMR2_BASE_ADDR + 0x08))\r
+#define T2PR (*(reg32_t *)(TMR2_BASE_ADDR + 0x0C))\r
+#define T2PC (*(reg32_t *)(TMR2_BASE_ADDR + 0x10))\r
+#define T2MCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x14))\r
+#define T2MR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x18))\r
+#define T2MR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x1C))\r
+#define T2MR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x20))\r
+#define T2MR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x24))\r
+#define T2CCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x28))\r
+#define T2CR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x2C))\r
+#define T2CR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x30))\r
+#define T2CR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x34))\r
+#define T2CR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x38))\r
+#define T2EMR (*(reg32_t *)(TMR2_BASE_ADDR + 0x3C))\r
+#define T2CTCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x70))\r
+\r
+/* Timer 3 */\r
+#define TMR3_BASE_ADDR 0xE0074000\r
+#define T3IR (*(reg32_t *)(TMR3_BASE_ADDR + 0x00))\r
+#define T3TCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x04))\r
+#define T3TC (*(reg32_t *)(TMR3_BASE_ADDR + 0x08))\r
+#define T3PR (*(reg32_t *)(TMR3_BASE_ADDR + 0x0C))\r
+#define T3PC (*(reg32_t *)(TMR3_BASE_ADDR + 0x10))\r
+#define T3MCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x14))\r
+#define T3MR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x18))\r
+#define T3MR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x1C))\r
+#define T3MR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x20))\r
+#define T3MR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x24))\r
+#define T3CCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x28))\r
+#define T3CR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x2C))\r
+#define T3CR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x30))\r
+#define T3CR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x34))\r
+#define T3CR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x38))\r
+#define T3EMR (*(reg32_t *)(TMR3_BASE_ADDR + 0x3C))\r
+#define T3CTCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x70))\r
+\r
+\r
+/* Pulse Width Modulator (PWM) */\r
+#define PWM0_BASE_ADDR 0xE0014000\r
+#define PWM0IR (*(reg32_t *)(PWM0_BASE_ADDR + 0x00))\r
+#define PWM0TCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x04))\r
+#define PWM0TC (*(reg32_t *)(PWM0_BASE_ADDR + 0x08))\r
+#define PWM0PR (*(reg32_t *)(PWM0_BASE_ADDR + 0x0C))\r
+#define PWM0PC (*(reg32_t *)(PWM0_BASE_ADDR + 0x10))\r
+#define PWM0MCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x14))\r
+#define PWM0MR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x18))\r
+#define PWM0MR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x1C))\r
+#define PWM0MR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x20))\r
+#define PWM0MR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x24))\r
+#define PWM0CCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x28))\r
+#define PWM0CR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x2C))\r
+#define PWM0CR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x30))\r
+#define PWM0CR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x34))\r
+#define PWM0CR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x38))\r
+#define PWM0EMR (*(reg32_t *)(PWM0_BASE_ADDR + 0x3C))\r
+#define PWM0MR4 (*(reg32_t *)(PWM0_BASE_ADDR + 0x40))\r
+#define PWM0MR5 (*(reg32_t *)(PWM0_BASE_ADDR + 0x44))\r
+#define PWM0MR6 (*(reg32_t *)(PWM0_BASE_ADDR + 0x48))\r
+#define PWM0PCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x4C))\r
+#define PWM0LER (*(reg32_t *)(PWM0_BASE_ADDR + 0x50))\r
+#define PWM0CTCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x70))\r
+\r
+#define PWM1_BASE_ADDR 0xE0018000\r
+#define PWM1IR (*(reg32_t *)(PWM1_BASE_ADDR + 0x00))\r
+#define PWM1TCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x04))\r
+#define PWM1TC (*(reg32_t *)(PWM1_BASE_ADDR + 0x08))\r
+#define PWM1PR (*(reg32_t *)(PWM1_BASE_ADDR + 0x0C))\r
+#define PWM1PC (*(reg32_t *)(PWM1_BASE_ADDR + 0x10))\r
+#define PWM1MCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x14))\r
+#define PWM1MR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x18))\r
+#define PWM1MR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x1C))\r
+#define PWM1MR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x20))\r
+#define PWM1MR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x24))\r
+#define PWM1CCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x28))\r
+#define PWM1CR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x2C))\r
+#define PWM1CR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x30))\r
+#define PWM1CR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x34))\r
+#define PWM1CR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x38))\r
+#define PWM1EMR (*(reg32_t *)(PWM1_BASE_ADDR + 0x3C))\r
+#define PWM1MR4 (*(reg32_t *)(PWM1_BASE_ADDR + 0x40))\r
+#define PWM1MR5 (*(reg32_t *)(PWM1_BASE_ADDR + 0x44))\r
+#define PWM1MR6 (*(reg32_t *)(PWM1_BASE_ADDR + 0x48))\r
+#define PWM1PCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x4C))\r
+#define PWM1LER (*(reg32_t *)(PWM1_BASE_ADDR + 0x50))\r
+#define PWM1CTCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x70))\r
+\r
+\r
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */\r
+#define UART0_BASE_ADDR 0xE000C000\r
+#define U0RBR (*(reg32_t *)(UART0_BASE_ADDR + 0x00))\r
+#define U0THR (*(reg32_t *)(UART0_BASE_ADDR + 0x00))\r
+#define U0DLL (*(reg32_t *)(UART0_BASE_ADDR + 0x00))\r
+#define U0DLM (*(reg32_t *)(UART0_BASE_ADDR + 0x04))\r
+#define U0IER (*(reg32_t *)(UART0_BASE_ADDR + 0x04))\r
+#define U0IIR (*(reg32_t *)(UART0_BASE_ADDR + 0x08))\r
+#define U0FCR (*(reg32_t *)(UART0_BASE_ADDR + 0x08))\r
+#define U0LCR (*(reg32_t *)(UART0_BASE_ADDR + 0x0C))\r
+#define U0LSR (*(reg32_t *)(UART0_BASE_ADDR + 0x14))\r
+#define U0SCR (*(reg32_t *)(UART0_BASE_ADDR + 0x1C))\r
+#define U0ACR (*(reg32_t *)(UART0_BASE_ADDR + 0x20))\r
+#define U0ICR (*(reg32_t *)(UART0_BASE_ADDR + 0x24))\r
+#define U0FDR (*(reg32_t *)(UART0_BASE_ADDR + 0x28))\r
+#define U0TER (*(reg32_t *)(UART0_BASE_ADDR + 0x30))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 1 (UART1) */\r
+#define UART1_BASE_ADDR 0xE0010000\r
+#define U1RBR (*(reg32_t *)(UART1_BASE_ADDR + 0x00))\r
+#define U1THR (*(reg32_t *)(UART1_BASE_ADDR + 0x00))\r
+#define U1DLL (*(reg32_t *)(UART1_BASE_ADDR + 0x00))\r
+#define U1DLM (*(reg32_t *)(UART1_BASE_ADDR + 0x04))\r
+#define U1IER (*(reg32_t *)(UART1_BASE_ADDR + 0x04))\r
+#define U1IIR (*(reg32_t *)(UART1_BASE_ADDR + 0x08))\r
+#define U1FCR (*(reg32_t *)(UART1_BASE_ADDR + 0x08))\r
+#define U1LCR (*(reg32_t *)(UART1_BASE_ADDR + 0x0C))\r
+#define U1MCR (*(reg32_t *)(UART1_BASE_ADDR + 0x10))\r
+#define U1LSR (*(reg32_t *)(UART1_BASE_ADDR + 0x14))\r
+#define U1MSR (*(reg32_t *)(UART1_BASE_ADDR + 0x18))\r
+#define U1SCR (*(reg32_t *)(UART1_BASE_ADDR + 0x1C))\r
+#define U1ACR (*(reg32_t *)(UART1_BASE_ADDR + 0x20))\r
+#define U1FDR (*(reg32_t *)(UART1_BASE_ADDR + 0x28))\r
+#define U1TER (*(reg32_t *)(UART1_BASE_ADDR + 0x30))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 2 (UART2) */\r
+#define UART2_BASE_ADDR 0xE0078000\r
+#define U2RBR (*(reg32_t *)(UART2_BASE_ADDR + 0x00))\r
+#define U2THR (*(reg32_t *)(UART2_BASE_ADDR + 0x00))\r
+#define U2DLL (*(reg32_t *)(UART2_BASE_ADDR + 0x00))\r
+#define U2DLM (*(reg32_t *)(UART2_BASE_ADDR + 0x04))\r
+#define U2IER (*(reg32_t *)(UART2_BASE_ADDR + 0x04))\r
+#define U2IIR (*(reg32_t *)(UART2_BASE_ADDR + 0x08))\r
+#define U2FCR (*(reg32_t *)(UART2_BASE_ADDR + 0x08))\r
+#define U2LCR (*(reg32_t *)(UART2_BASE_ADDR + 0x0C))\r
+#define U2LSR (*(reg32_t *)(UART2_BASE_ADDR + 0x14))\r
+#define U2SCR (*(reg32_t *)(UART2_BASE_ADDR + 0x1C))\r
+#define U2ACR (*(reg32_t *)(UART2_BASE_ADDR + 0x20))\r
+#define U2ICR (*(reg32_t *)(UART2_BASE_ADDR + 0x24))\r
+#define U2FDR (*(reg32_t *)(UART2_BASE_ADDR + 0x28))\r
+#define U2TER (*(reg32_t *)(UART2_BASE_ADDR + 0x30))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 3 (UART3) */\r
+#define UART3_BASE_ADDR 0xE007C000\r
+#define U3RBR (*(reg32_t *)(UART3_BASE_ADDR + 0x00))\r
+#define U3THR (*(reg32_t *)(UART3_BASE_ADDR + 0x00))\r
+#define U3DLL (*(reg32_t *)(UART3_BASE_ADDR + 0x00))\r
+#define U3DLM (*(reg32_t *)(UART3_BASE_ADDR + 0x04))\r
+#define U3IER (*(reg32_t *)(UART3_BASE_ADDR + 0x04))\r
+#define U3IIR (*(reg32_t *)(UART3_BASE_ADDR + 0x08))\r
+#define U3FCR (*(reg32_t *)(UART3_BASE_ADDR + 0x08))\r
+#define U3LCR (*(reg32_t *)(UART3_BASE_ADDR + 0x0C))\r
+#define U3LSR (*(reg32_t *)(UART3_BASE_ADDR + 0x14))\r
+#define U3SCR (*(reg32_t *)(UART3_BASE_ADDR + 0x1C))\r
+#define U3ACR (*(reg32_t *)(UART3_BASE_ADDR + 0x20))\r
+#define U3ICR (*(reg32_t *)(UART3_BASE_ADDR + 0x24))\r
+#define U3FDR (*(reg32_t *)(UART3_BASE_ADDR + 0x28))\r
+#define U3TER (*(reg32_t *)(UART3_BASE_ADDR + 0x30))\r
+\r
+/* I2C Interface 0 */\r
+#define I2C0_BASE_ADDR 0xE001C000\r
+#define I20CONSET (*(reg32_t *)(I2C0_BASE_ADDR + 0x00))\r
+#define I20STAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x04))\r
+#define I20DAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x08))\r
+#define I20ADR (*(reg32_t *)(I2C0_BASE_ADDR + 0x0C))\r
+#define I20SCLH (*(reg32_t *)(I2C0_BASE_ADDR + 0x10))\r
+#define I20SCLL (*(reg32_t *)(I2C0_BASE_ADDR + 0x14))\r
+#define I20CONCLR (*(reg32_t *)(I2C0_BASE_ADDR + 0x18))\r
+\r
+/* I2C Interface 1 */\r
+#define I2C1_BASE_ADDR 0xE005C000\r
+#define I21CONSET (*(reg32_t *)(I2C1_BASE_ADDR + 0x00))\r
+#define I21STAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x04))\r
+#define I21DAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x08))\r
+#define I21ADR (*(reg32_t *)(I2C1_BASE_ADDR + 0x0C))\r
+#define I21SCLH (*(reg32_t *)(I2C1_BASE_ADDR + 0x10))\r
+#define I21SCLL (*(reg32_t *)(I2C1_BASE_ADDR + 0x14))\r
+#define I21CONCLR (*(reg32_t *)(I2C1_BASE_ADDR + 0x18))\r
+\r
+/* I2C Interface 2 */\r
+#define I2C2_BASE_ADDR 0xE0080000\r
+#define I22CONSET (*(reg32_t *)(I2C2_BASE_ADDR + 0x00))\r
+#define I22STAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x04))\r
+#define I22DAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x08))\r
+#define I22ADR (*(reg32_t *)(I2C2_BASE_ADDR + 0x0C))\r
+#define I22SCLH (*(reg32_t *)(I2C2_BASE_ADDR + 0x10))\r
+#define I22SCLL (*(reg32_t *)(I2C2_BASE_ADDR + 0x14))\r
+#define I22CONCLR (*(reg32_t *)(I2C2_BASE_ADDR + 0x18))\r
+\r
+/* SPI0 (Serial Peripheral Interface 0) */\r
+#define SPI0_BASE_ADDR 0xE0020000\r
+#define S0SPCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x00))\r
+#define S0SPSR (*(reg32_t *)(SPI0_BASE_ADDR + 0x04))\r
+#define S0SPDR (*(reg32_t *)(SPI0_BASE_ADDR + 0x08))\r
+#define S0SPCCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x0C))\r
+#define S0SPINT (*(reg32_t *)(SPI0_BASE_ADDR + 0x1C))\r
+\r
+/* SSP0 Controller */\r
+#define SSP0_BASE_ADDR 0xE0068000\r
+#define SSP0CR0 (*(reg32_t *)(SSP0_BASE_ADDR + 0x00))\r
+#define SSP0CR1 (*(reg32_t *)(SSP0_BASE_ADDR + 0x04))\r
+#define SSP0DR (*(reg32_t *)(SSP0_BASE_ADDR + 0x08))\r
+#define SSP0SR (*(reg32_t *)(SSP0_BASE_ADDR + 0x0C))\r
+#define SSP0CPSR (*(reg32_t *)(SSP0_BASE_ADDR + 0x10))\r
+#define SSP0IMSC (*(reg32_t *)(SSP0_BASE_ADDR + 0x14))\r
+#define SSP0RIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x18))\r
+#define SSP0MIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x1C))\r
+#define SSP0ICR (*(reg32_t *)(SSP0_BASE_ADDR + 0x20))\r
+#define SSP0DMACR (*(reg32_t *)(SSP0_BASE_ADDR + 0x24))\r
+\r
+/* SSP1 Controller */\r
+#define SSP1_BASE_ADDR 0xE0030000\r
+#define SSP1CR0 (*(reg32_t *)(SSP1_BASE_ADDR + 0x00))\r
+#define SSP1CR1 (*(reg32_t *)(SSP1_BASE_ADDR + 0x04))\r
+#define SSP1DR (*(reg32_t *)(SSP1_BASE_ADDR + 0x08))\r
+#define SSP1SR (*(reg32_t *)(SSP1_BASE_ADDR + 0x0C))\r
+#define SSP1CPSR (*(reg32_t *)(SSP1_BASE_ADDR + 0x10))\r
+#define SSP1IMSC (*(reg32_t *)(SSP1_BASE_ADDR + 0x14))\r
+#define SSP1RIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x18))\r
+#define SSP1MIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x1C))\r
+#define SSP1ICR (*(reg32_t *)(SSP1_BASE_ADDR + 0x20))\r
+#define SSP1DMACR (*(reg32_t *)(SSP1_BASE_ADDR + 0x24))\r
+\r
+\r
+/* Real Time Clock */\r
+#define RTC_BASE_ADDR 0xE0024000\r
+#define RTC_ILR (*(reg32_t *)(RTC_BASE_ADDR + 0x00))\r
+#define RTC_CTC (*(reg32_t *)(RTC_BASE_ADDR + 0x04))\r
+#define RTC_CCR (*(reg32_t *)(RTC_BASE_ADDR + 0x08))\r
+#define RTC_CIIR (*(reg32_t *)(RTC_BASE_ADDR + 0x0C))\r
+#define RTC_AMR (*(reg32_t *)(RTC_BASE_ADDR + 0x10))\r
+#define RTC_CTIME0 (*(reg32_t *)(RTC_BASE_ADDR + 0x14))\r
+#define RTC_CTIME1 (*(reg32_t *)(RTC_BASE_ADDR + 0x18))\r
+#define RTC_CTIME2 (*(reg32_t *)(RTC_BASE_ADDR + 0x1C))\r
+#define RTC_SEC (*(reg32_t *)(RTC_BASE_ADDR + 0x20))\r
+#define RTC_MIN (*(reg32_t *)(RTC_BASE_ADDR + 0x24))\r
+#define RTC_HOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x28))\r
+#define RTC_DOM (*(reg32_t *)(RTC_BASE_ADDR + 0x2C))\r
+#define RTC_DOW (*(reg32_t *)(RTC_BASE_ADDR + 0x30))\r
+#define RTC_DOY (*(reg32_t *)(RTC_BASE_ADDR + 0x34))\r
+#define RTC_MONTH (*(reg32_t *)(RTC_BASE_ADDR + 0x38))\r
+#define RTC_YEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x3C))\r
+#define RTC_CISS (*(reg32_t *)(RTC_BASE_ADDR + 0x40))\r
+#define RTC_ALSEC (*(reg32_t *)(RTC_BASE_ADDR + 0x60))\r
+#define RTC_ALMIN (*(reg32_t *)(RTC_BASE_ADDR + 0x64))\r
+#define RTC_ALHOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x68))\r
+#define RTC_ALDOM (*(reg32_t *)(RTC_BASE_ADDR + 0x6C))\r
+#define RTC_ALDOW (*(reg32_t *)(RTC_BASE_ADDR + 0x70))\r
+#define RTC_ALDOY (*(reg32_t *)(RTC_BASE_ADDR + 0x74))\r
+#define RTC_ALMON (*(reg32_t *)(RTC_BASE_ADDR + 0x78))\r
+#define RTC_ALYEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x7C))\r
+#define RTC_PREINT (*(reg32_t *)(RTC_BASE_ADDR + 0x80))\r
+#define RTC_PREFRAC (*(reg32_t *)(RTC_BASE_ADDR + 0x84))\r
+\r
+\r
+/* A/D Converter 0 (AD0) */\r
+#define AD0_BASE_ADDR 0xE0034000\r
+#define AD0CR (*(reg32_t *)(AD0_BASE_ADDR + 0x00))\r
+#define AD0GDR (*(reg32_t *)(AD0_BASE_ADDR + 0x04))\r
+#define AD0INTEN (*(reg32_t *)(AD0_BASE_ADDR + 0x0C))\r
+#define AD0DR0 (*(reg32_t *)(AD0_BASE_ADDR + 0x10))\r
+#define AD0DR1 (*(reg32_t *)(AD0_BASE_ADDR + 0x14))\r
+#define AD0DR2 (*(reg32_t *)(AD0_BASE_ADDR + 0x18))\r
+#define AD0DR3 (*(reg32_t *)(AD0_BASE_ADDR + 0x1C))\r
+#define AD0DR4 (*(reg32_t *)(AD0_BASE_ADDR + 0x20))\r
+#define AD0DR5 (*(reg32_t *)(AD0_BASE_ADDR + 0x24))\r
+#define AD0DR6 (*(reg32_t *)(AD0_BASE_ADDR + 0x28))\r
+#define AD0DR7 (*(reg32_t *)(AD0_BASE_ADDR + 0x2C))\r
+#define AD0STAT (*(reg32_t *)(AD0_BASE_ADDR + 0x30))\r
+\r
+\r
+/* D/A Converter */\r
+#define DAC_BASE_ADDR 0xE006C000\r
+#define DACR (*(reg32_t *)(DAC_BASE_ADDR + 0x00))\r
+\r
+\r
+/* Watchdog */\r
+#define WDG_BASE_ADDR 0xE0000000\r
+#define WDMOD (*(reg32_t *)(WDG_BASE_ADDR + 0x00))\r
+#define WDTC (*(reg32_t *)(WDG_BASE_ADDR + 0x04))\r
+#define WDFEED (*(reg32_t *)(WDG_BASE_ADDR + 0x08))\r
+#define WDTV (*(reg32_t *)(WDG_BASE_ADDR + 0x0C))\r
+#define WDCLKSEL (*(reg32_t *)(WDG_BASE_ADDR + 0x10))\r
+\r
+/* CAN CONTROLLERS AND ACCEPTANCE FILTER */\r
+#define CAN_ACCEPT_BASE_ADDR 0xE003C000\r
+#define CAN_AFMR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x00)) \r
+#define CAN_SFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x04)) \r
+#define CAN_SFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x08))\r
+#define CAN_EFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x0C))\r
+#define CAN_EFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x10)) \r
+#define CAN_EOT (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x14))\r
+#define CAN_LUT_ERR_ADR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x18)) \r
+#define CAN_LUT_ERR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x1C))\r
+\r
+#define CAN_CENTRAL_BASE_ADDR 0xE0040000 \r
+#define CAN_TX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x00)) \r
+#define CAN_RX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x04)) \r
+#define CAN_MSR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x08))\r
+\r
+#define CAN1_BASE_ADDR 0xE0044000\r
+#define CAN1MOD (*(reg32_t *)(CAN1_BASE_ADDR + 0x00)) \r
+#define CAN1CMR (*(reg32_t *)(CAN1_BASE_ADDR + 0x04)) \r
+#define CAN1GSR (*(reg32_t *)(CAN1_BASE_ADDR + 0x08)) \r
+#define CAN1ICR (*(reg32_t *)(CAN1_BASE_ADDR + 0x0C)) \r
+#define CAN1IER (*(reg32_t *)(CAN1_BASE_ADDR + 0x10))\r
+#define CAN1BTR (*(reg32_t *)(CAN1_BASE_ADDR + 0x14)) \r
+#define CAN1EWL (*(reg32_t *)(CAN1_BASE_ADDR + 0x18)) \r
+#define CAN1SR (*(reg32_t *)(CAN1_BASE_ADDR + 0x1C)) \r
+#define CAN1RFS (*(reg32_t *)(CAN1_BASE_ADDR + 0x20)) \r
+#define CAN1RID (*(reg32_t *)(CAN1_BASE_ADDR + 0x24))\r
+#define CAN1RDA (*(reg32_t *)(CAN1_BASE_ADDR + 0x28)) \r
+#define CAN1RDB (*(reg32_t *)(CAN1_BASE_ADDR + 0x2C))\r
+ \r
+#define CAN1TFI1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x30)) \r
+#define CAN1TID1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x34)) \r
+#define CAN1TDA1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x38))\r
+#define CAN1TDB1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x3C)) \r
+#define CAN1TFI2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x40)) \r
+#define CAN1TID2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x44)) \r
+#define CAN1TDA2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x48)) \r
+#define CAN1TDB2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x4C))\r
+#define CAN1TFI3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x50)) \r
+#define CAN1TID3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x54)) \r
+#define CAN1TDA3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x58)) \r
+#define CAN1TDB3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x5C))\r
+\r
+#define CAN2_BASE_ADDR 0xE0048000\r
+#define CAN2MOD (*(reg32_t *)(CAN2_BASE_ADDR + 0x00)) \r
+#define CAN2CMR (*(reg32_t *)(CAN2_BASE_ADDR + 0x04)) \r
+#define CAN2GSR (*(reg32_t *)(CAN2_BASE_ADDR + 0x08)) \r
+#define CAN2ICR (*(reg32_t *)(CAN2_BASE_ADDR + 0x0C)) \r
+#define CAN2IER (*(reg32_t *)(CAN2_BASE_ADDR + 0x10))\r
+#define CAN2BTR (*(reg32_t *)(CAN2_BASE_ADDR + 0x14)) \r
+#define CAN2EWL (*(reg32_t *)(CAN2_BASE_ADDR + 0x18)) \r
+#define CAN2SR (*(reg32_t *)(CAN2_BASE_ADDR + 0x1C)) \r
+#define CAN2RFS (*(reg32_t *)(CAN2_BASE_ADDR + 0x20)) \r
+#define CAN2RID (*(reg32_t *)(CAN2_BASE_ADDR + 0x24))\r
+#define CAN2RDA (*(reg32_t *)(CAN2_BASE_ADDR + 0x28)) \r
+#define CAN2RDB (*(reg32_t *)(CAN2_BASE_ADDR + 0x2C))\r
+ \r
+#define CAN2TFI1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x30)) \r
+#define CAN2TID1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x34)) \r
+#define CAN2TDA1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x38))\r
+#define CAN2TDB1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x3C)) \r
+#define CAN2TFI2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x40)) \r
+#define CAN2TID2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x44)) \r
+#define CAN2TDA2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x48)) \r
+#define CAN2TDB2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x4C))\r
+#define CAN2TFI3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x50)) \r
+#define CAN2TID3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x54)) \r
+#define CAN2TDA3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x58)) \r
+#define CAN2TDB3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x5C))\r
+\r
+\r
+/* MultiMedia Card Interface(MCI) Controller */\r
+#define MCI_BASE_ADDR 0xE008C000\r
+#define MCI_POWER (*(reg32_t *)(MCI_BASE_ADDR + 0x00))\r
+#define MCI_CLOCK (*(reg32_t *)(MCI_BASE_ADDR + 0x04))\r
+#define MCI_ARGUMENT (*(reg32_t *)(MCI_BASE_ADDR + 0x08))\r
+#define MCI_COMMAND (*(reg32_t *)(MCI_BASE_ADDR + 0x0C))\r
+#define MCI_RESP_CMD (*(reg32_t *)(MCI_BASE_ADDR + 0x10))\r
+#define MCI_RESP0 (*(reg32_t *)(MCI_BASE_ADDR + 0x14))\r
+#define MCI_RESP1 (*(reg32_t *)(MCI_BASE_ADDR + 0x18))\r
+#define MCI_RESP2 (*(reg32_t *)(MCI_BASE_ADDR + 0x1C))\r
+#define MCI_RESP3 (*(reg32_t *)(MCI_BASE_ADDR + 0x20))\r
+#define MCI_DATA_TMR (*(reg32_t *)(MCI_BASE_ADDR + 0x24))\r
+#define MCI_DATA_LEN (*(reg32_t *)(MCI_BASE_ADDR + 0x28))\r
+#define MCI_DATA_CTRL (*(reg32_t *)(MCI_BASE_ADDR + 0x2C))\r
+#define MCI_DATA_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x30))\r
+#define MCI_STATUS (*(reg32_t *)(MCI_BASE_ADDR + 0x34))\r
+#define MCI_CLEAR (*(reg32_t *)(MCI_BASE_ADDR + 0x38))\r
+#define MCI_MASK0 (*(reg32_t *)(MCI_BASE_ADDR + 0x3C))\r
+#define MCI_MASK1 (*(reg32_t *)(MCI_BASE_ADDR + 0x40))\r
+#define MCI_FIFO_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x48))\r
+#define MCI_FIFO (*(reg32_t *)(MCI_BASE_ADDR + 0x80))\r
+\r
+\r
+/* I2S Interface Controller (I2S) */\r
+#define I2S_BASE_ADDR 0xE0088000\r
+#define I2S_DAO (*(reg32_t *)(I2S_BASE_ADDR + 0x00))\r
+#define I2S_DAI (*(reg32_t *)(I2S_BASE_ADDR + 0x04))\r
+#define I2S_TX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x08))\r
+#define I2S_RX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x0C))\r
+#define I2S_STATE (*(reg32_t *)(I2S_BASE_ADDR + 0x10))\r
+#define I2S_DMA1 (*(reg32_t *)(I2S_BASE_ADDR + 0x14))\r
+#define I2S_DMA2 (*(reg32_t *)(I2S_BASE_ADDR + 0x18))\r
+#define I2S_IRQ (*(reg32_t *)(I2S_BASE_ADDR + 0x1C))\r
+#define I2S_TXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x20))\r
+#define I2S_RXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x24))\r
+\r
+\r
+/* General-purpose DMA Controller */\r
+#define DMA_BASE_ADDR 0xFFE04000\r
+#define GPDMA_INT_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x000))\r
+#define GPDMA_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x004))\r
+#define GPDMA_INT_TCCLR (*(reg32_t *)(DMA_BASE_ADDR + 0x008))\r
+#define GPDMA_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x00C))\r
+#define GPDMA_INT_ERR_CLR (*(reg32_t *)(DMA_BASE_ADDR + 0x010))\r
+#define GPDMA_RAW_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x014))\r
+#define GPDMA_RAW_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x018))\r
+#define GPDMA_ENABLED_CHNS (*(reg32_t *)(DMA_BASE_ADDR + 0x01C))\r
+#define GPDMA_SOFT_BREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x020))\r
+#define GPDMA_SOFT_SREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x024))\r
+#define GPDMA_SOFT_LBREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x028))\r
+#define GPDMA_SOFT_LSREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x02C))\r
+#define GPDMA_CONFIG (*(reg32_t *)(DMA_BASE_ADDR + 0x030))\r
+#define GPDMA_SYNC (*(reg32_t *)(DMA_BASE_ADDR + 0x034))\r
+\r
+/* DMA channel 0 registers */\r
+#define GPDMA_CH0_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x100))\r
+#define GPDMA_CH0_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x104))\r
+#define GPDMA_CH0_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x108))\r
+#define GPDMA_CH0_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x10C))\r
+#define GPDMA_CH0_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x110))\r
+\r
+/* DMA channel 1 registers */\r
+#define GPDMA_CH1_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x120))\r
+#define GPDMA_CH1_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x124))\r
+#define GPDMA_CH1_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x128))\r
+#define GPDMA_CH1_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x12C))\r
+#define GPDMA_CH1_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x130))\r
+\r
+\r
+/* USB Controller */\r
+#define USB_INT_BASE_ADDR 0xE01FC1C0\r
+#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */\r
+\r
+#define USB_INT_STAT (*(reg32_t *)(USB_INT_BASE_ADDR + 0x00))\r
+\r
+/* USB Device Interrupt Registers */\r
+#define DEV_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x00))\r
+#define DEV_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x04))\r
+#define DEV_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x08))\r
+#define DEV_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x0C))\r
+#define DEV_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x2C))\r
+\r
+/* USB Device Endpoint Interrupt Registers */\r
+#define EP_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x30))\r
+#define EP_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x34))\r
+#define EP_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x38))\r
+#define EP_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x3C))\r
+#define EP_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x40))\r
+\r
+/* USB Device Endpoint Realization Registers */\r
+#define REALIZE_EP (*(reg32_t *)(USB_BASE_ADDR + 0x44))\r
+#define EP_INDEX (*(reg32_t *)(USB_BASE_ADDR + 0x48))\r
+#define MAXPACKET_SIZE (*(reg32_t *)(USB_BASE_ADDR + 0x4C))\r
+\r
+/* USB Device Command Reagisters */\r
+#define CMD_CODE (*(reg32_t *)(USB_BASE_ADDR + 0x10))\r
+#define CMD_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x14))\r
+\r
+/* USB Device Data Transfer Registers */\r
+#define RX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x18))\r
+#define TX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x1C))\r
+#define RX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x20))\r
+#define TX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x24))\r
+#define USB_CTRL (*(reg32_t *)(USB_BASE_ADDR + 0x28))\r
+\r
+/* USB Device DMA Registers */\r
+#define DMA_REQ_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x50))\r
+#define DMA_REQ_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x54))\r
+#define DMA_REQ_SET (*(reg32_t *)(USB_BASE_ADDR + 0x58))\r
+#define UDCA_HEAD (*(reg32_t *)(USB_BASE_ADDR + 0x80))\r
+#define EP_DMA_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x84))\r
+#define EP_DMA_EN (*(reg32_t *)(USB_BASE_ADDR + 0x88))\r
+#define EP_DMA_DIS (*(reg32_t *)(USB_BASE_ADDR + 0x8C))\r
+#define DMA_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x90))\r
+#define DMA_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x94))\r
+#define EOT_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xA0))\r
+#define EOT_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xA4))\r
+#define EOT_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xA8))\r
+#define NDD_REQ_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xAC))\r
+#define NDD_REQ_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xB0))\r
+#define NDD_REQ_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xB4))\r
+#define SYS_ERR_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xB8))\r
+#define SYS_ERR_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xBC))\r
+#define SYS_ERR_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xC0))\r
+\r
+/* USB Host and OTG registers are for LPC24xx only */\r
+/* USB Host Controller */\r
+#define USBHC_BASE_ADDR 0xFFE0C000\r
+#define HC_REVISION (*(reg32_t *)(USBHC_BASE_ADDR + 0x00))\r
+#define HC_CONTROL (*(reg32_t *)(USBHC_BASE_ADDR + 0x04))\r
+#define HC_CMD_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x08))\r
+#define HC_INT_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x0C))\r
+#define HC_INT_EN (*(reg32_t *)(USBHC_BASE_ADDR + 0x10))\r
+#define HC_INT_DIS (*(reg32_t *)(USBHC_BASE_ADDR + 0x14))\r
+#define HC_HCCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x18))\r
+#define HC_PERIOD_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x1C))\r
+#define HC_CTRL_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x20))\r
+#define HC_CTRL_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x24))\r
+#define HC_BULK_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x28))\r
+#define HC_BULK_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x2C))\r
+#define HC_DONE_HEAD (*(reg32_t *)(USBHC_BASE_ADDR + 0x30))\r
+#define HC_FM_INTERVAL (*(reg32_t *)(USBHC_BASE_ADDR + 0x34))\r
+#define HC_FM_REMAINING (*(reg32_t *)(USBHC_BASE_ADDR + 0x38))\r
+#define HC_FM_NUMBER (*(reg32_t *)(USBHC_BASE_ADDR + 0x3C))\r
+#define HC_PERIOD_START (*(reg32_t *)(USBHC_BASE_ADDR + 0x40))\r
+#define HC_LS_THRHLD (*(reg32_t *)(USBHC_BASE_ADDR + 0x44))\r
+#define HC_RH_DESCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x48))\r
+#define HC_RH_DESCB (*(reg32_t *)(USBHC_BASE_ADDR + 0x4C))\r
+#define HC_RH_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x50))\r
+#define HC_RH_PORT_STAT1 (*(reg32_t *)(USBHC_BASE_ADDR + 0x54))\r
+#define HC_RH_PORT_STAT2 (*(reg32_t *)(USBHC_BASE_ADDR + 0x58))\r
+\r
+/* USB OTG Controller */\r
+#define USBOTG_BASE_ADDR 0xFFE0C100\r
+#define OTG_INT_STAT (*(reg32_t *)(USBOTG_BASE_ADDR + 0x00))\r
+#define OTG_INT_EN (*(reg32_t *)(USBOTG_BASE_ADDR + 0x04))\r
+#define OTG_INT_SET (*(reg32_t *)(USBOTG_BASE_ADDR + 0x08))\r
+#define OTG_INT_CLR (*(reg32_t *)(USBOTG_BASE_ADDR + 0x0C))\r
+/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ \r
+#define OTG_STAT_CTRL (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10))\r
+#define OTG_TIMER (*(reg32_t *)(USBOTG_BASE_ADDR + 0x14))\r
+\r
+#define USBOTG_I2C_BASE_ADDR 0xFFE0C300\r
+#define OTG_I2C_RX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00))\r
+#define OTG_I2C_TX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00))\r
+#define OTG_I2C_STS (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x04))\r
+#define OTG_I2C_CTL (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x08))\r
+#define OTG_I2C_CLKHI (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x0C))\r
+#define OTG_I2C_CLKLO (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x10))\r
+\r
+/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are \r
+OTG_CLK_CTRL and OTG_CLK_STAT respectively. */\r
+#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0\r
+#define OTG_CLK_CTRL (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04))\r
+#define OTG_CLK_STAT (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08))\r
+\r
+/* Note: below three register name convention is for LPC23xx USB device only, match\r
+with the spec. update in USB Device Section. */ \r
+#define USBPortSel (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10))\r
+#define USBClkCtrl (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04))\r
+#define USBClkSt (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08))\r
+\r
+/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */\r
+#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */\r
+#define MAC_MAC1 (*(reg32_t *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */\r
+#define MAC_MAC2 (*(reg32_t *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */\r
+#define MAC_IPGT (*(reg32_t *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */\r
+#define MAC_IPGR (*(reg32_t *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */\r
+#define MAC_CLRT (*(reg32_t *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */\r
+#define MAC_MAXF (*(reg32_t *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */\r
+#define MAC_SUPP (*(reg32_t *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */\r
+#define MAC_TEST (*(reg32_t *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */\r
+#define MAC_MCFG (*(reg32_t *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */\r
+#define MAC_MCMD (*(reg32_t *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */\r
+#define MAC_MADR (*(reg32_t *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */\r
+#define MAC_MWTD (*(reg32_t *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */\r
+#define MAC_MRDD (*(reg32_t *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */\r
+#define MAC_MIND (*(reg32_t *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */\r
+\r
+#define MAC_SA0 (*(reg32_t *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */\r
+#define MAC_SA1 (*(reg32_t *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */\r
+#define MAC_SA2 (*(reg32_t *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */\r
+\r
+#define MAC_COMMAND (*(reg32_t *)(MAC_BASE_ADDR + 0x100)) /* Command reg */\r
+#define MAC_STATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */\r
+#define MAC_RXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */\r
+#define MAC_RXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */\r
+#define MAC_RXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */\r
+#define MAC_RXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */\r
+#define MAC_RXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */\r
+#define MAC_TXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */\r
+#define MAC_TXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */\r
+#define MAC_TXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */\r
+#define MAC_TXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */\r
+#define MAC_TXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */\r
+\r
+#define MAC_TSV0 (*(reg32_t *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */\r
+#define MAC_TSV1 (*(reg32_t *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */\r
+#define MAC_RSV (*(reg32_t *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */\r
+\r
+#define MAC_FLOWCONTROLCNT (*(reg32_t *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */\r
+#define MAC_FLOWCONTROLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */\r
+\r
+#define MAC_RXFILTERCTRL (*(reg32_t *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */\r
+#define MAC_RXFILTERWOLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */\r
+#define MAC_RXFILTERWOLCLR (*(reg32_t *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */\r
+\r
+#define MAC_HASHFILTERL (*(reg32_t *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */\r
+#define MAC_HASHFILTERH (*(reg32_t *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */\r
+\r
+#define MAC_INTSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */\r
+#define MAC_INTENABLE (*(reg32_t *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */\r
+#define MAC_INTCLEAR (*(reg32_t *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */\r
+#define MAC_INTSET (*(reg32_t *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */\r
+\r
+#define MAC_POWERDOWN (*(reg32_t *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */\r
+#define MAC_MODULEID (*(reg32_t *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */\r
+\r
+#endif /* LPC23XX_H */\r
projects / bertos.git / commitdiff