Use dmac for data blk transfer from sd. Fix set bus with function. Clean up.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@5010 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c
index 3cd4a4eaac2163a425ff53f54a69161dbc5c6734..b32d688be173e9adac02914c16f7449f0d6cdf3a 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c
@@ -43,10 +43,20 @@
 
 #include <io/cm3.h>
 
+/** DMA Transfer Descriptor as well as Linked List Item */
+typedef struct DmacDesc
+{
+    uint32_t src_addr;     /**< Source buffer address */
+    uint32_t dst_addr;     /**< Destination buffer address */
+    uint32_t ctrl_a;       /**< Control A register settings */
+    uint32_t ctrl_b;       /**< Control B register settings */
+    uint32_t dsc_addr;     /**< Next descriptor address */
+} DmacDesc;
+
+
 
 
-#define HSMCI_INIT_SPEED  400000
-#define HSMCI_CLK_DIV     ((CPU_FREQ / (HSMCI_INIT_SPEED << 1)) - 1)
+#define HSMCI_CLK_DIV(RATE)     ((CPU_FREQ / (RATE << 1)) - 1)
 
 #define HSMCI_ERROR_MASK   (BV(HSMCI_SR_RINDE)    | \
                                                        BV(HSMCI_SR_RDIRE)    | \
@@ -63,6 +73,8 @@
 #define HSMCI_RESP_ERROR_MASK   (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
          | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
 
+#define HSMCI_DATA_ERROR_MASK   (BV(HSMCI_SR_DCRCE) | BV(HSMCI_SR_DTOE))
+
 #define HSMCI_READY_MASK     (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY))
 #define HSMCI_WAIT()\
        do { \
@@ -94,20 +106,30 @@ do { \
 
 static DECLARE_ISR(hsmci_irq)
 {
-       if (HSMCI_SR & BV(HSMCI_IER_RTOE))
+       uint32_t status = HSMCI_SR;
+       if (status & BV(HSMCI_IER_DMADONE))
+       {
+               kputs("\n\nfatto\n\n");
+       }
+}
+
+
+static DECLARE_ISR(dmac_irq)
+{
+       uint32_t stat = DMAC_EBCISR;
+
+       if (stat & BV(DMAC_EBCISR_ERR3))
        {
-               HSMCI_ARGR = 0;
-               HSMCI_CMDR = 0 | HSMCI_CMDR_RSPTYP_NORESP | BV(HSMCI_CMDR_OPDCMD);
+               kprintf("err %08lx\n", stat);
        }
 }
 
-void hsmci_readResp(void *resp, size_t len)
+void hsmci_readResp(uint32_t *resp, size_t len)
 {
        ASSERT(resp);
-       uint32_t *r = (uint32_t *)resp;
 
        for (size_t i = 0; i < len ; i++)
-               r[i] = HSMCI_RSPR;
+               resp[i] = HSMCI_RSPR;
 }
 
 bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
@@ -116,7 +138,7 @@ bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
        HSMCI_WAIT();
 
        HSMCI_ARGR = argument;
-       HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT) | BV(HSMCI_CMDR_OPDCMD);
+       HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT);// | BV(HSMCI_CMDR_OPDCMD);
 
        uint32_t status = HSMCI_SR;
        while (!(status & BV(HSMCI_SR_CMDRDY)))
@@ -133,35 +155,84 @@ bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
        return 0;
 }
 
-void hsmci_setBlkSize(size_t blk_size)
+INLINE void hsmci_setBlockSize(size_t blk_size)
 {
-       HSMCI_DMA = BV(HSMCI_DMA_DMAEN);
-       HSMCI_BLKR = (blk_size << HSMCI_BLKR_BLKLEN_SHIFT);
+       HSMCI_IER = BV(HSMCI_IER_DMADONE);
+       HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
+       HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
 }
 
-bool hsmci_read(uint32_t *buf, size_t word_num)
+void hsmci_prgTxDMA(uint32_t *buf, size_t word_num, size_t blk_size)
 {
-       ASSERT(buf);
+
+       hsmci_setBlockSize(blk_size);
+
+       DMAC_CHDR = BV(DMAC_CHDR_DIS0);
+
+       DMAC_SADDR0 = (uint32_t)buf;
+       DMAC_DADDR0 = (uint32_t)&HSMCI_TDR;
+       DMAC_DSCR0 = 0;
+
+       DMAC_CTRLA0 = (word_num & DMAC_CTRLA_BTSIZE_MASK) |
+               DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
+       DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | DMAC_CTRLB_FC_MEM2PER_DMA_FC |
+                                       DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING | BV(DMAC_CTRLB_IEN));
+
+       kprintf("SDDR %08lx\n", DMAC_SADDR0);
+       kprintf("DDDR %08lx\n", DMAC_DADDR0);
+       kprintf("CTRA %08lx\n", DMAC_CTRLA0);
+       kprintf("CTRB %08lx\n", DMAC_CTRLB0);
+       kprintf("EBCI %08lx\n", DMAC_EBCISR);
+       kprintf("CHSR %08lx\n", DMAC_CHSR);
+
        ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
+       DMAC_CHER = BV(DMAC_CHER_ENA0);
+
+}
+
+void hsmci_prgRxDMA(uint32_t *buf, size_t word_num, size_t blk_size)
+{
+       hsmci_setBlockSize(blk_size);
 
-       kprintf("DMAC status %08lx channel st %08lx\n", DMAC_EBCISR, DMAC_CHSR);
+       DMAC_CHDR = BV(DMAC_CHDR_DIS0);
 
-       DMAC_SADDR0 = 0x40000200U;
+       DMAC_SADDR0 = (uint32_t)&HSMCI_RDR;
        DMAC_DADDR0 = (uint32_t)buf;
        DMAC_DSCR0 = 0;
 
-       DMAC_CTRLA0 = word_num | DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
-       DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
-                                       DMAC_CTRLB_SRC_INCR_FIXED | DMAC_CTRLB_DST_INCR_INCREMENTING | BV(DMAC_CTRLB_IEN));
+       DMAC_CTRLA0 = (word_num & DMAC_CTRLA_BTSIZE_MASK) |
+               DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
+       DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
+                                       DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED | BV(DMAC_CTRLB_IEN));
+
+       kprintf("SDDR %08lx\n", DMAC_SADDR0);
+       kprintf("DDDR %08lx\n", DMAC_DADDR0);
+       kprintf("CTRA %08lx\n", DMAC_CTRLA0);
+       kprintf("CTRB %08lx\n", DMAC_CTRLB0);
+       kprintf("EBCI %08lx\n", DMAC_EBCISR);
+       kprintf("CHSR %08lx\n", DMAC_CHSR);
 
        ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
        DMAC_CHER = BV(DMAC_CHER_ENA0);
+}
 
+
+void hsmci_waitTransfer(void)
+{
        while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE)))
                cpu_relax();
+}
 
-       DMAC_CHDR = BV(DMAC_CHDR_DIS0);
-       return 0;
+void hsmci_setSpeed(uint32_t data_rate, int flag)
+{
+       if (flag)
+               HSMCI_CFG |= BV(HSMCI_CFG_HSMODE);
+       else
+               HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE);
+
+       HSMCI_MR = HSMCI_CLK_DIV(data_rate) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK);
+
+       timer_delay(10);
 }
 
 void hsmci_init(Hsmci *hsmci)
@@ -178,23 +249,23 @@ void hsmci_init(Hsmci *hsmci)
 
        HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576;
        HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576;
-       HSMCI_MR = HSMCI_CLK_DIV | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK) | BV(HSMCI_MR_RDPROOF);
-       HSMCI_SDCR = 0;
+       HSMCI_MR = HSMCI_CLK_DIV(HSMCI_INIT_SPEED) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK) | BV(HSMCI_MR_RDPROOF);
        HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL);
 
        sysirq_setHandler(INT_HSMCI, hsmci_irq);
        HSMCI_CR = BV(HSMCI_CR_MCIEN);
-       HSMCI_DMA &= ~BV(HSMCI_DMA_DMAEN);
+       HSMCI_DMA = 0;
+
 
        //init DMAC
        DMAC_EBCIDR = 0x3FFFFF;
-       DMAC_CHDR = BV(DMAC_CHDR_DIS0);
-
-       DMAC_CFG0 = 0;
-       DMAC_CFG0 = BV(DMAC_CFG_SRC_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | BV(DMAC_CFG_SOD);
+       DMAC_CHDR = 0x1F;
+       DMAC_CFG0 = BV(DMAC_CFG_SRC_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
 
        pmc_periphEnable(DMAC_ID);
        DMAC_EN = BV(DMAC_EN_ENABLE);
+       sysirq_setHandler(INT_DMAC, dmac_irq);
+
+       DMAC_EBCIER = BV(DMAC_EBCIER_BTC0) | BV(DMAC_EBCIER_ERR0);
 
-       //HSMCI_IER = BV(HSMCI_IER_RTOE);
 }

diff --git a/bertos/cpu/cortex-m3/drv/hsmci_sam3.h b/bertos/cpu/cortex-m3/drv/hsmci_sam3.h
index f5cebdc776a8610e8329f6fe975431aa84ed3672..61fb878d5b495dc2096d1da3a8bf1b5991f326ab 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/hsmci_sam3.h
+++ b/bertos/cpu/cortex-m3/drv/hsmci_sam3.h
@@ -74,6 +74,7 @@
        } while (!(HSMCI_SR & BV(HSMCI_SR_NOTBUSY)))
 
 
+#define HSMCI_INIT_SPEED  400000
 
 typedef struct Hsmci
 {
@@ -91,15 +92,24 @@ INLINE void hsmci_disableIrq(void)
 
 INLINE void hsmci_setBusWidth(size_t len)
 {
-       ASSERT((len == 8) || (len == 4) || (len == 1));
-       HSMCI_SDCR = (len << HSMCI_SDCR_SDCBUS_SHIFT) & HSMCI_SDCR_SDCBUS_MASK;
+       int sdcsel= 0;
+       if (len == 4)
+               sdcsel = 2;
+       if (len == 8)
+               sdcsel = 3;
+
+       HSMCI_SDCR = (sdcsel << HSMCI_SDCR_SDCBUS_SHIFT) & HSMCI_SDCR_SDCBUS_MASK;
 }
 
-void hsmci_readResp(void *resp, size_t len);
+void hsmci_readResp(uint32_t *resp, size_t len);
 bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type);
 
-void hsmci_setBlkSize(size_t blk_size);
-bool hsmci_read(uint32_t *buf, size_t word_num);
+void hsmci_prgRxDMA(uint32_t *buf, size_t word_num, size_t blk_size);
+void hsmci_prgTxDMA(uint32_t *buf, size_t word_num, size_t blk_size);
+void hsmci_waitTransfer(void);
+
+void hsmci_setSpeed(uint32_t data_rate, int flag);
+