*/
uint8_t afsk_dac_isr(Afsk *af)
{
*/
uint8_t afsk_dac_isr(Afsk *af)
{
/* Check if we are at a start of a sample cycle */
if (af->sample_count == 0)
{
/* Check if we are at a start of a sample cycle */
if (af->sample_count == 0)
{
{
AFSK_DAC_IRQ_STOP(af->dac_ch);
af->sending = false;
{
AFSK_DAC_IRQ_STOP(af->dac_ch);
af->sending = false;
{
AFSK_DAC_IRQ_STOP(af->dac_ch);
af->sending = false;
{
AFSK_DAC_IRQ_STOP(af->dac_ch);
af->sending = false;
af->phase_acc %= SIN_LEN;
af->sample_count--;
af->phase_acc %= SIN_LEN;
af->sample_count--;
return sin_sample(af->phase_acc);
}
return sin_sample(af->phase_acc);
}