Add support for at91sam7x.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@1059 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/cpu/arm/drv/kdebug_at91.c b/cpu/arm/drv/kdebug_at91.c
index a5ec8343e7362a8fd30edd55bb516f4700f1ae41..64b3845f37ea3a07dafec6cf694a3abaf2646939 100644 (file)
--- a/cpu/arm/drv/kdebug_at91.c
+++ b/cpu/arm/drv/kdebug_at91.c
@@ -76,7 +76,7 @@ INLINE void kdbg_hw_init(void)
                DBGU_MR =  US_CHMODE_NORMAL | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1;
                /* Enable DBGU transmitter. */
                DBGU_CR = BV(US_TXEN);
-               #if !CPU_ARM_AT91SAM7S256
+               #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256
                        #warning Check Debug Unit AT91 pins on datasheet!
                #endif
                /* Disable PIO on DGBU tx pin. */

diff --git a/cpu/arm/drv/ser_at91.c b/cpu/arm/drv/ser_at91.c
index 14027e896604990fc3f07fc7277726c808d8fcd8..9f3ed4b9f1ac64a75bb0f7237b737c29cc6b25ef 100644 (file)
--- a/cpu/arm/drv/ser_at91.c
+++ b/cpu/arm/drv/ser_at91.c
@@ -101,17 +101,17 @@
         *
         * - Disable GPIO on USART0 tx/rx pins
         * - Reset USART0
-        * - Set serial param: mode Normal, 8bit data, 1bit stop
+        * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
         * - Enable both the receiver and the transmitter
         * - Enable only the RX complete interrupt
         */
-       #if !CPU_ARM_AT91SAM7S256
+       #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256
                #warning Check USART0 pins!
        #endif
        #define SER_UART0_BUS_TXINIT do { \
                PIOA_PDR = BV(RXD0) | BV(TXD0); \
                US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \
-               US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
+               US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO; \
                US0_CR = BV(US_RXEN) | BV(US_TXEN); \
                US0_IER = BV(US_RXRDY); \
        } while (0)
@@ -173,13 +173,13 @@
 
 #ifndef SER_UART1_BUS_TXINIT
        /** \sa SER_UART1_BUS_TXINIT */
-       #if !CPU_ARM_AT91SAM7S256
+       #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256
                #warning Check USART1 pins!
        #endif
        #define SER_UART1_BUS_TXINIT do { \
                PIOA_PDR = BV(RXD1) | BV(TXD1); \
                US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \
-               US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
+               US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO; \
                US1_CR = BV(US_RXEN) | BV(US_TXEN); \
                US1_IER = BV(US_RXRDY); \
        } while (0)

diff --git a/cpu/arm/io/at91.h b/cpu/arm/io/at91.h
index 0c2feb15aba6e2a4cc2faaf02b6af9fe6beff191..7bdde9b9a72cd4af7cecb9d43c0b7d79a7f75027 100644 (file)
--- a/cpu/arm/io/at91.h
+++ b/cpu/arm/io/at91.h
@@ -75,8 +75,9 @@
 
 #include <cpu/detect.h>
 
-#if CPU_ARM_AT91SAM7S256
-       #include "at91sam7s256.h"
+#if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256
+       #include "at91sam7.h"
+
 #else
        #error Missing I/O definitions for CPU.
 #endif