Fix comment.
authorasterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Mon, 23 May 2011 16:37:20 +0000 (16:37 +0000)
committerasterix <asterix@38d2e660-2303-0410-9eaa-f027e97ec537>
Mon, 23 May 2011 16:37:20 +0000 (16:37 +0000)
git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4916 38d2e660-2303-0410-9eaa-f027e97ec537

bertos/cpu/cortex-m3/io/sam3_dacc.h

index 0848a3b2e317904784cb84df3b0ce7dcbbe3b826..562d5f495f988ff486dc3e3edb6973bce0556930 100644 (file)
 /**
  * DACC Interrupt disable register
  */
-#define DACC_IMR_OFF             0x0000002C     ///< Interrupt disable register offeset.
-#define DACC_IMR          (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF)))    ///< Interrupt disable register address.
+#define DACC_IMR_OFF             0x0000002C     ///< Interrupt mask register offeset.
+#define DACC_IMR          (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF)))    ///< Interrupt mask register address.
 
 /**
  * DACC Interrupt status register
 
 #define DACC_TXRDY                        0     ///< Transmit ready interrupt
 #define DACC_EOC                          1     ///< End of conversion interrupt
-#define DACC_ENDTX                        2     ///< End of transmit buffer interrupt
+#define DACC_ENDTX                        2     ///< End of DMA Interrupt Flag
 #define DACC_TXBUFE                       3     ///< Transmit buffer empty interrupt