Crate new SDK tag.

git-svn-id: https://src.develer.com/svnoss/bertos/tags/sdk-current@5001 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/VERSION b/VERSION
index 7778da7318c4d46c851fb2772945ce33fa1cbdc2..74da158d18d9ba165a6b300cc22c0e4136f00ee5 100644 (file)
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-BeRTOS 2.7.0-rc1
+BeRTOS 2.7.0

diff --git a/bertos/cpu/cortex-m3/io/sam3_pmc.h b/bertos/cpu/cortex-m3/io/sam3_pmc.h
index 7c02328f315da9c1567adcc207a2a7774c442c0b..5bac08a7df0d7aecc61b9addeebf3dd01dd7f911 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_pmc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_pmc.h
@@ -95,6 +95,25 @@
 #endif
 /*\}*/
 
+
+/**
+ * Programmable clock ids.
+ * \{
+ */
+#define  PMC_PCK0_ID   8
+#define  PMC_PCK1_ID   9
+#define  PMC_PCK2_ID  10
+/*\}*/
+
+/**
+ * Programmable clock status.
+ * \{
+ */
+#define PMC_PCKRDY0                          8  ///< Programmable clock 0 ready.
+#define PMC_PCKRDY1                          9  ///< Programmable clock 1 ready.
+#define PMC_PCKRDY2                         10  ///< Programmable clock 2 ready.
+/*\}*/
+
 /**
  * PMC registers.
  */
@@ -126,16 +145,16 @@
        #define PMC_PCER0  (*((reg32_t *)(PMC_BASE + PMC_PCER0_OFF)))     ///< Peripheral Clock Enable Register
        #define PMC_PCDR0  (*((reg32_t *)(PMC_BASE + PMC_PCDR0_OFF)))     ///< Peripheral Clock Disable Register
        #define PMC_PCSR0  (*((reg32_t *)(PMC_BASE + PMC_PCSR0_OFF)))     ///< Peripheral Clock Status Register
-       #define PMC_UCKR   (*((reg32_t *)(PMC_BASE + PMC_UCKR _OFF)))     ///< UTMI clock register
+       #define PMC_UCKR   (*((reg32_t *)(PMC_BASE + PMC_UCKR_OFF)))     ///< UTMI clock register
        #define CKGR_PLLAR (*((reg32_t *)(PMC_BASE + PMC_PLLAR_OFF)))     ///< PLL Register
        #define PMC_USB_O  (*((reg32_t *)(PMC_BASE + PMC_USB_O_OFF)))     ///< USB clock register
-       #define PMC_PCK0   (*((reg32_t *)(PMC_BASE + PMC_PCK0 _OFF)))     ///< Programmable Clock 0 Register
-       #define PMC_PCK1   (*((reg32_t *)(PMC_BASE + PMC_PCK1 _OFF)))     ///< Programmable Clock 1 Register
-       #define PMC_PCK2   (*((reg32_t *)(PMC_BASE + PMC_PCK2 _OFF)))     ///< Programmable Clock 2 Register
+       #define PMC_PCK0   (*((reg32_t *)(PMC_BASE + PMC_PCK0_OFF)))     ///< Programmable Clock 0 Register
+       #define PMC_PCK1   (*((reg32_t *)(PMC_BASE + PMC_PCK1_OFF)))     ///< Programmable Clock 1 Register
+       #define PMC_PCK2   (*((reg32_t *)(PMC_BASE + PMC_PCK2_OFF)))     ///< Programmable Clock 2 Register
        #define PMC_PCER1  (*((reg32_t *)(PMC_BASE + PMC_PCER1_OFF)))     ///< Peripheral Clock Enable Register
        #define PMC_PCDR1  (*((reg32_t *)(PMC_BASE + PMC_PCDR1_OFF)))     ///< Peripheral Clock Disable Register
        #define PMC_PCSR1  (*((reg32_t *)(PMC_BASE + PMC_PCSR1_OFF)))     ///< Peripheral Clock Status Register
-       #define PMC_PCR    (*((reg32_t *)(PMC_BASE + PMC_PCR  _OFF)))     ///< Oscillator Calibration Register
+       #define PMC_PCR    (*((reg32_t *)(PMC_BASE + PMC_PCR_OFF)))     ///< Oscillator Calibration Register
 
        #define CKGR_PLLR  CKGR_PLLAR
 #endif
@@ -231,9 +250,9 @@ INLINE void pmc_periphDisable(unsigned id)
 #define CKGR_MOR_MOSCRCF_SHIFT    4
 #define CKGR_MOR_MOSCRCF_MASK     (0x7 << CKGR_MOR_MOSCRCF_SHIFT)   ///< Main On-Chip RC Oscillator Frequency Selection
 #define CKGR_MOR_MOSCRCF(value)   ((CKGR_MOR_MOSCRCF_MASK & ((value) << CKGR_MOR_MOSCRCF_SHIFT)))
-#define   CKGR_MOR_MOSCRCF_4MHZ   (0x0 << CKGR_MOR_MOSCRCF_SHIFT)
-#define   CKGR_MOR_MOSCRCF_8MHZ   (0x1 << CKGR_MOR_MOSCRCF_SHIFT)
-#define   CKGR_MOR_MOSCRCF_12MHZ  (0x2 << CKGR_MOR_MOSCRCF_SHIFT)
+#define CKGR_MOR_MOSCRCF_4MHZ   (0x0 << CKGR_MOR_MOSCRCF_SHIFT)
+#define CKGR_MOR_MOSCRCF_8MHZ   (0x1 << CKGR_MOR_MOSCRCF_SHIFT)
+#define CKGR_MOR_MOSCRCF_12MHZ  (0x2 << CKGR_MOR_MOSCRCF_SHIFT)
 #define CKGR_MOR_MOSCXTST_SHIFT   8
 #define CKGR_MOR_MOSCXTST_MASK    (0xff << CKGR_MOR_MOSCXTST_SHIFT)   ///< Main Crystal Oscillator Start-up Time
 #define CKGR_MOR_MOSCXTST(value)  ((CKGR_MOR_MOSCXTST_MASK & ((value) << CKGR_MOR_MOSCXTST_SHIFT)))
@@ -271,12 +290,12 @@ INLINE void pmc_periphDisable(unsigned id)
  * Defines for bit fields in PMC_MCKR register.
  */
 /*\{*/
-#define PMC_MCKR_CSS_MASK        0x3   ///< Master Clock Source Selection mask
+#define   PMC_MCKR_CSS_MASK        0x3   ///< Master Clock Source Selection mask
 #define   PMC_MCKR_CSS_SLOW_CLK  0x0   ///< Slow Clock is selected
 #define   PMC_MCKR_CSS_MAIN_CLK  0x1   ///< Main Clock is selected
 #define   PMC_MCKR_CSS_PLL_CLK   0x2   ///< PLL Clock is selected
-#define PMC_MCKR_PRES_SHIFT      4
-#define PMC_MCKR_PRES_MASK       (0x7 << PMC_MCKR_PRES_SHIFT)    ///< Processor Clock Prescaler mask
+#define   PMC_MCKR_PRES_SHIFT      4
+#define   PMC_MCKR_PRES_MASK       (0x7 << PMC_MCKR_PRES_SHIFT)    ///< Processor Clock Prescaler mask
 #define   PMC_MCKR_PRES_CLK      (0x0 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock
 #define   PMC_MCKR_PRES_CLK_2    (0x1 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 2
 #define   PMC_MCKR_PRES_CLK_4    (0x2 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 4
@@ -285,20 +304,20 @@ INLINE void pmc_periphDisable(unsigned id)
 #define   PMC_MCKR_PRES_CLK_32   (0x5 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 32
 #define   PMC_MCKR_PRES_CLK_64   (0x6 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 64
 #define   PMC_MCKR_PRES_CLK_3    (0x7 << PMC_MCKR_PRES_SHIFT)   ///< Selected clock divided by 3
-#define PMC_MCKR_PLLDIV2         12   ///< PLL Divisor by 2
+#define   PMC_MCKR_PLLDIV2         12   ///< PLL Divisor by 2
 /*\}*/
 
 /**
  * Defines for bit fields in PMC_PCK[3] register.
  */
 /*\{*/
-#define PMC_PCK_CSS_MASK       0x7   ///< Master Clock Source Selection mask
+#define   PMC_PCK_CSS_MASK     0x7   ///< Master Clock Source Selection mask
 #define   PMC_PCK_CSS_SLOW     0x0   ///< Slow Clock is selected
 #define   PMC_PCK_CSS_MAIN     0x1   ///< Main Clock is selected
 #define   PMC_PCK_CSS_PLL      0x2   ///< PLL Clock is selected
 #define   PMC_PCK_CSS_MCK      0x4   ///< Master Clock is selected
-#define PMC_PCK_PRES_SHIFT 4
-#define PMC_PCK_PRES_MASK      (0x7 << PMC_PCK_PRES_SHIFT)   ///< Programmable Clock Prescaler
+#define   PMC_PCK_PRES_SHIFT     4
+#define   PMC_PCK_PRES_MASK    (0x7 << PMC_PCK_PRES_SHIFT)   ///< Programmable Clock Prescaler
 #define   PMC_PCK_PRES_CLK     (0x0 << PMC_PCK_PRES_SHIFT)   ///< Selected clock
 #define   PMC_PCK_PRES_CLK_2   (0x1 << PMC_PCK_PRES_SHIFT)   ///< Selected clock divided by 2
 #define   PMC_PCK_PRES_CLK_4   (0x2 << PMC_PCK_PRES_SHIFT)   ///< Selected clock divided by 4

diff --git a/bertos/net/lwip/src/arch/sys_arch.c b/bertos/net/lwip/src/arch/sys_arch.c
index d626f0cfd09933c66d6d9c9e3462808fa95dfd5d..b883529c1ddf48d0f58bbc956ccb46da60889253 100644 (file)
--- a/bertos/net/lwip/src/arch/sys_arch.c
+++ b/bertos/net/lwip/src/arch/sys_arch.c
@@ -1,7 +1,7 @@
 #include "cfg/cfg_lwip.h"
 
-#define LOG_LEVEL  3
-#define LOG_FORMAT 0
+#define LOG_LEVEL  3 //INFO
+#define LOG_FORMAT 0 //TERSE
 #include <cfg/log.h>
 
 #include <drv/timer.h>
@@ -153,6 +153,7 @@ u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
                mutex_obtain(sem);
                return ticks_to_ms(timer_clock() - start);
        }
+
        do
        {
                cpu_relax();
@@ -197,6 +198,7 @@ sys_mbox_t sys_mbox_new(UNUSED_ARG(int, size))
                return SYS_MBOX_NULL;
        }
        msg_initPort(&port->port, event_createGeneric());
+       port->port.event.Ev.Sig.sig_proc = NULL;
 
        return (sys_mbox_t)(&port->port);
 }
@@ -209,8 +211,7 @@ void sys_mbox_free(sys_mbox_t mbox)
 
 void sys_mbox_post(sys_mbox_t mbox, void *data)
 {
-       if (UNLIKELY(sys_mbox_trypost(mbox, data) == ERR_MEM))
-               LOG_ERR("out of messages!\n");
+       sys_mbox_trypost(mbox, data);
 }
 
 /*
@@ -223,9 +224,18 @@ err_t sys_mbox_trypost(sys_mbox_t mbox, void *data)
 
        PROC_ATOMIC(msg = (IpMsg *)list_remHead(&free_msg));
        if (UNLIKELY(!msg))
+       {
+               LOG_ERR("out of messages!\n");
                return ERR_MEM;
+       }
        msg->data = data;
-       msg_put(mbox, &msg->msg);
+
+       msg_lockPort(mbox);
+       ADDTAIL(&mbox->queue, &msg->msg.link);
+       msg_unlockPort(mbox);
+
+       if (mbox->event.Ev.Sig.sig_proc)
+               event_do(&mbox->event);
 
        return ERR_OK;
 }
@@ -257,13 +267,22 @@ u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **data, u32_t timeout)
                msg = msg_get(mbox);
                if (LIKELY(msg))
                        break;
+
+               mbox->event.Ev.Sig.sig_proc = proc_current();
                /* Slow path */
                if (!timeout)
                        event_wait(&mbox->event);
-               else if (!event_waitTimeout(&mbox->event,
+               else
+               {
+                       if (!event_waitTimeout(&mbox->event,
                                        ms_to_ticks(timeout)))
-                       return SYS_ARCH_TIMEOUT;
+                       {
+                               mbox->event.Ev.Sig.sig_proc = NULL;
+                               return SYS_ARCH_TIMEOUT;
+                       }
+               }
        }
+       mbox->event.Ev.Sig.sig_proc = NULL;
        if (data)
                *data = containerof(msg, IpMsg, msg)->data;
 
@@ -317,6 +336,15 @@ static struct sys_timeouts lwip_system_timeouts; // Default timeouts list for lw
 
 struct sys_timeouts *sys_arch_timeouts(void)
 {
+       ThreadNode *thread_node;
+       struct Process *curr_pid = proc_current();
+
+       FOREACH_NODE(thread_node, &used_thread)
+       {
+               if (thread_node->pid == curr_pid)
+                       return &(thread_node->timeout);
+       }
+
        return &lwip_system_timeouts;
 }
 
@@ -350,6 +378,7 @@ sys_thread_t sys_thread_new(const char *name, void (* thread)(void *arg),
        if (UNLIKELY(!thread_node))
        {
                proc_permit();
+               LOG_ERR("Out of threads!\n");
                return NULL;
        }
        ADDHEAD(&used_thread, &thread_node->node);
@@ -360,7 +389,7 @@ sys_thread_t sys_thread_new(const char *name, void (* thread)(void *arg),
 
        #if !CONFIG_KERN_HEAP
                ASSERT(stacksize <= DEFAULT_THREAD_STACKSIZE);
-               PROC_ATOMIC(stackbase = &thread_stack[last_stack++]);
+               PROC_ATOMIC(stackbase = thread_stack[last_stack++]);
        #else
                stackbase = NULL;
        #endif

diff --git a/doc/README.bertos b/doc/README.bertos
index 131788375e0fbdb3aa553085d8dd43182b337ea5..40a9cb51d3d8d66e7cd4be0a64fbae60c491ab4c 100644 (file)
--- a/doc/README.bertos
+++ b/doc/README.bertos
@@ -40,8 +40,6 @@ designed for fine-grained modularity and minimal external dependencies.
 Most non-essential features can be configured out for applications with small
 memory footprint requirements.
 
-The basic design principles are explained in the \ref oop page.
-
 \section features Features
 
   - multitasking kernel with IPC, semaphores, priority levels;

diff --git a/test/run_tests.sh b/test/run_tests.sh
index 9419451d5b913e70bb051fc22b3ae89d67446cba..c33f00e2a3ed3d3cdc3a53ca60ca1bc42573f458 100755 (executable)
--- a/test/run_tests.sh
+++ b/test/run_tests.sh
@@ -65,16 +65,6 @@ SRC_LIST="
        bertos/io/kblock_ram.c
        bertos/io/kblock_posix.c
        bertos/io/kfile.c
-       bertos/sec/cipher.c
-       bertos/sec/cipher/blowfish.c
-       bertos/sec/cipher/aes.c
-       bertos/sec/kdf/pbkdf1.c
-       bertos/sec/kdf/pbkdf2.c
-       bertos/sec/hash/sha1.c
-       bertos/sec/hash/md5.c
-       bertos/sec/hash/ripemd.c
-       bertos/sec/mac/hmac.c
-       bertos/sec/mac/omac.c
 "
 
 buildout='/dev/null'