sam3 ethernet: remove kludge to fix early sam3x-ek ethernet.

git-svn-id: https://src.develer.com/svnoss/bertos/trunk@4942 38d2e660-2303-0410-9eaa-f027e97ec537

diff --git a/bertos/cpu/cortex-m3/drv/eth_sam3.c b/bertos/cpu/cortex-m3/drv/eth_sam3.c
index f83dba7227d71d4ffe551045eb23d82fd2ab6462..f93275db44304e8b66bde6a4cff8bdff6511ed11 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/eth_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/eth_sam3.c
@@ -234,13 +234,8 @@ static int emac_reset(void)
        pmc_periphEnable(PIOD_ID);
        pmc_periphEnable(EMAC_ID);
 
-       // Disable TESTMODE and RMII
-       PIOC_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
-
-       // Disable PHY power down.
-       PIOD_PER  = BV(PHY_PWRDN_BIT);
-       PIOD_OER  = BV(PHY_PWRDN_BIT);
-       PIOD_CODR = BV(PHY_PWRDN_BIT);
+       // Disable TESTMODE
+       PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
 #endif
 
        // Toggle external hardware reset pin.
@@ -262,9 +257,6 @@ static int emac_reset(void)
        PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
        PIOB_PDR = PHY_MII_PINS_PORTB;
 
-       PIO_PERIPH_SEL(PIOC_BASE, PHY_MII_PINS_PORTC, PIO_PERIPH_A);
-       PIOC_PDR = PHY_MII_PINS_PORTC;
-
        // Enable receive, transmit clocks and RMII mode.
        EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
 #endif

diff --git a/bertos/cpu/cortex-m3/drv/eth_sam3.h b/bertos/cpu/cortex-m3/drv/eth_sam3.h
index a756ffc2b82e78c9d738527e56f1df44510b84e9..7ed89bd57feb4ee3f181e05976c1f7ecc8dd1faa 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/eth_sam3.h
+++ b/bertos/cpu/cortex-m3/drv/eth_sam3.h
@@ -131,17 +131,14 @@
 #define PHY_TXEN_BIT            1
 #define PHY_TXD0_BIT            2
 #define PHY_TXD1_BIT            3
+#define PHY_RXDV_TESTMODE_BIT   4
 #define PHY_RXD0_AD0_BIT        5
 #define PHY_RXD1_AD1_BIT        6
 #define PHY_RXER_RXD4_RPTR_BIT  7
 #define PHY_MDC_BIT             8
 #define PHY_MDIO_BIT            9
-// Port C
-#define PHY_RXDV_TESTMODE_BIT   10
 // Port A
 #define PHY_MDINTR_BIT          5
-// Port D -- FIXME: Only on which revision?
-#define PHY_PWRDN_BIT           18
 
 #define PHY_MII_PINS_PORTB \
        BV(PHY_REFCLK_XT2_BIT) \
@@ -154,9 +151,6 @@
        | BV(PHY_MDC_BIT) \
        | BV(PHY_MDIO_BIT)
 
-#define PHY_MII_PINS_PORTC \
-       BV(PHY_RXDV_TESTMODE_BIT)
-
 #endif /* CPU_ARM_AT91 */
 // \}