* $WIZ$ type = "int"
* $WIZ$ min = 2
*/
-#define CONFIG_UART0_TXBUFSIZE 32
+#define CONFIG_UART0_TXBUFSIZE 16
/**
* Size of the inbound FIFO buffer for port 0 [bytes].
*/
#define CONFIG_UART0_RXBUFSIZE 512
-/**
- * Size of the outbound FIFO buffer for port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
- */
-#define CONFIG_UART1_TXBUFSIZE 32
-
-/**
- * Size of the inbound FIFO buffer for port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
- */
-#define CONFIG_UART1_RXBUFSIZE 32
-
-/**
- * Size of the outbound FIFO buffer for port 2 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2"
- */
-#define CONFIG_UART2_TXBUFSIZE 32
-
-/**
- * Size of the inbound FIFO buffer for port 2 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lm3s or lpc2"
- */
-#define CONFIG_UART2_RXBUFSIZE 32
-
-/**
- * Size of the outbound FIFO buffer for port 3 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lpc2"
- */
-#define CONFIG_UART3_TXBUFSIZE 32
-
-/**
- * Size of the inbound FIFO buffer for port 3 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "lpc2"
- */
-#define CONFIG_UART3_RXBUFSIZE 32
-
-
/**
* Size of the outbound FIFO buffer for SPI port [bytes].
* $WIZ$ type = "int"
* $WIZ$ min = 2
* $WIZ$ supports = "avr"
*/
-#define CONFIG_SPI_TXBUFSIZE 32
+#define CONFIG_SPI_TXBUFSIZE 0
/**
* Size of the inbound FIFO buffer for SPI port [bytes].
* $WIZ$ min = 2
* $WIZ$ supports = "avr"
*/
-#define CONFIG_SPI_RXBUFSIZE 32
-
-/**
- * Size of the outbound FIFO buffer for SPI port 0 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI0_TXBUFSIZE 32
-
-/**
- * Size of the inbound FIFO buffer for SPI port 0 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI0_RXBUFSIZE 32
-
-/**
- * Size of the outbound FIFO buffer for SPI port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI1_TXBUFSIZE 32
-
-/**
- * Size of the inbound FIFO buffer for SPI port 1 [bytes].
- * $WIZ$ type = "int"
- * $WIZ$ min = 2
- * $WIZ$ supports = "at91"
- */
-#define CONFIG_SPI1_RXBUFSIZE 32
+#define CONFIG_SPI_RXBUFSIZE 0
/**
* SPI data order.