#define CPU_HARVARD 0
/// Valid pointers should be >= than this value (used for debug)
- #if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32F103RB || CPU_CM3_AT91SAM3)
+ #if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32F103RB || CPU_CM3_SAM3)
#define CPU_RAM_START 0x20000000
#else
#warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x20000000
#include "clock_lm3s.h"
#elif CPU_CM3_STM32
#include "clock_stm32.h"
-#elif CPU_CM3_AT91SAM3
+#elif CPU_CM3_SAM3
#include "clock_sam3.h"
/*#elif Add other Cortex-M3 CPUs here */
#else
*
* -->
*
- * \brief ATSAM3 clock setup.
+ * \brief Atmel SAM3 clock setup.
*
* \author Stefano Fedrigo <aleph@develer.com>
*/
*
* -->
*
- * \brief Low-level clocking driver for AT91SAM3.
+ * \brief Low-level clocking driver for SAM3.
*
* \author Stefano Fedrigo <aleph@develer.com>
*/
-#ifndef DRV_AT91SAM3_CLOCK_H
-#define DRV_AT91SAM3_CLOCK_H
+#ifndef DRV_SAM3_CLOCK_H
+#define DRV_SAM3_CLOCK_H
void clock_init(void);
-#endif /* DRV_AT91SAM3_CLOCK_H */
+#endif /* DRV_SAM3_CLOCK_H */
#include <io/lm3s.h>
#elif CPU_CM3_STM32
#include <io/stm32.h>
-#elif CPU_CM3_AT91SAM3
+#elif CPU_CM3_SAM3
#include <io/sam3.h>
/*#elif Add other families here */
#else
#include "kdebug_lm3s.c"
#elif CPU_CM3_STM32
#include "kdebug_stm32.c"
-#elif CPU_CM3_AT91SAM3
+#elif CPU_CM3_SAM3
#include "kdebug_sam3.c"
/*#elif Add other families here */
#else
*
* -->
*
- * \brief AT91SAM3 debug support (implementation).
+ * \brief SAM3 debug support (implementation).
*
* \author Stefano Fedrigo <aleph@develer.com>
*/
#define UART_ID UART0_ID
#define UART_PIO_BASE PIOA_BASE
#define UART_PINS (BV(RXD0) | BV(TXD0))
-#elif (CONFIG_KDEBUG_PORT == 1) && !defined(CPU_CM3_AT91SAM3U)
+#elif (CONFIG_KDEBUG_PORT == 1) && !defined(CPU_CM3_SAM3U)
#define UART_BASE UART1_BASE
#define UART_ID UART1_ID
#define UART_PIO_BASE PIOB_BASE
#include "ser_lm3s.h"
#elif CPU_CM3_STM32
#include "ser_stm32.h"
-#elif CPU_CM3_AT91SAM3
+#elif CPU_CM3_SAM3
#include "ser_sam3.h"
/*#elif Add other Cortex-M3 CPUs here */
#else
/* End USART0 macros */
-#if !CPU_CM3_AT91SAM3U
+#if !CPU_CM3_SAM3U
#ifndef SER_UART1_BUS_TXINIT
/**
#define SER_UART1_BUS_TXINIT do { \
PIOA_PDR = BV(RXD1) | BV(TXD1); \
} while (0)
- #elif CPU_CM3_AT91SAM3
+ #elif CPU_CM3_SAM3
#define SER_UART1_BUS_TXINIT do { \
PIOB_PDR = BV(RXD1) | BV(TXD1); \
} while (0)
* Default TXINIT macro - invoked in spi_init()
* The default is no action.
*/
- #if CPU_CM3_AT91SAM3
+ #if CPU_CM3_SAM3
#define SER_SPI0_BUS_TXINIT do { \
/* Disable PIO on SPI pins */ \
PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \
AIC_EOICR = 0; \
} while (0)
-#elif CPU_CM3_AT91SAM3
+#elif CPU_CM3_SAM3
/** Inform hw that we have served the IRQ */
#define SER_INT_ACK do { /* nop */ } while (0)
/* TX and RX buffers */
static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
-#if !CPU_CM3_AT91SAM3U
+#if !CPU_CM3_SAM3U
static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
#endif
};
static ISR_PROTO(uart0_irq_dispatcher);
-#if !CPU_CM3_AT91SAM3U
+#if !CPU_CM3_SAM3U
static ISR_PROTO(uart1_irq_dispatcher);
#endif
static ISR_PROTO(spi0_irq_handler);
enum
{
SER_UART0,
-#if !CPU_CM3_AT91SAM3U
+#if !CPU_CM3_SAM3U
SER_UART1,
#endif
SER_SPI0,
#include <io/lm3s.h>
#elif CPU_CM3_STM32
#include <io/stm32.h>
-#elif CPU_CM3_AT91SAM3
+#elif CPU_CM3_SAM3
#include <io/sam3.h>
/*#elif Add other families here */
#else
+++ /dev/null
-#
-#-*- coding: utf-8 -*-
-#
-# \file
-# <!--
-# This file is part of BeRTOS.
-#
-# Bertos is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-#
-# As a special exception, you may use this file as part of a free software
-# library without restriction. Specifically, if other files instantiate
-# templates or use macros or inline functions from this file, or you compile
-# this file and link it with other files to produce an executable, this
-# file does not by itself cause the resulting executable to be covered by
-# the GNU General Public License. This exception does not however
-# invalidate any other reasons why the executable file might be covered by
-# the GNU General Public License.
-#
-# Copyright 2010 Develer S.r.l. (http://www.develer.com/)
-#
-# -->
-#
-# General CPU info denfinition for Cortex-M3-based LM3S1968 board.
-#
-# This file contain all info for the BeRTOS wizard.
-#
-# \author Andrea Righi <arighi@develer.com>
-#
-#
-
-# Import the common settings for the path.
-include("cm3.common")
-
-# CPU type used for flashing/debugging
-MK_PROGRAMMER_CPU = "sam3"
-MK_FLASH_SCRIPT = PRG_SCRIPTS_DIR + "arm/flash-sam3.sh"
-
-# CPU default clock frequency
-CPU_DEFAULT_FREQ = "48000000UL"
-
-# Special CPU related tags.
-CPU_TAGS += ["sam3"]
-
-# Additional hw drivers.
-MK_CPU_CSRC += DRV_DIR + "clock_sam3.c "
-
-# Short description of the cpu.
-CPU_DESC += [ "256 Kbytes on-chip flash memory",
- "24 Kbytes on-chip SRAM memory" ]
-
-# GCC flags for this cpu.
-MK_CPU_CPPFLAGS += " -D__ARM_AT91SAM3N4__"
-MK_CPU_LDFLAGS += " -T " + SCRIPT_DIR + "at91sam3n4_ram.ld"
--- /dev/null
+#
+#-*- coding: utf-8 -*-
+#
+# \file
+# <!--
+# This file is part of BeRTOS.
+#
+# Bertos is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# As a special exception, you may use this file as part of a free software
+# library without restriction. Specifically, if other files instantiate
+# templates or use macros or inline functions from this file, or you compile
+# this file and link it with other files to produce an executable, this
+# file does not by itself cause the resulting executable to be covered by
+# the GNU General Public License. This exception does not however
+# invalidate any other reasons why the executable file might be covered by
+# the GNU General Public License.
+#
+# Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+#
+# -->
+#
+# General CPU info denfinition for Cortex-M3-based LM3S1968 board.
+#
+# This file contain all info for the BeRTOS wizard.
+#
+# \author Andrea Righi <arighi@develer.com>
+#
+#
+
+# Import the common settings for the path.
+include("cm3.common")
+
+# CPU type used for flashing/debugging
+MK_PROGRAMMER_CPU = "sam3"
+MK_FLASH_SCRIPT = PRG_SCRIPTS_DIR + "arm/flash-sam3.sh"
+
+# CPU default clock frequency
+CPU_DEFAULT_FREQ = "48000000UL"
+
+# Special CPU related tags.
+CPU_TAGS += ["sam3"]
+
+# Additional hw drivers.
+MK_CPU_CSRC += DRV_DIR + "clock_sam3.c "
+
+# Short description of the cpu.
+CPU_DESC += [ "256 Kbytes on-chip flash memory",
+ "24 Kbytes on-chip SRAM memory" ]
+
+# GCC flags for this cpu.
+MK_CPU_CPPFLAGS += " -D__ARM_SAM3N4__"
+MK_CPU_LDFLAGS += " -T " + SCRIPT_DIR + "sam3n4_ram.ld"
#include "lm3s.h"
#elif CPU_CM3_STM32
#include "stm32.h"
-#elif CPU_CM3_AT91SAM3
+#elif CPU_CM3_SAM3
#include "sam3.h"
/*#elif Add other Cortex-M3 CPUs here */
#else
* Peripherals IDs.
*/
/*\{*/
-#if CPU_CM3_AT91SAM3N
+#if CPU_CM3_SAM3N
#define SUPC_ID 0 ///< Supply Controller (SUPC)
#define RSTC_ID 1 ///< Reset Controller (RSTC)
#define RTC_ID 2 ///< Real Time Clock (RTC)
* UART I/O pins
*/
/*\{*/
-#if CPU_CM3_AT91SAM3U
+#if CPU_CM3_SAM3U
#define RXD0 11
#define TXD0 12
#else
* PIO I/O pins
*/
/*\{*/
-#if CPU_CM3_AT91SAM3U
+#if CPU_CM3_SAM3U
#define SPI0_SPCK 15
#define SPI0_MOSI 14
#define SPI0_MISO 13
*
* -->
*
- * \brief ATSAM3 enhanced embedded flash controller definitions.
+ * \brief Atmel SAM3 enhanced embedded flash controller definitions.
*/
#ifndef SAM3_FLASH_H
*
* -->
*
- * \brief AT91SAM3 interrupt definitions.
+ * \brief SAM3 interrupt definitions.
*/
#ifndef SAM3_INTS_H
*
* -->
*
- * \brief ATSAM3 NVIC hardware.
+ * \brief Atmel SAM3 NVIC hardware.
*
* This file does not follow the BeRTOS AT91 register naming convention,
* because the NVIC subsystem is in common with other Cortex-M3 ports.
*
* \author Francesco Sacchi <batt@develer.com>
*
- * ATSAM3 Parallel input/output controller.
+ * Atmel SAM3 Parallel input/output controller.
* This file is based on NUT/OS implementation. See license below.
*/
*
* -->
*
- * \brief AT91SAM3 PMC hardware.
+ * \brief SAM3 PMC hardware.
*/
#ifndef SAM3_PMC_H
*
* \author Francesco Sacchi <batt@develer.com>
*
- * ATSAM3 SPI register definitions.
+ * Atmel SAM3 SPI register definitions.
* This file is based on NUT/OS implementation. See license below.
*/
*
* -->
*
- * \brief ATSAM3 system controller registers.
+ * \brief Atmel SAM3 system controller registers.
*/
#ifndef SAM3_SYSCTL_H
*
* -->
*
- * \brief AT91SAM3 UART hardware.
+ * \brief SAM3 UART hardware.
*/
#ifndef SAM3_UART_H
*/
/*\{*/
#define UART0_BASE 0x400E0600
-#ifndef CPU_CM3_AT91SAM3U
+#ifndef CPU_CM3_SAM3U
#define UART1_BASE 0x400E0800
#endif
/*\}*/
*
* \author Daniele Basile <asterix@develer.com>
*
- * ATSAM3 USART User interface.
+ * Atmel SAM3 USART User interface.
* This file is based on NUT/OS implementation. See license below.
*/
/*
/**
* USART base addresses.
*/
-#if CPU_CM3_AT91SAM3U
+#if CPU_CM3_SAM3U
#define USART0_BASE 0x40090000
#define USART1_BASE 0x40094000
#define USART2_BASE 0x40098000
*
* \author Francesco Sacchi <batt@develer.com>
*
- * ATSAM3 Watchdog.
+ * Atmel SAM3 Watchdog.
* This file is based on NUT/OS implementation. See license below.
*/
*
* -->
*
- * \brief Atmel's ATSAM3 registers definitions.
+ * \brief Atmel's SAM3 registers definitions.
*
* This file derives from the one included in Atmel softpack, and defines
* registers not yet written in standard BeRTOS include file (io/sam3_*.h) with
#define IROM_ADDR (0x00800000u) /* Internal ROM base address */
#define IRAM_ADDR (0x20000000u) /* Internal RAM base address */
-#if CPU_CM3_AT91SAM3N1
+#if CPU_CM3_SAM3N1
#define IFLASH_SIZE 0x10000
#define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */
#define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */
#define IFLASH_NB_OF_PAGES (256) /* Internal FLASH 0 Number of Pages: 256 */
#define IFLASH_NB_OF_LOCK_BITS (4) /* Internal FLASH 0 Number of Lock Bits: 4 */
#define IRAM_SIZE 0x2000
-#elif CPU_CM3_AT91SAM3N2
+#elif CPU_CM3_SAM3N2
#define IFLASH_SIZE 0x20000
#define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */
#define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */
#define IFLASH_NB_OF_PAGES (512) /* Internal FLASH 0 Number of Pages: 512 */
#define IFLASH_NB_OF_LOCK_BITS (8) /* Internal FLASH 0 Number of Lock Bits: 8 */
#define IRAM_SIZE 0x4000
-#elif CPU_CM3_AT91SAM3N4
+#elif CPU_CM3_SAM3N4
#define IFLASH_SIZE 0x40000
#define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */
#define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */
+++ /dev/null
-/**
- * \file
- * <!--
- * This file is part of BeRTOS.
- *
- * Bertos is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * As a special exception, you may use this file as part of a free software
- * library without restriction. Specifically, if other files instantiate
- * templates or use macros or inline functions from this file, or you compile
- * this file and link it with other files to produce an executable, this
- * file does not by itself cause the resulting executable to be covered by
- * the GNU General Public License. This exception does not however
- * invalidate any other reasons why the executable file might be covered by
- * the GNU General Public License.
- *
- * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
- *
- * -->
- *
- * \author Stefano Fedrigo <aleph@develer.com>
- *
- * \brief Linker script for AT91SAM3N4 Cortex M3 processor.
- *
- */
-
-/*
- * Memory configuration for AT91SAM3N4.
- */
-MEMORY
-{
- rom(rx) : org = 0x0, len = 256k
- ram(rwx) : org = 0x20000000, len = 24k
-}
-
-INCLUDE "bertos/cpu/cortex-m3/scripts/cortex-m3_ram.ld"
-
+++ /dev/null
-/**
- * \file
- * <!--
- * This file is part of BeRTOS.
- *
- * Bertos is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * As a special exception, you may use this file as part of a free software
- * library without restriction. Specifically, if other files instantiate
- * templates or use macros or inline functions from this file, or you compile
- * this file and link it with other files to produce an executable, this
- * file does not by itself cause the resulting executable to be covered by
- * the GNU General Public License. This exception does not however
- * invalidate any other reasons why the executable file might be covered by
- * the GNU General Public License.
- *
- * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
- *
- * -->
- *
- * \author Stefano Fedrigo <aleph@develer.com>
- *
- * \brief Linker script for AT91SAM3N4 Cortex M3 processor.
- *
- */
-
-/*
- * Memory configuration for AT91SAM3N4.
- */
-MEMORY
-{
- rom(rx) : org = 0x0, len = 256k
- ram(rwx) : org = 0x20000000, len = 24k
-}
-
-INCLUDE "bertos/cpu/cortex-m3/scripts/cortex-m3_rom.ld"
-
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \author Stefano Fedrigo <aleph@develer.com>
+ *
+ * \brief Linker script for Atmel SAM3N4 Cortex M3 processor.
+ *
+ */
+
+/*
+ * Memory configuration for SAM3N4.
+ */
+MEMORY
+{
+ rom(rx) : org = 0x0, len = 256k
+ ram(rwx) : org = 0x20000000, len = 24k
+}
+
+INCLUDE "bertos/cpu/cortex-m3/scripts/cortex-m3_ram.ld"
+
--- /dev/null
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \author Stefano Fedrigo <aleph@develer.com>
+ *
+ * \brief Linker script for Atmel SAM3N4 Cortex M3 processor.
+ *
+ */
+
+/*
+ * Memory configuration for SAM3N4.
+ */
+MEMORY
+{
+ rom(rx) : org = 0x0, len = 256k
+ ram(rwx) : org = 0x20000000, len = 24k
+}
+
+INCLUDE "bertos/cpu/cortex-m3/scripts/cortex-m3_rom.ld"
+
#define CPU_CM3_STM32F103RB 0
#endif
- #if defined (__ARM_AT91SAM3N4__)
- #define CPU_CM3_AT91SAM3 1
- #define CPU_CM3_AT91SAM3N 1
- #define CPU_CM3_AT91SAM3N4 1
- #define CPU_NAME "AT91SAM3N4"
-
- #define CPU_CM3_AT91SAM3S 0
- #define CPU_CM3_AT91SAM3U 0
- #define CPU_CM3_AT91SAM3N2 0
- #define CPU_CM3_AT91SAM3N1 0
+ #if defined (__ARM_SAM3N4__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3N 1
+ #define CPU_CM3_SAM3N4 1
+ #define CPU_NAME "SAM3N4"
+
+ #define CPU_CM3_SAM3S 0
+ #define CPU_CM3_SAM3U 0
+ #define CPU_CM3_SAM3N2 0
+ #define CPU_CM3_SAM3N1 0
#else
- #define CPU_CM3_AT91SAM3N4 0
+ #define CPU_CM3_SAM3N4 0
#endif
- #if defined (__ARM_AT91SAM3S4__)
- #define CPU_CM3_AT91SAM3 1
- #define CPU_CM3_AT91SAM3S 1
- #define CPU_CM3_AT91SAM3S4 1
- #define CPU_NAME "AT91SAM3S4"
+ #if defined (__ARM_SAM3S4__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3S 1
+ #define CPU_CM3_SAM3S4 1
+ #define CPU_NAME "SAM3S4"
- #define CPU_CM3_AT91SAM3N 0
- #define CPU_CM3_AT91SAM3U 0
+ #define CPU_CM3_SAM3N 0
+ #define CPU_CM3_SAM3U 0
#else
- #define CPU_CM3_AT91SAM3S4 0
+ #define CPU_CM3_SAM3S4 0
#endif
- #if defined (__ARM_AT91SAM3U4__)
- #define CPU_CM3_AT91SAM3 1
- #define CPU_CM3_AT91SAM3U 1
- #define CPU_CM3_AT91SAM3U4 1
- #define CPU_NAME "AT91SAM3U4"
+ #if defined (__ARM_SAM3U4__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3U 1
+ #define CPU_CM3_SAM3U4 1
+ #define CPU_NAME "SAM3U4"
- #define CPU_CM3_AT91SAM3N 0
- #define CPU_CM3_AT91SAM3S 0
+ #define CPU_CM3_SAM3N 0
+ #define CPU_CM3_SAM3S 0
#else
- #define CPU_CM3_AT91SAM3U4 0
+ #define CPU_CM3_SAM3U4 0
#endif
#if defined (CPU_CM3_LM3S)
#error Luminary Cortex-M3 CPU configuration error
#endif
#define CPU_CM3_STM32 0
- #define CPU_CM3_AT91SAM3 0
+ #define CPU_CM3_SAM3 0
#elif defined (CPU_CM3_STM32)
#if CPU_CM3_STM32F103RB + 0 != 1
#error STM32 Cortex-M3 CPU configuration error
#endif
#define CPU_CM3_LM3S 0
- #define CPU_CM3_AT91SAM3 0
- #elif defined (CPU_CM3_AT91SAM3)
- #if CPU_CM3_AT91SAM3N + 0 != 1
- #error AT91SAM3 Cortex-M3 CPU configuration error
+ #define CPU_CM3_SAM3 0
+ #elif defined (CPU_CM3_SAM3)
+ #if CPU_CM3_SAM3N + 0 != 1
+ #error SAM3 Cortex-M3 CPU configuration error
#endif
- #if CPU_CM3_AT91SAM3N4 + CPU_CM3_AT91SAM3S4 + CPU_CM3_AT91SAM3U4 + 0 != 1
- #error AT91SAM3 Cortex-M3 CPU configuration error
+ #if CPU_CM3_SAM3N4 + CPU_CM3_SAM3S4 + CPU_CM3_SAM3U4 + 0 != 1
+ #error SAM3 Cortex-M3 CPU configuration error
#endif
#define CPU_CM3_LM3S 0
#define CPU_CM3_STM32 0
#else
#define CPU_CM3_LM3S 0
#define CPU_CM3_STM32 0
- #define CPU_CM3_AT91SAM3 0
+ #define CPU_CM3_SAM3 0
#endif
- #if CPU_CM3_LM3S + CPU_CM3_STM32 + CPU_CM3_AT91SAM3 + 0 /* Add other Cortex-M3 families here */ != 1
+ #if CPU_CM3_LM3S + CPU_CM3_STM32 + CPU_CM3_SAM3 + 0 /* Add other Cortex-M3 families here */ != 1
#error Cortex-M3 CPU configuration error
#endif
#define CPU_CM3_STM32 0
#define CPU_CM3_STM32F103RB 0
- #define CPU_CM3_AT91SAM3 0
- #define CPU_CM3_AT91SAM3N 0
- #define CPU_CM3_AT91SAM3N4 0
+ #define CPU_CM3_SAM3 0
+ #define CPU_CM3_SAM3N 0
+ #define CPU_CM3_SAM3N4 0
#endif
#if (defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)) \
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